Chapter 3

3.1. (a)
x1 x2 x3 f

0 0 0 0 1 1 1 1 (b)

0 0 1 1 0 0 1 1

0 1 0 1 0 1 0 1

0 1 1 0 1 0 0 1

#transistors = NOT gates 2 + AND gates 8 + OR gates = 3 2 + 4 8 + 1 10 = 48

3.2. (a) In problem 3.1 the canonical SOP for f is

f = x1 x2 x3 + x1x2 x3 + x1x2x3 + x1x2x3

This expression is equivalent to f in Figure P3.2, as derived below.
x1 x2 x2 x3 + x2 x3

x3

x3

x1 x2 x3 + x1 x2 x3 + x1 x2 x3 + x1 x2 x3

x2 x3 + x2 x3

(b) Assuming the multiplexers are implemented using transmission gates

#transistors = NOT gates 2 + MUXes 6 = 1 2 + 3 6 = 20

3-1

3.3. (a) A SOP expression for f in Figure P3.3 is:

f = (x1 x2 ) x3 = (x1 x2 )x3 + (x1 x2 )x3 = x1 x2 x3 + x1x2 x3 + x1 x2x3 + x1x2x3

which is equivalent to the expression derived in problem 3.2. (b) Assuming the XOR gates are implemented as shown in Figure 3.61b

#transistors = XOR gates 8 = 2 8 = 16

3.4. Using the circuit

The number of transistors needed is 16. 3.5. Using the circuit

The number of transistors needed is 20. 3.6. (a)

x1 x2 x3 f

0 0 0 0 1 1 1 1

0 0 1 1 0 0 1 1

0 1 0 1 0 1 0 1

1 1 1 1 1 0 0 0

3-2

(b) The canonical SOP expression is

f = x1 x2 x3 + x1x2 x3 + x1x2 x3 + x1 x2x3 + x1 x2 x3

The number of transistors required using only AND, OR, and NOT gates is

#transistors = NOT gates 2 + AND gates 8 + OR gates 12 = 3 2 + 5 8 + 1 12 = 58

3.7. (a)

x1 x2 x3 x4

x1 x2 x3 x4

0 0 0 0 0 0 0 0 (b)

0 0 0 0 1 1 1 1

0 0 1 1 0 0 1 1

0 1 0 1 0 1 0 1

1 0 0 0 1 0 0 0

1 1 1 1 1 1 1 1

0 0 0 0 1 1 1 1

0 0 1 1 0 0 1 1

0 1 0 1 0 1 0 1

1 0 0 0 0 0 0 0

f = x1 x2x3 x4 + x1 x2x3 x4 + x1x2x3 x4 = x1 x3x4 + x2 x3 x4

The number of transistors required using only AND, OR, and NOT gates is

#transistors = NOT gates 2 + AND gates 8 + OR gates 4 = 4 2 + 2 8 + 1 4 = 28

3.8.
VDD

Vx Vx Vx

3 2

Vf

3-3

3.9.
Vx Vx
3

Vf

Vx Vx

3.10. Minimum SOP expression for f is

f = x2x3 + x1 x3 + x2 x4 + x1 x4 = (x1 + x2)(x3 + x4)

which leads to the circuit
VDD

Vf Vx Vx Vx Vx

3.11. Minimum SOP expression for f is

f = x4 + x1 x2 x3
which leads to the circuit

3-4

VDD

Vf Vx Vx Vx Vx
4

3.12.
VDD VDD

Vf Vx Vy

Vz

3-5

3.13.
VDD VDD

Vy Vx Vz

Vy

Vz

Vf Vz Vy Vy

Vx

Vz

3.14. (a) Since VDS

3.15. (a) Since VDS

VGS ; VT the NMOS transistor is operating in the saturation region: ID = 1 kn W (VGS ; VT )2 2 L = 10 VA 5 (5 V ; 1 V)2 = 800 A 2 (b) In this case VDS < VGS ; VT , thus the NMOS transistor is operating in the triode region: 2 ID = kn W (VGS ; VT )VDS ; 1 VDS L 2 = 20 VA 5 (5 V ; 1 V) 0:2 V ; 1 (0:2 V)2 = 78 A 2 2
0 0 0

VGS ; VT the PMOS transistor is operating in the saturation region: ID = 1 kp W (VGS ; VT )2 2 L = 5 VA 5 (;5 V + 1 V)2 = 400 A 2 (b) In this case VDS > VGS ; VT , thus the PMOS transistor is operating in the triode region: 1 2 ID = kp W (VGS ; VT )VDS ; 2 VDS L = 10 VA 5 (;5 V + 1 V) (;0:2) V ; 1 (;0:2 V)2 = 39 A 2 2
0

3-6

3.16.

RDS = 1= kn W (VGS ; VT ) L = 1= 0:020 mA 10 (5 V ; 1 V) = 1:25 k V2

0

3.17.

RDS = 1= kn W (VGS ; VT ) L = 1= 0:040 mA 10 (3:3 V ; 0:66 V) = 947 V2

0

3.18. Since VDS

Hence the value of RDS is

< (VGS ; VT ), the PMOS transistor is operating in the saturation region: ISD = 1 kp W (VGS ; VT )2 2 L = 50 VA (;5 V + 1 V)2 = 800 A 2
0

RDS = VDS =IDS = 4:8 V=800 A = 6 k

3.19. Since VDS

Hence the value of RDS is

< (VGS ; VT ), the PMOS transistor is operating in the saturation region: 1 ISD = 2 kp W (VGS ; VT )2 L A (;3:3 V + 0:66 V)2 = 558 A = 80 V2
0

RDS = VDS =IDS = 3:2 V=558 A = 5:7 k

3.20. The low output voltage of the pseudo-NMOS inverter can be obtained by setting V x = VDD and evaluating the voltage Vf . First we assume that the NMOS transistor is operating in the triode region while the PMOS is operating in the saturation region. For simplicity we will assume that the magnitude of the threshold voltages for both the NMOS and PMOS transistors are equal, so that

VT = VT N = ;VT P
The current owing through the PMOS transistor is

ID = 1 kp Wp (;VDD ; VT P )2 2 Lp = 1 kp (;VDD ; VT P )2 2 = 1 kp (VDD ; VT )2 2

0

3-7

Similarly, the current going through the NMOS transistor is

ID = kn Wn (Vx ; VT N )Vf ; 1 Vf2 Ln 2 = kn (Vx ; VT N )Vf ; 1 Vf2 2 = kn (VDD ; VT )Vf ; 1 Vf2 2

0

Since there is only one path for current to ow, we can equate the currents owing through the NMOS and PMOS transistors and solve for the voltage Vf .

kp(VDD ; VT )2 ; 2kn(VDD ; VT )Vf + knVf2 = 0

This quadratic equation can be solved using the standard formula, with the parameters

1 kp (VDD ; VT )2 = 2kn (VDD ; VT )Vf ; 2 Vf2

a = kn b = ;2kn(VDD ; VT ) c = kp (VDD ; VT )2
which gives

Vf = ;b 2a

b2 ; c 4a2 r a k = (VDD ; VT ) (VDD ; VT )2 ; k p (VDD ; VT )2 = (VDD ; VT ) 1

" r

k 1 ; kp
"

Only one of these two solutions is valid, because we started with the assumption that the NMOS transistor is in the triode region while the PMOS is in the saturation region. Thus

k Vf = (VDD ; VT ) 1 ; 1 ; k p n
3.21. (a)
0

(b)

Istat = 1 kp Wp (VDD ; VT )2 2 Lp = 12 VA 1 (5 V ; 1 V)2 = 192 A 2 RDS = 1= kn Wn (VGS ; VT ) Ln = 1= 0:060 mA 4 (5 V ; 1 V) = 1:04 k V2

0

(c) Using the expression derived in problem 3.20

0

kp = kp Wp = 24 VA 2 Lp kn = kn Wn = 240 VA 2 Ln
0

3-8

VOL = Vf
(d)

24 = (5 V ; 1 V) 1 ; 1 ; 240 = 0:21 V

"

PD = IstatVDD = 192 A 5 V = 960 W 1mW

(e)

RSD P = VSD =ISD = (VDD ; Vf )=Istat = (5 V ; 0:21 V)=0:192 mA = 24:9 k

(f ) The low-to-high propagation delay is

tpLH = =
The high-to-low propagation delay is

kp Wpp VDD L
0

1:7C

1:7 70 fF = 0:99 ns 24 VA 1 5 V 2 1:7C

tpHL = =
3.22. (a)

n kn Wn VDD L
0

1:7 70 fF = 0:1 ns 60 VA 4 5 V 2
0

Istat = 1 kp Wp (VDD ; VT )2 2 Lp = 48 VA 1 (5 V ; 1 V)2 = 768 A 2

(b)

RDS = 1= kn Wn (VGS ; VT ) Ln = 1= 0:060 mA 4 (5 V ; 1 V) = 1:04 k V2

0

(c) Using the expression derived in problem 3.20

kp = kp Wp = 96 VA kn = kn Wn = 240 VA 2 2 L L
0 0

3-9

VOL = Vf
(d)

96 = (5 V ; 1 V) 1 ; 1 ; 240 = 0:90 V

"

PD = IstatVDD = 768 A 5 V = 3840 W 3:8mW

(e)

RSD P = VSD =ISD = (VDD ; Vf )=Istat = (5 V ; 0:90 V)=0:768 mA = 5:34 k

(f ) The low-to-high propagation delay is

tpLH = =
The high-to-low propagation delay is

0 kp Wpp VDD L

1:7C

1:7 70 fF = 0:25 ns 96 VA 1 5 V 2

tpHL =

1:7C n kn Wn VDD L 1:7 70 fF = 0:1 ns = 60 VA 4 5 V 2

0 0

3.23. (a)

Istat = 1 kp Wp (VDD ; VT )2 2 Lp = 12 VA 1 (5 V ; 1 V)2 = 192 A 2 RDS = 1= kn Wn (VGS ; VT ) Ln = 1= 0:060 mA 2 (5 V ; 1 V) = 2:08 k V2

0

(b) The two NMOS transistors in series can be considered equivalent to a single transistor with twice the length. Thus

(c) Using the expression derived in problem 3.20

0

kp = kp Wp = 24 VA 2 Lp kn = kn Wn = 120 VA 2 Ln
0

3-10

VOL = Vf
(d)

24 = (5 V ; 1 V) 1 ; 1 ; 120 = 0:42 V

"

PD = IstatVDD = 192 A 5 V = 960 W 1mW

(e)

RSDP = VSD =ISD = (VDD ; Vf )=Istat = (5 V ; 0:42 V)=0:192 mA = 23:9 k

(f ) The low-to-high propagation delay is

tpLH = =
The high-to-low propagation delay is

kp Wpp VDD L
0

1:7C

1:7 70 fF = 0:99 ns 24 VA 1 5 V 2 1:7C

tpHL = =
3.24. (a)

n kn Wn VDD L
0

1:7 70 fF = 0:2 ns 60 VA 2 5 V 2
0

Istat = 1 kp Wp (VDD ; VT )2 2 Lp = 12 VA 1 (5 V ; 1 V)2 = 192 A 2 RDS = 1= kn Wn (VGS ; VT ) Ln = 1= 0:060 mA 8 (5 V ; 1 V) = 520 V2

0

(b) The two NMOS transistors in parallel can be considered equivalent to a single transistor with twice the width. Thus

(c) Using the expression derived in problem 3.20

0

kp = kp Wp = 24 VA 2 Lp kn = kn Wn = 480 VA 2 Ln
0

3-11

VOL = Vf
(d)

24 = (5 V ; 1 V) 1 ; 1 ; 480 = 0:10 V

"

PD = IstatVDD = 192 A 5 V = 960 W 1mW

(e)

RSD P = VSD =ISD = (VDD ; Vf )=Istat = (5 V ; 0:10 V)=0:192 mA = 25:5 k

(f ) The low-to-high propagation delay is

tpLH = =
The high-to-low propagation delay is

kp Wpp VDD L
0

1:7C

1:7 70 fF = 0:99 ns 24 VA 1 5 V 2

tpHL =

1:7C n kn Wn VDD L 1:7 70 fF = 0:05 ns = 60 VA 8 5 V 2

0

3.25. (a)

NM H = VOH ; VIH = 0:5 V NM L = VIL ; VOL = 0:7 V

(b)

VOL = 8 0:1 V = 0:8 V NM L = 1 V ; 0:8 V = 0:2 V

3.26. Under steady-state conditions, for an n-input CMOS NAND gate the voltage levels VOL and VOH are 0 V and VDD , respectively. No current ows in a CMOS gate in the steady-state. Thus there can be no voltage drop across any of the transistors. 3.27. (a)

PNOT
(b)

gate

= fCV 2 = 75 MHz 150 fF (5 V)2 = 281 W

Ptotal = 0:2 250 000 281 W = 14 W

3-12

3.28. (a)

PNOT
(b)

gate

= fCV 2 = 125 MHz 120 fF (3:3 V)2 = 163 W

Ptotal = 0:2 250 000 163 W = 8:2 W tpHL = tpLH =

n kn Wn VDD L
0

3.29. (a) The high-to-low propagation delay is

1:7C

(b) The low-to-high propagation delay is

0

1:7 150 fF = 0:255 ns 20 VA 10 5 V 2

(c) For equivalent high-to-low and low-to-high delays

kp Wpp VDD L

1:7C

= 1:7 150 fF = 0:638 ns 8 VA 10 5 V 2

tpHL = tpLH 1:7C 1:7C = Wp n kn Wn VD D kp Lp VD D L k Wp = kn Wn p Lp Ln 12:5 m = 0:5 m

0 0
0 0

3.30. (a) The high-to-low propagation delay is

tpHL = tpLH =

(b) The low-to-high propagation delay is

1:7C = 1:7 150 fF = 0:193 ns n kn Wn VDD 40 VA 10 3:3 V 2 L

0 0 kp Wpp VDD L

1:7C

1:7 150 fF = 0:483 ns 16 VA 10 3:3 V 2

(c) For equivalent high-to-low and low-to-high delays

tpHL = tpLH 1:7C 1:7C Wn V D = Wp kn Ln D kp Lp VD D k Wp = kn Wn p Lp Ln 8:75 m = 0:35 m

0 0
0 0

3-13

3.31. The two PMOS transistors in a CMOS NAND gate are connected in parallel. The worst case current to drive the output high happens when only one of these transistors is turned ON. Thus each transistor has to have Wp the same dimensions as the PMOS transistor in the inverter, namely Lp = 4.

n The two NMOS transistors are connected in series. If each one had the ratio Wn , then the two transistors L W could be thought of as one equivalent transistor with a 2Ln ratio. Thus each NMOS transistor must have n Wn = 4. twice the width of that in the inverter, namely Ln

3.32. The two NMOS transistors in a CMOS NOR gate are connected in parallel. The worst case current to drive the output low happens when only one of these transistors is turned ON. Thus each transistor has to have n the same dimensions as the NMOS transistor in the inverter, namely Wn = 2. L Wp The two PMOS transistors are connected in series. If each of these transistors had the ratio Lp , then the two W transistors could be thought of as one transistor with a 2Lp ratio. Thus each PMOS transistor must be made p n twice as wide as that in the inverter, namely Wn = 8. L 3.33. The worst case path in the PMOS network contains two transistors in series. Thus each PMOS transistor must be twice as wide the transistors in the inverter. The worst case path in the NMOS network also contains two transistors in series. Similarly, each NMOS transistor must be twice as wide as those in the inverter. 3.34. The worst case PMOS path contains three transistors in series so each transistor must be three times as wide as the PMOS transistors in the inverter. The worst case NMOS path contains two transistors in series. Thus the NMOS transistors must be two times as wide. 3.35. (a) The current owing through the inverter is equal to the current owing through the PMOS transistor. We shall assume that the PMOS transistor is operating in the saturation region.

(b) The current owing through the NMOS transistor is equal to the static current I stat. Assume that the NMOS transistor is operating in the triode region.

1 Istat = 2 kp Wp (VGS ; VTp )2 Lp = 120 VA ((3:5 V ; 5 V) + 1 V)2 = 30 A 2

0

1 2 Istat = kn Wn (VGS ; VTn )VDS ; 2 VDS Ln 1 30 A = 240 VA 2:5 V Vf ; 2 Vf2 2

0

1 = 20Vf ; 4Vf2

Solving this quadratic equation yields V f = 0:05V. Note that the output voltage V f satises the assumption that the PMOS transistor is operating in the saturation region while the NMOS transistor is operating in the triode region. (c) The static power dissipated in the inverter is

PS = IstatVDD = 30 A 5 V = 150 W
(d) The static power dissipated by 250,000 inverters.

250 000 Ps = 37:5 W

3-14

3.36.
x1 x2 x3 NOR plane VDD VDD

P1 P2 P3 P4

NOR plane

f1

f2

3.37.
x1 x2 x3 NOR plane VDD VDD

P1 P2 P3 P4

NOR plane

f1

f2

3-15

3.38.
x1 x2 x3 NOR plane VDD VDD

S1 S2 S3 S4

NOR plane

f1

f2

3.39.
x1 x2 x3 NOR plane VDD VDD

S1 S2 S3 S4

NOR plane

f1

f2

3-16

3.40.
VDD

x1

x2

x3

NOR plane VDD

VDD

VDD

VDD

NOR plane

f1

3.41.
VDD

x1

x2

x3

NOR plane VDD

VDD

VDD

VDD

NOR plane

f1

3-17

3.42.

f2 f2 f2 f2 f2 f2 f2 f2 f2 f2 f2 f2 f2 f2 f2
3.43.

= = = = = = = = = = = = = = = = = = = = = = = = = = = = = =

m1 m2 m4 m7 m1 + m2 m1 + m4 m1 + m7 m2 + m4 m2 + m7 m4 + m7 m1 + m2 + m4 m1 + m2 + m7 m1 + m4 + m7 m2 + m4 + m7 m1 + m2 + m4 + m7 m0 m3 m5 m6 m0 + m3 m0 + m5 m0 + m6 m3 + m4 m3 + m6 m5 + m6 m0 + m3 + m5 m0 + m3 + m6 m0 + m5 + m6 m3 + m5 + m6 m0 + m3 + m5 + m6

f2 f2 f2 f2 f2 f2 f2 f2 f2 f2 f2 f2 f2 f2 f2

3-18

3.44.
x1 x2

0 0 1 0 0 0 0 1 0 0 1 0

x1 x2

x1 x3

0 1 1 1
x1 x3

x1 x2 + x1 x3

0 1 1 1

x1 x2 + x1 x3 + x2 x3

x2 x3

x2 x3

3.45. The canonical SOP for f is

f = x1 x2x3 + x1x2 x3 + x1x2 x3 + x1x2x3 + x1 x2x3

This expression can be manipulated into

f = x1 x2 + x1x3 + x1 x2 = x2 + x1x3
The circuit is
x1 x3

0 0 1 0

x1 x3

x2

0 1 1 1

x2 + x1 x3

3.46. The canonical SOP for f is

f = x1x2 x4 + x2x3 x4 + x1 x2x3 f = x2 (x1 x4 + x3x4 ) + x2 (x1x3 )

This expression can be manipulated into

Using functional decomposition we have

f = x2f1 + x2 f2
where

f1 = x1 x4 + x3x4 f2 = x1 x3
3-19

The circuit is
x1 x3 x4 x1 x4 + x3 x4

x1 x2 x4 + x2 x3 x4 + x1 x2 x3

0 x1 x3 x2 x1 x3

3.47. The canonical SOP for f is

f = x1x2 x4 + x2x3 x4 + x1 x2x3 f = x2 (x1 x4 + x3x4 ) + x2 (x1x3 )

This expression can be manipulated into

Using functional decomposition we have

f = x2f1 + x2 f2
where

f1 = x1 x4 + x3x4 f2 = x1 x3 The function f1 requires one 2-LUT, while f2 requires three 2-LUTs. We then need three additional 3-LUTs to realize f , as illustrated in the circuit
x1 x4 x1 x4 x1 x4 + x3 x4 x1 x2 x4 + x3 x2 x4 x3 x4 x2 x1 x3 x1 x3 x1 x2 x3 x3 x4 x1 x2 x4 + x2 x3 x4 + x1 x2 x3

3.48.

g h j k

= = = =

x2 x3 x1 x2 x3

3-20

3.49. (a)

x2 0

x1

x1 0 + x1 x2

x3 x1 x2 + x3 1 = x1 x2 + x3

x3

(b)

x3

x3 0 + x3 ( x1 + x2 ) = x1 x3 + x2 x3

x1 x2 + x1 1 = x1 + x2

x2 1

x1

3.50. (a)

x1 x2 1 1 x3 1 1

x1 x2

x1 x2 x3 = x1 x2 + x3

x3

3-21

(b)
x1 x2 x4 x1 x2 x3 x4 1 1 x4 x2 x3 x4 x1 x2 x4 x1 x2 x3 x4 = x1 x2 x4 + x1 + x2 x3 x4 x1 x2 x4

3.51.

LIBRARY ieee ; USE ieee.std logic 1164.all ; ENTITY prob3 51 IS PORT ( x1, x2, x3, x4 : IN STD LOGIC ; f : OUT STD LOGIC ) ; END prob3 51 ; ARCHITECTURE LogicFunc OF prob3 51 IS BEGIN f <= (x2 AND NOT x3 AND NOT x4) OR (NOT x1 AND x2 AND x4) OR (NOT x1 AND x2 AND x3) OR (x1 AND x2 AND x3) ; END LogicFunc ;

3.52.

LIBRARY ieee ; USE ieee.std logic 1164.all ; ENTITY prob3 52 IS PORT ( x1, x2, x3, x4 : IN STD LOGIC ; f : OUT STD LOGIC ) ; END prob3 52 ; ARCHITECTURE LogicFunc OF prob3 52 IS BEGIN f <= (x1 OR x2 OR NOT x4) AND (NOT x2 OR x3 OR NOT x4) AND (NOT x1 OR x3 OR NOT x4) AND (NOT x1 OR NOT x3 OR NOT x4) ; END LogicFunc ;

3-22

3.53.

LIBRARY ieee ; USE ieee.std logic 1164.all ; ENTITY prob3 53 IS PORT ( x1, x2, x3, x4, x5, x6, x7 : IN STD LOGIC ; f : OUT STD LOGIC ) ; END prob3 53 ; ARCHITECTURE LogicFunc OF prob3 53 IS BEGIN f <= (x1 AND x3 AND NOT x6) OR (x1 AND x4 AND x5 AND NOT x6) OR (x2 AND x3 AND x7) OR (x2 AND x4 AND x5 AND x7) ; END LogicFunc ;

3.54. The circuit in Figure P3.10 is a two-input XOR gate. Since NMOS transistors are used only to pass logic 0 and PMOS transistors are used only to pass logic 1, the circuit does nor suffer from any major drawbacks. 3.55. The circuit in Figure P3.11 is a two-input XOR gate. This circuit has two drawbacks: when both inputs are 0 the PMOS transistor must drive f to 0, resulting in f = V T volts. Also, when x1 = 1 and x2 = 0, the NMOS transistor must drive the output high, resulting in f = V DD ; VT .

3-23