Technotran

A Full Semester Internship report on

VLSI Design
Submitted in a partial fulfillment for the award of the degree
BACHELOR OF TECHNOLOGY

IN
ELECTRONICS AND COMMUNICATION ENGINEERING
Submitted by

PAVULURU VENKATA CHAITHANYA

(202H1A0499)
Under the esteemed Guidance of
Ms. P. Sree Lakshmi, M.Tech, Ph.D,
Associate Professor, Dept. of ECE

DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING

(AUTONOMOUS)

NH5 Bypass Road, Gudur – 524101, Tirupati (DT.)

Andhra Pradesh
www.audisankara.ac.in
2023-2024

1
 (AUTONOMOUS)
NH5 Bypass Road, Gudur – 524101, Tirupati (DT.)
Department of Electronics and Communication Engineering

CERTIFICATE
This is to certify that the Full Semester Internship report on entitled “ VLSI Design”
is the bonafide work done by the student PAVULURU VENKATA CHAITHANYA
, REGD NO : 202H1A0499, in partial fulfillment of the requirements for the award
of the degree of Bachelor of Technology in Electronics and Communication
Engineering, from Jawaharlal Nehru Technological University Anantapur,
Anantapuramu, during the year 2023-2024.

Internship Guide Head of the Department

Ms. P. Sree Lakshmi, M.Tech, Ph.D Prof. J. AMARENDRA M.Tech., (P.HD)
Associate Professor, Associate Professor & HOD,
Department of ECE Department of ECE,
ASIT, GUDUR – TIRUPATI (DT). ASIT, GUDUR-TIRUPATI(DT).

Submitted for the viva-voce Examination held on:

Internal Examiner External Examiner

2
 DECLARATION

I, PAVULURU VENKATA CHAITHANYA, REG NO:-202H1A0499, hereby

declare that the Project Work entitled “VLSI Design” done by us under the esteemed
Guidance of Ms. P. Sree Lakshmi, M.Tech, Ph.D Associate professor Department of
ECE . The Full Semester Internship report is submitted in partial fulfillment of the
requirements for the award of the bachelor’s degree in Electronics and Communication
Engineering.

Date:

Place:

Signature of the candidate

PAVULURU VENKATA CHAITHANYA

(202H1A0499)

3
 ACKNOWLEDGEMENT
The satisfaction and elation that accompany the successful completion of any task would be incomplete
without the mention of the people who have made it a possibility. It is our great privilege to express our
gratitude and respect to all those who have guided us and inspired us during the course of this project Working
towards Industry/Research Internship has been a period of various challenges that have led to a great deal of
learning and professional growth. Making it through would not have been possible without the help and
support of family and friends.
First and Foremost, I would like to express my deep and sincere thanks to the team of Directors of
Technotran, India for giving me the opportunity to do an internship within the organization .I express my
sincere gratitude and thanks to our honorable Chairman Dr. VANKI PENCHALAIAH, M.A.,M.L.,Ph.D.,
for providing facilities and necessary encouragement during the Full semester Internship Program.I am highly
indebted to Director Dr. A. MOHAN BABU, Ph.D., and Principal Prof. K.DHANUNJAYA, M. Tech,
(Ph.D.), for the facilities provided to accomplish this internship. I would like to thank my Head of the
Department Prof. J.AMARENDRA, M.Tech, (Ph.D), for his constant support and guidance throughout my
internship. I would like to thank Ms. P. Sree Lakshmi, M.Tech, Ph.D Internship coordinator, Department of
ECE for their support and advice to get and complete internship in above said organization.
I would like to convey my heartfelt gratitude to external supervisor and mentor, for having accepted me as
Industry/Research Internship report student and providing unconditional support and guidance regarding all
aspects of internship and career.
I also would like all the people that worked along with me in Technotran, Nellore with their patience and
openness they created an enjoyable and learning oriented ambience online. It is indeed with a great sense of
pleasure and immense sense of gratitude that I acknowledge the help of these individuals. I am extremely great
full to my department staff members and friends who helped me in successful completion of this internship .

PAVULURU VENKATA CHAITHANYA

(202H1A0499)

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 PROFILE OF THE COMPANY

Name of the Company With Address:

Technotran,
Magunta Layout, Nellore, Andhra Pradesh-524003
Mail:- info@technotran.in

"Technotran, (an ISO 9001:2015 Certified Company), is a leading Educational Technology firm specializing
in Embedded Systems, 3D Printing, Robotics, IoT, and Artificial Intelligence. We serve universities, colleges,
and schools nationwide. Our unwavering commitment revolves around delivering toptier services,
encompassing DIY Robotic kit design, electronic product design, PCB Design, prototyping, and
Manufacturing, all meticulously customized to precise specifications. Our ultimate mission is to empower both
students and institutions with state-of-the-art technology solutions."

Technotran is driven by the mission of nurturing a skilled workforce that complements the remarkable
advancements unfolding in our nation. Our commitment empowers us to spearhead, promote, and disseminate
educational reforms, equipping individuals with the precise expertise and skills demanded by the corporate
landscape.

Our vision is to be at the forefront of the educational technology sector in India, specifically in the domains of
Robotics, AI, and Embedded Systems. By 2030, we aspire to establish Robotics labs in more than 100 schools
and educational institutions, featuring our customized Robotics kits.

5
CERTIFICATE

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 ABSTRACT
The modern world, Digital electronics systems are compact and faster. But, the major problem of these
systems are power dissipation. The Power dissipation have different variants such as a static power,
dynamic power, short circuit and leakage current dissipation. In VLSI Design, the power consumption
plays an important role. In order to minimize the power dissipation there are many different low power
methodologies are used such as a multi-Vth method, clock gating and reversible logic gate method. The
major advantages of a circuit designing using a reversible logic gates will be compatible with an
obtainable resources and the reversible Gates have a zero heat dissipation. The Arithmetic and Logical
Unit is fundamental part of a computing systems. This paper, presents a Design of low garbage
Reversible Arithmetic and logical unit design for computing system and the design includes Adder,
subtractor and Multiplier blocks. The functionality of a design performance, trash outputs, Quantum cost
are analysed. The proposed design has a 11 trash outputs and 57 quantum costs. The design is coded on
Verilog HDL and synthesized, simulated by a Vivado software.

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 CONTENTS

S.NO TOPIC PAGE

NO
1 CHAPTER 1:INTRODUCTION
2 CHAPTER 2:LITERATURE REVIEW
3 CHAPTER 3:METHODOLOGY/APPROACH
4 CHAPTER 4:OBSERVATION ON PROPOSED
DESIGN
5 CHAPTER 5:CODE FOR REVERSIBLE ALU
6 CHAPTER 6: SIMULATION AND RESULTS
7 CHAPTER 7:CONCLUSION
8 CHAPTER 8:REFERENCES

8
 INTRODUCTION
Irreversible gates are used as design units in the conventional techniques for creating a digital circuit. Due to
bit loss in each operation, these gates cause information loss. The major source of heat produced by digital
systems is the bit loss phenomenon in digital circuits. Although it is true that computers consume a maximum
energy, the question is why computers consume the maximum level energy? In 1961,

[1] Mr. Rolf Landauer developed a novel solution from thermodynamics for this problem that he named the
Landauer principle. The principle demonstrates that irreversible information loss of every bit will result in the
generation of the ln2kT Joules of heat energy, where ln is a logarithm of 2, T is a temperature, and k is the
Boltzmann constant. In 1973, Bennett.

[2] Demonstrated that using reversible computing as opposed to irreversible calculation prevents the
expenditure of ln2kT Joules of energy.

[3] In typical computers, the calculation is irreversible, meaning that once the output is produced, the input
data may be lost and cannot be recovered, resulting in increased power usage. Reversible logic circuits,
however, are an exception to this rule since they allow for the generation of input from output. There will be
a distinct input combination for each output logic. Because they are all multiple level input, single input to
output logic gates, gates like AND, OR, and XOR cannot be reversed.

[4] If the vectors of the input bits and output bits are equal and the inputs and outputs are assigned to each
individual input in a one-to-one relationship, then a logic gate is said to be reversible. As a result, the outputs
of a reversible gate may potentially be used to identify it individually. Input bits may still be recovered from
the logic gates even after the creation of the output. Reversible logic gates' inputs and outputs can only be
recovered from one another in a certain way. Information cannot be deleted using reversible logical processes,
and no heat is produced.

[5] In order to reproduce the inputs from the outputs, the reversible circuit works backward, which results
in zero power usage. Reversible logic gates are used to create reversible circuits, which carry out difficult
logical and arithmetic operations. From the help of Reversible Logic gates (toffoli, peres gate,etc.).

[6]) the Arithmetic and Logical unit is proposed.

This ALU design is Consists a Peres gate based Reversible adder, DKG gate based subtractor and Reversible
2x2 multiplier. Also, the proposed ALU design is combined with a decoder, Multiplexer and 1 bit memory
unit.
In the regard of power dissipation, irreversible computation inherently leads to the energy losses due to the
missing data bit. Landauer demon-strated that, the amount of heat dissipated for operation of every bit of
information, regardless of its realization technique, is given by kTln2, where k is the Boltzmann’s constant
–23 –1
(1.38×10 JK ) and T is the absolute temperature. Bennett showed that the energy loss in a logic circuit can be
avoided by designing reversible logic circuits with an acyclic combinational logic gates in which all gates are
reversible, and are interconnected without explicit fan-outs and loops. Reversible gates can be realized by
quantum circuits. If the function F is re-versible then unique one-to-one mapping is existed between an n-
input vector and a corresponding n-output vector.

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Quantum logic gates are inherently reversible and that are construct based on reversible logic. Reversible logic
is considered as a novel alternative for reduction of the physical entropy gain. Reversible computing is one of
the aspects of quantum computer. Reversible logic is a new developed field of study that holds promise for
quantum computing. In quantum computing, any state of the computation is described by a state pattern that
is a complex linear superposition of all binary digit states. A qubit is the quantum of a classical bit, which can
be in a state of superimposition of zero and one.

A reversible logic gate is an m-input, m-output circuit which generates a unique output vector Ov for each
possible input vector Iv.A brief review on reversible logic fund mentals and corresponding parameters are
presented in the appendix. There are many reversible logic gates which have been presented in the state of the
art literatures, like: Feynman Gate (FG) with quantum cost of 1, Peres Gate (PG) with quantum cost of 4,
Toffoli Gate (TG) with quantum cost of 5, Fredkin Gate (FRG) with quantum cost of 6, Thapliyal Ranganathan
Gate (TRG) with quantum cost of 4, and Reversible Multiplexer (RMUX1) gate with quantum cost of 4. Also,
other beneficial gates were presented in previous works. Among them, 4×4 Double Peres Gate
(DPG) with quantum cost of 6, 4×4 Morrison Ranganathan Gate (MRG) with quantum cost of 6.
presents some of these reversible gates including their logical operations as well as quantum
implementations.

There are some major issues for determining the complexity and performance of reversible circuits. To evaluate
reversible logic circuits, researchers considered different cost metrics such as the number of gates, garbage
outputs, constant inputs, quantum cost, and hardware complexity. In the analysis of a reversible logic circuit,
these different cost metrics should be determined and compared to other similar circuits. Quantum cost is
referred as the number of 1×1 and 2×2 gates. The quantum cost and the hardware complexity should be
minimized. Secondly, the number of gates, constant inputs and garbage outputs, which are utilized for
maintaining the reversibility of the logic circuit, must be diminished. Minimization of the cost parameters is
also required. Reduction of the number of gates, garbage outputs, constant inputs, quantum cost, and hardware
complexity is needed to improve design and costs. Reversible circuits for different purposes e.g. HA (Half
Adder), FA (Full Adder), and multi-plier have been proposed recently. Among these reversible circuits,
Arithmetic Logic Unit (ALU) is very important in the digital processing.
ALU is a main structure of a Central Processing Unit (CPU) in any computing system. It can be generate to
Boolean functions, such as XOR, NAND, and OR. The ALU is central for the design of the instruction set of
a programmable computing device. Consequently, optimized ALUs are on demand in computer system and
DSP (Digital Signal Processor). shows a basic ALU composed of two inputs for the operands, one input for
selecting the control operation, and one output for the product. An ALU performs one of the several possible
functions on two operands A and B depending on control inputs. In addition, the ALUs are suitable for different
quantum technology and embedded processors.

10
 General form of ALU

This paper focuses on the design of reversible ALUs that can be part of a programmable reversible computer.
Reversible ALUs help us to build more complex systems and low-power digital circuit in nanotechnology and
quantum computers. In this study, we propose three new designs of reversible ALU which could handle
different elementary arithmetic and logical operations.

For the past decades, there were numerous of difficulties and problems occurred in the development of
conventional computing technologies. The major problem of the conventional computing technologies is
power dissipation which is an important issue in today’s computer chip . The advancement in Very Large Scale
Integrated (VLSI) designs especially in portable device technologies lead to faster, smaller and more complex
electronic system design . In VLSI design, the conventional logic circuits dissipate more power. In the
conventional logic circuits, every bit of information loss will generate kTlog2 joules of heat energy . In the
conventional logic circuit design, information loss occurs due to the total number of output signals is less than
the total number of input signals applied to the logic circuit. Reversible computing is a promising method in
low power dissipating circuit design for current technologies such as low power Complementary Metal Oxide
Semiconductor (CMOS) design, cryptography, optical information processing, quantum computing and
nanotechnology . Reversible logic can be defined as thermodynamics of information processing. Hence, it is
used to reduce the power dissipation by preventing the loss on information. It is shown in that the circuit which
designed using reversible logic can eliminate the heat dissipation due to information loss. This is due to the
amount of energy dissipated in a system which bears a direct relationship to the number of bits erased during
computation. The difference between the reversible circuits and conventional logic circuits is that the
reversible circuits are built from reversible logic gates.

Arithmetic and Logic Unit (ALU) works as a data processing unit which is an important part in the central
process unit (CPU) of any computer architecture. ALU is a multi-functional circuit that performs one of a few
possible functions on two operands and which depends on the control inputs [7]. ALU needs to continually
perform during the life-time of any computational devices such as a computer or a hand held device such as
hand phone. Thus, reversible logic can be implemented in designing ALU to reduce the power dissipation and
propagation delay in the circuits [8]. In this paper, two new reversible ALU designs are proposed using two
different reversible full adder logic circuits. In the proposed designs, eight arithmetic and four logical
operations are performed. In the proposed reversible ALU design 1, Peres Full Adder Gate (PFAG) is used in
the design, HNG gate [9] is used as an adder logic circuit in the proposed reversible ALU design 2. The
proposed designs are analysed and compared in terms of number of gates count, garbage output, quantum cost
and propagation delay. A short review on few existing reversible gates is detailed in section-II of the paper.

11
Section-III introduces the proposed ALU designs. The 16 bit ALU shown in section-IV The simulations
results are shown in section-V.The conclusion and references section-VI.

12
 LITERATURE REVIEW
The Proposed ALU Architecture performs the addition, Subtraction and multiplication operations and
additionally decoder and multiplexer is combined. Adder, Subtractor and multiplier of various designs have
already addressed and worked on by numerous authors in a literature of reversible designs with the aim of
creating the large optimal and better performance circuits [7-10].

In the year 2011[7], S. Sultana optimised this 8-bit Adder/Subtractor architecture. They used twenty-five
reversible logic gates, seventeen trash outputs, and seventy three quantum rate while designing this circuit.
An improved 4-bit Adder/Subtractor [8] circuit was put out in the 2013 publication by, Shefali Mamataj. 8
reversible gates with a mix of Feynman and DKG gates were used in that design. 11 trash output signals
were produced by this design.

In 2015, Harpreet Singh [9] suggested a novel reversible logic gate under the moniker WG gate. This paper
presents the construction of a comprehensive Adder/Subtractor circuit utilising with a one gate and two trash
outputs and a quantum rate of seven.

In [10] the adder/subtractor design is proposed using reversible gates. The author concluded as the design
have a 2n trash outputs and seven n quantum rates.

In 2018 [11], the HNG gate based 8 bit and 4 bit array multiplier is proposed. The author proposed the
multiplier design using HNG gate based Ripple Carry Adder and the multiplier design have a 28 gates, 5249
nW power, 231 µm2 area.

In 2017 [12], the sixteen bit reversible arithmetical and logical unit is design by the author Swaminathan.
The ALU design contains adder and subtractor and the multiplexer is used as a control unit. The design is
reduced the power 0.312mw to 0.261mw and delay 2.266ns to 1.907ns and the ALU design parameters are
compared with irreversible ALU design.

In 2021[13], the novel ALU design is provided by the author Behrouz Safaie zadeh using quantum dot
cellular automata. The proposed design performs 6 Arithmetic operations and 10 logical operations. The
design is reduced the area 0.92 µm2 to 0.62 µm2 and Quantum rate 21 to 16 compared to other existing
designs and Vedic multiplier design[14] is designed using Quantum Dot cellular automata. In 2011 [15], the
author approach the two different ALU designs and comparison of the ALU parameters also provided. The
Quantum rate is reduced compared to the other existing designs.

In 2020 [16], author Ravi Ranjan provide the 8 bit reversible ALU Architecture on programmable gate. In
this design the adder/subtractor performance is increased. Compared to other designs, this design has a
limited amount of logic size or trash output values.

In [17] the reversible gates and combinational circuits are reviewed and the author gave the difference of the
combinational circuits design using multiple reversible logic gates. Above literature survey shows that, the
researchers have done particular work in area of reversible logic based circuits and ALU designs. This paper
presents a low garbage output reversible Arithmetic and logical unit architecture.

13
 METHODOLOGY
The Reversible logic gates methodology is used in the proposed design.
A. Reversible Logic Gates
A device with a one point to one other point mapping between input and output vectors is a reversible
logical gates. The vector of outputs may always be used to reconstruct the vector of inputs. Each output
vectors have a unique functionalities compared to the other output vectors. A reversible circuit gate has a at
least four logic gates with low complexity level. The Reversible logic circuits have different parameters like
constant given inputs, trash outputs, Quantum rate or cost and number of gates used in the circuit designing.

1. Number of gates (CG): gates needed to construct reversible circuits.

2. Number of constant inputs given (CI): the proportion of inputs in a function that represents the number of
unchangeable inputs.
3. Garbage or trash output (GO): The reversible logic gate's output lines are maintained by the amount of
unused or undesirable output bits, allowing reversible circuits to be created.
4. Quantum cost (QC): It is calculated by counting the number of reversible gates wanted to realising a
circuits, which have one input-output and two input outputs. The realisation of one input-output and two
input-output QC is 1. B. SOME BASIC REVERSIBLE LOGIC GATES

To implement the combinational circuits, the following basic reversible gates are used. Not, Toffoli, Peres,
CNOT, DKG and TR gates are used in this proposed design. Not gate [6] is a 1x1 gate and functional block
is illustrated in figure.1. M(a) is the input vectored, while K is the output vectored (p). p=a' is the definition
of the not gate's output. The not gate's quantum rate is 1.

The Toffoli gate, or a doubly controlled NOT gate, is a (3X3) universal reversible gate. As shown in Figure
2, the first two inputs are directly passed to the corresponding outputs and the third output is the logical XOR
of the third input with the logical AND of all the first two inputs. a, b and c are the three inputs to the gate
and the corresponding Output lines are X, Y and Z respectively.

Figure.2 shows the functional block for the Toffoli gate [6], that is a 3x3 gate. Toff, gate's input and output
vectors are M(a,b,c) and K(p,q,r). Toffoli gate's output will specified as p=a, q=b, r =ab xor c. The Toffoli
gate's quantum rate is 5.

14
Peres gate is another important gate which has a low quantum cost as compared to other gates. As illustrated in Figure
4, the input vector is I (A, B, C) and the output vector is O (P, Q, R). It is a single gate that performs the same
functions that the Feynman and the Toffoli gates perform individually.

Figure.3 shows the functional block for the Peres gate [6], a 3x3 gate. The gate's input and output vectors are
M(a,b,c) and K(p,q,r). The peres gate's output is denoted as p=a, q= a xor b, and r =ab xor c. The Peres Gate
has a quantum rate of 4.

Figure.4 shows the functional block and the CNOT gate [6], which is a 2x2 gate. M(a,b) and K represent the
input and output vectors (p,q). The CNOT gate's output is denoted as p=a, q=a xor b. The CNOT gate has a
quantum rate of 1.

Itis 4* 4 reversible DKG gate [6] that can work singly as a reversible Full adder and a reversible Full subtractor.
Figure.5 shows the functional block for the DKG gate, a 4x4 gate. DKG gate's input and output vectors are
M(a,b,c,d) and K(p,q,r,s). p=b, q=a xor c, r=(a xor b)(c xor d) xor cd, and s=b xor c xor d are the output
parameters of the DKG. The DKG gate's quantum rate is 17.

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Figure 6 shows the functional block for the TR gate [6], a 3x3 gate. The input vectors for the TR gate are
M(a,b,c) and Output Vector of the gate is K(p,q,r), respectively. The definition of the TR gate's output is p=a,
q=a xor b, and r =b' xor c. Quantum rate of the TR gate is 4.

Other than this, some basic reversible gates also available like Feynmann(2x2 gate), Double Feynmenn(3x3
gate)[6], HNG gate, Fredkin gate[13], TSG, NFT, RMUX1, TKS, BVF. These gates also used for implement
the combinational circuits.

PROPOSED DESIGN
The Reversible arithmetic and logical unit architecture is proposed. The arithmetic operations are the
fundamental part of most computing system and good logical implementation of these also important for the
computing system. Improvement of a Arithmetic unit is help to improve the entire computing system. For
reversible garbage free output computing system, the garbage free arithmetic unit also important. Generally,
the arithmetic system performs the addition, subtraction and multiplication operations. The proposed
combined architecture contains the adder, subtractor, multiplier, 1 bit memory store element edge triggered
flipflop[18], encoder, multiplexer and logical unit. For the adder design Peres gates are used. In full adder
design sum and carry generation is not possible without copying one of the inputs. In reversible logic overlap
of the input information help to generate the carry and sum in garbage bits. Different reversible adders are
used in the ripple structure [19]. e.g. reversible binary coded decimal adder. For single bit adder design 2
gates are used. For 4 bit, 8 gates are used. For n bit, 2xn-bit size gates are used. For Subtractor 4x4 DKG
gate is used. Multiplication is a another important operation for computing system. To perform the
multiplication operation in reversible, save both multiplicand and multiplier while still producing the
product. The half adder design is used for the 2x2 multiplication operation for proposed design.
Multiplication design is shown in figure.8 and half adder is shown in figure.9. For garbage free
multiplication, Karatsuba algorithm [20] is used.

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17
For storing the bit, 1-bit memory store element edge triggered flip flop is proposed and shown in figure 10.
In this proposed design, decoder and multiplexer combined with ALU architecture. Decoder is designed
using 1 peres gate, 1 TR gate, 3 CNOTgate, 1 NOT gate. 2x4 decoder shown in the figure 11. The actual
presented design is shown in figure 12. Combined architecture of the Arithmetic and logical unit is proposed
and it contains the adder, subtractor and multiplier for arithmetic operations and decoder used for decode the
instructions set, Multiplexer is used as a control system, it controls the arithmetic operation. For storing the
bit, 1bit memory element reversible edge triggered flip flop [19] is used. The combined method of ALU is
approached from the implementation of De interleaver[21]. It performs the addition, subtraction and
multiplication operations in single cycle and simulation of the operations and RTL view of the design is
shown below.

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 CODE FOR REVERSIBLE ALU

RTL Code:-

module Reversible_ALU( input A, B, C, D, S0,

S1, CLK, input [1:0] M1, M2, output sum,
carry, diff, Bout, Storing, Mux_out,
output AND, OR, NOT, XOR, XNOR, NAND, NOR,
output [3:0] Product, output [3:0] Decoder_Y);
wire [1:0] p;

Full_adder x1(A, B, C, sum, carry);

Multiplexer4to1 x2(A, B, C, D, S0, S1, Mux_out);
Multiplier2bit X3(M1, M2, p);
Storing_element x4(CLK, D, Storing);
Subtractor X5(A, B, D, diff, Bout);
Decoder2to4 X6(S0, S1, Decoder_Y);

assign AND = A & B;

assign OR = A | B; assign
NOT = ~A; assign XOR
= A ^ B; assign XNOR =
~(A ^ B); assign NOR =
~(A | B);
assign NAND = ~(A & B);

assign {Product[3], Product[2], Product[1], Product[0]} = p;

assign Decoder_Y = {X6.r[3], X6.r[2], X6.r[1], X6.r[0]};
19
endmodule

module Full_adder(
input A, B, Cin, output
sum, carry); wire P, G, r;
peres p1(A, B, 0, P, q, r);
peres p2(q, Cin, r, G, sum, carry); endmodule

module Multiplexer4to1(
input I0, I1, I2, I3, S0, S1,
output OUT); wire a, b, c,
d, out;
MG m1(S0, I1, I0, a, b, G1);
MG m2(S0, I3, I2, c, d, G2);
MG m3(S1, d, b, a, out, G3);
assign OUT = out;
endmodule

module Multiplier2bit( input [1:0] M1,

M2, output [3:0] p); wire [3:0] pp1,
pp2, pp3, pp4, r; peres a1(M1[0], M2[0],
0, pp1, q1, r[0]); peres a2(M1[0], M2[1],
0, pp2, q2, r[1]); peres a3(M1[1], M2[0],
0, pp3, q3, r[2]); peres a4(M1[1], M2[1],
0, pp4, q4, r[3]); Half_adder_db a5(pp2,
pp3, r[1], c); Half_adder_db a6(c, pp4,
p[2], p[3]);
endmodule

module Half_adder_db(
input A, B, output S,
Cout); wire p, q;
Toffoli t1(A, B, 0, p, q, Cout);
cnot t2(p, q, Cout, S); endmodule

module Storing_element(
input CLKin, D,
output out); wire
f;
fredkin f1(CLKin, D, f, out, out, out); endmodule

module fredkin( input A, B, C,

output p, q, r); assign p = A;
assign q = (!A & B) ^ (A & C);
assign r = (A & B) ^ (!A & C);
endmodule

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module Subtractor(
input A, B, Bin,
output diff, Bout);
wire p, q, r;
DKG d1(1, A, B, Bin, p, q, Bout, diff);
endmodule

module DKG(
input A, B, C, D, output P, Q, R, S);
assign P = B; assign Q = A ^ C; assign
R = ((A ^ B) & (C ^ D)) ^ (C & D); assign
S = B ^ C ^ D; endmodule

module Decoder2to4(
input I0, I1, output [3:0] r);
wire [3:0] y; peres h1(I1, I0,
0, G1, p1, p2); TR h2(I1, I0,
0, G2, t1, t2); cnot h3(p2, 0,
c1, y[3]); cnot h4(!p1, c1, q3,
y[0]); cnot h5(t2, t1, y[2],
y[1]);
assign r = y;
endmodule

module cnot(
input A, B, output
p, q); assign p =
A; assign q = A ^
B; endmodule

module TR(
input A, B, C, output
p, q, r); assign p = A;
assign q = A ^ B; assign
r = (A & ~B) ^ C;
endmodule

module MG(
input S, B, A, output O, G0,
Y); assign O = S; assign G0
= (!S & B) | (S & A);
assign Y = (!S & A) | (S & B);
endmodule

module PG(
input A, B,
output O, Y);
assign O = A;
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assign Y = A ^ B;
endmodule

module Toffoli(
input A, B, C,
output p, q, r);
assign p = A;
assign q = B;
assign r = (A & B) ^ C;
endmodule

module peres( input A,

B, C, output p, q, r);
assign p = A; assign q
= A ^ B; assign r = (A
& B) ^ C; endmodule

TESTBENCH Code:-

module Reversible_ALU_tb;
// Inputs
reg A, B, C, D, S0, S1, CLK;
reg [1:0] M1, M2;

// Outputs wire sum, carry, diff, Bout,

Storing, Mux_out;
wire AND, OR, NOT, XOR, XNOR, NAND, NOR;
wire [3:0] Product, Decoder_Y;

// Instantiate the unit under test (UUT)

Reversible_ALU UUT(
.A(A), .B(B), .C(C), .D(D), .S0(S0), .S1(S1), .CLK(CLK),
.M1(M1), .M2(M2),
.sum(sum), .carry(carry), .diff(diff), .Bout(Bout),
.Storing(Storing), .Mux_out(Mux_out),
.AND(AND), .OR(OR), .NOT(NOT), .XOR(XOR),
.XNOR(XNOR), .NAND(NAND), .NOR(NOR),
.Product(Product), .Decoder_Y(Decoder_Y)
);

// Clock generation
always #5 CLK = ~CLK;

// Initial stimulus
initial begin
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 $monitor("Time=%0t, A=%b, B=%b, C=%b, D=%b, S0=%b, S1=%b, M1=%b, M2=%b, sum=%b,
carry=%b, diff=%b, Bout=%b, Storing=%b, Mux_out=%b, AND=%b, OR=%b, NOT=%b, XOR=%b,
XNOR=%b, NAND=%b, NOR=%b, Product=%b, Decoder_Y=%b",
$time, A, B, C, D, S0, S1, M1, M2, sum, carry, diff, Bout, Storing, Mux_out, AND, OR, NOT, XOR,
XNOR, NAND, NOR, Product, Decoder_Y);

// Apply test vectors

A = 0; B = 1; C = 0; D = 1; S0 = 0; S1 = 1; M1 = 2; M2 = 3;
#10;
A = 1; B = 1; C = 1; D = 0; S0 = 1; S1 = 0; M1 = 1; M2 = 0;
#10;
// Add more test cases as needed
end

endmodule

SIMULATION AND RESULTS

In this section Peres Gate based full adder is discussed. For reversible adder 2 Peres gates are used. In first
3x3 Peres gate, adder input a and b are connected to the pin 1 and 2. 3rd pin is declared as 0. Second and
third output of the 1st Gate is connected with a 2nd Peres gate input pin 1 and 3. Pin 2 is connected with
input Carry. The output of the adder Sum and carry out is produced in 2nd Peres gate pin 2 and 3. In
simulation, the adder input pins a is set as 1, b set as 0 and Cin set as a 1. The output of the adder sum and
Carry out is generated in the pin sum and Cout as 0 and 1. The full adder have a 1 trash output, 8 quantum
rate and 6 number of gates. The synthesized design and simulation is shown in figure.13&14.

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The full subtractor circuit is design is constrcted using DKG reversible gate. For performing full subtraction
operation in DKG gate, input pin 1 is declared as 1, pin 2&3 connected with a subtractor input a and b,
borrow input is connected with pin 4. The output Borrow out and difference is produced at the DKG gate
3&4. In simulation figure.16, the input pins of the gate, a is set as 0, b is set as 1 and Bin set as 1. The output
of the subtractor borrow out and difference is generated in the pin Diff and Bout. Dkg subtractor have a 2
trash outputs, 17 Quantum rate and 8 gates are used. The synthesized design of DKG subtractor is shown in
figure.15.

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In figure.17, the 2x2 Reversible Multiplier Synthesize design is shown. For 2x2 multiplier design 2
Reversible half adders and 4 Toffoli gates are used. In input side, 4 toffoli gates 3rd pin is declared as 0,
input a0 and b0 is connected with 1st toffoli gate, a1 and b0 is connected with 2nd gate, a0 and b1 connected
with 3rd gate and a1 and b1 connected with 4th gate. 1st gate is produced the output P0 at pin3. Output of the
2nd and 3rd Toffoli gate is connected with a half adder design1 and half adder design1 output at pin 2 and
4th gate output is connected with a half adder design2. Half adder design1 and design2 is produced the
output of the multiplier P1, P2 and P3. Half adder design is designed using 1 toffoli gate and 1 CNOT gate
and the design is shown in a figure9. In simulation figure.18, the multiplier input pin a0 set as 0, a1 set as 1,
b0 set as 0, b1 set as 1 and the output of the multiplier p0,p1,p2,p3 is generated in the pin P0,P1,P3 and P2 as
a 0001. The 2x2 multiplier design have a 8 garbage outputs, 32 Quantum cost and 18 number of gates.

The combined architecture consists 11 pins. In that, a, b, c, d, Cin and Bin are the input pins and Diff, sum,
Bout, Cout, o are the output pins. For addition operation a, b, Cin, Sum and Cout pins are used as a input and
output pins. For subtraction operation a, b and Bin pins are used as a input pins. Diff, Bout pins are worked
as a output for subtractor. In this 2x2 multiplier design, a and b, c and d pins are used as a input pins and Pin
o is used as a output pin for multiplier. The Overall operation of a Combined Architecture is shown in
Simulation figure.19, In figure.19, for addition operation pin a is set as 1, b is set as 0 and Cin is set as 0. The
output of the adder sum and output Carry is generated in the sum, Cout pins as 1 and 0. For Subtraction
operation the same input pin of adder, a and b is used and input borrow is applied on a pin Bin. a set as 1, b
set as a 0, Bin is set as a 0.

25
26
Output of the Subtractor difference and output borrow is generated in the diff and Bout pins as a 1 and 0. For
2x2 multiplication operation a, b, c, d pins are used as a input pins. Pin a is set as a 1, pin b is set as a 0, pin c
is set as a 0, pin d is set as a 0. The output product of the multiplier is generated in the pin o. pin o is a bus
format output pin so, the actual output of the multiplier is generated in the pin o[0] as a 0, pin o[1] as a 0, pin
o[2] as a 0, pin o[3] as a 0. The proposed design is performed addition, subtraction and multiplication
operations in single cycle. Reversible parameters of proposed design is analyzed. In proposed design, the adder
has a 1 trash output and 8 quantum cost, the Fig.19. Simulation for Proposed ALU Design subtractor have a 2
trash outputs and 17 quantum rate, the multiplier has a 8 trash output values and 32 quantum rate. Totally the
proposed design contains the 11 trash outputs and 57 quantum cost. More specifically, we are working on a
generic multiplication circuit and have created new low garbage output addition circuits. A reversible
arithmetic logic unit was also built by combining multiple operations. The development of bigger reversible
computing systems is achievable using these and other low garbage output arithmetic circuits. We have already
show the design of ALU architecture and this implemented using the reversible gates. These systems are still
small, with further research, it should be able to apply the same techniques to create a larger system. In table.1,
the Parameters of the Proposed adder and subtractor design is compared with existing 4bit adder/subtractor
design [10].

27
Compared to the existing design [10], the adder has 4 garbage output and subtractor have an 8 garbage
output. From the comparison, the proposed design has a Minimum level of garbage outputs and low number
of gates are used in the design. The single bit proposed ALU design parameters Accuracy level is shown in
figure.20.

CONCLUSION

The proposed design is a low garbage output ALU design and it have a 11 garbage output values and 57
Quantum Cost. This design is dedicated to the computer arithmetics. For computing system many conventional
logic methods are available but, in reversible computing the input recreation is happened it is help to the
applications of computing systems and the energy loss is avoided by the reversible logic gates.

Normal logic gates, such as AND, OR, and NOT gates, are fundamental building blocks of classical digital
circuits. They operate in a way that is not reversible; that is, given an output, you cannot always determine the
exact inputs that produced that output. For example, in an OR gate, if the output is 1, you cannot
determine whether both inputs were 1 or just one of them.

On the other hand, reversible logic gates are designed such that given an output, you can always determine the
exact inputs that produced that output. These gates are important in quantum computing and low-power
computing because they do not dissipate energy when changing states. One of the key features of reversible
logic gates is that they conserve information, meaning no information is lost during computation. Examples
reversible logic gates are designed to be reversible, conserving information and enabling efficient
and opportunities for innovation in computing architecture:
28
 1. Energy Efficiency : Reversible logic gates inherently conserve energy since they do not dissipate
energy when changing states. This can lead to significant reductions in power consumption, making
reversible ALUs ideal for low-power computing applications, such as in mobile devices and IoT
devices.
2. Quantum Computing: Reversible ALUs are essential components in quantum computing systems
due to their ability to maintain coherence and reversibility, which are fundamental principles in
quantum mechanics. By designing ALUs with reversible logic gates, we can advance the development
of practical quantum computing architectures.
3. Optimized Circuit Design: Reversible logic gates require a different approach to circuit design
compared to traditional irreversible logic gates. This presents an opportunity for exploring novel
circuit architectures and optimization techniques to improve performance, reduce area overhead, and
enhance overall efficiency.
4. Information Preservation: Reversible ALUs ensure that no information is lost during computation,
which can be advantageous in certain applications where data integrity and reversibility are critical,
such as cryptography and error-correction algorithms.
5. Reduced Heat Dissipation: Since reversible logic gates do not produce heat during computation,
reversible ALUs can operate at higher speeds without the need for extensive cooling mechanisms. This
opens up possibilities for designing high-performance computing systems with reduced thermal
management requirements.
In conclusion, the design of an optimized ALU using reversible logic gates offers numerous benefits,
including energy efficiency, suitability for quantum computing, opportunities for circuit optimization,
information preservation, and reduced heat dissipation. These advantages make reversible ALUs an
attractive area of research for advancing computing technology towards more efficient and sustainable
architectures.

29
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