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3)Multiplier

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The document outlines the design, simulation, and implementation of an 8-bit adder using XILINX ISE Software and an FPGA Spartan-3E Starter Board. It includes the necessary tools, program code for a four-bit multiplier, and pin assignments for the hardware implementation. The result confirms successful design and simulation of the 4-bit multiplier.

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3)Multiplier

Uploaded by

mmmsmaheshwaran
1 views4 pages
The document outlines the design, simulation, and implementation of an 8-bit adder using XILINX ISE Software and an FPGA Spartan-3E Starter Board. It includes the necessary tools, program code for a four-bit multiplier, and pin assignments for the hardware implementation. The result confirms successful design and simulation of the 4-bit multiplier.

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The document outlines the design, simulation, and implementation of an 8-bit adder using XILINX ISE Software and an FPGA Spartan-3E Starter Board. It includes the necessary tools, program code for a four-bit multiplier, and pin assignments for the hardware implementation. The result confirms successful design and simulation of the 4-bit multiplier.

Copyright:

© All Rights Reserved
Download as PDF, TXT or read online from Scribd
Download as pdf or txt
1 views4 pages

3)Multiplier

Uploaded by

mmmsmaheshwaran
The document outlines the design, simulation, and implementation of an 8-bit adder using XILINX ISE Software and an FPGA Spartan-3E Starter Board. It includes the necessary tools, program code for a four-bit multiplier, and pin assignments for the hardware implementation. The result confirms successful design and simulation of the 4-bit multiplier.

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© All Rights Reserved
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EX.

NO: DESIGN ENTRY, SIMULATION AND IMPLEMENTATION OF A 8-BIT


ADDER
DATE :

AIM:
To design, Simulate and Implement 8-Bit Adder using XILINX ISE Software and
FPGA Board.

TOOLS REQUIRED:
1. Personal Computer
2. XILINX Software
3. FPGA Spartan-3E Starter Board(XC3S500E)

PROGRAM (8-BIT ADDER):

//Four Bit Multiplier


‘timescale 1ns/1ps
module fourbitmul(a,b,p);
input[3:0]a,b;
output[7:0]p;
wire[14:0]pp;
wire[5:0]s;
wire[1:0]c;
and a1(p[0],a[0],b[0]);
and a2(pp[0],a[1],b[0]);
and a3(pp[1],a[2],b[0]);
and a4(pp[2],a[3],b[0]);
and a5(pp[3],a[0],b[1]);
and a6(pp[4],a[1],b[1]);
and a7(pp[5],a[2],b[1]);
and a8(pp[6],a[3],b[1]);
and a9(pp[7],a[0],b[2]);
and a10(pp[8],a[1],b[2]);
and a11(pp[9],a[2],b[2]);

Reg.No:61072112113
and a12(pp[10],a[3],b[2]);
and a13(pp[11],a[0],b[3]);
and a14(pp[12],a[1],b[3]);
and a15(pp[13],a[2],b[3]);
and a16(pp[14],a[3],b[3]);
fourbitadder a17({1'b0,pp[2:0]},pp[6:3],{s[2:0],p[1]},c[0]);
fourbitadder a18({c[0],s[2:0]},pp[10:7],{s[5:3],p[2]},c[1]);
fourbitadder a19({c[1],s[5:3]},pp[14:11],p[6:3],p[7]);
endmodule

//Fourbitadder
‘timescale 1ns/1ps
module fourbitadder(
input [3:0] a,
input [3:0] b,
input cin,
output [3:0] sum,
output carry);
wire [2:0] c;
fulladder fulladder0(a[0], b[0],cin, sum[0], c[0]);
fulladder fulladder1(a[1], b[1], c[0], sum[1], c[1]);
fulladder fulladder2(a[2], b[2], c[1], sum[2], c[2]);
fulladder fulladder3(a[3], b[3], c[2], sum[3], carry);
endmodule

//Full adder
‘timescale 1ns/1ps
module fulladder(a,b,c,sum,carry);
input a,b,c;
output sum;

Reg.No:61072112113
output carry;
assign sum=(a^b^c);
assign carry=(a|b)&(b|c)&(c|a);
endmodule

PIN ASSIGNMENTS:

//Pin Assignments(Locations Assigning) for 4-Bit Multiplier


NET "a[0]" LOC="P119"
NET "a[1]" LOC="P120"
NET "a[2]" LOC="P128"
NET "a[3]" LOC="P129"
NET "b[0]" LOC="P78"
NET "b[1]" LOC="P84"
NET "b[2]" LOC="P89"
NET "b[3]" LOC="P95"
NET "p[0]" LOC="P124"
NET "p[1]" LOC="P132"
NET "p[2]" LOC="P112"
NET "p[3]" LOC="P113"
NET "p[4]" LOC="P116"
NET "p[5]" LOC="P117"
NET "p[6]" LOC="P134"
NET "p[7]" LOC="P135"

Reg.No:61072112113
SIMULATION OUTPUT:

RESULT:
Thus 4-Bit Multiplier is designed and Simulation is done using XILINX ISE
Software and Implementation is done using FPGA Spartan-3E Starter Board.

Reg.No:61072112113

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