COA GATE Material – 8 to 11 Marks

Here we would discuss for both the software and hardware concepts
Architecture – Entire design of the computer components
Organization – How to properly organize the devices and communicate among them.
GATE syllabus
 Basics of computer components and its design
 Instruction set formats and addressing modes ** (2 – 3 Marks)
o Types of addressing modes ** (1 – 2 marks)
o Subroutine calls and Interrupt *
o RISC and CISC
 Memory *** (3 – 4 Marks)
o Memory architecture understanding
o Cache memory and Main memory mapping ** (2 – 3 marks)
o Secondary Memory ** (1 – 2 Marks)
 Instruction Pipelining ** (2 – 3 marks)
o Difference of sequential and parallel approach
o Pipeline execution stages
o Pipeline Hazards and stalls
 I/O Devices
o I/O modules and devices connection
o Types of I/O ** (1 marks around)
 Programmed I/O
 Interrupt Driver I/O
 Direct Memory Access I/O
 Control Unit Design (0 – 1 Marks)
o Micro operations understanding
o Hardwired and Micro programmed control unit
 Computer Arithmetic and ALU
o Integer arithmetic and representation (Mostly Not in syllabus)
o Floating point arithmetic (Mostly Not in syllabus)

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Chapter 1: Basics of COA
 The basic concept about the understanding of the different components present in
the computer system is described by the Von Nuemann Architecture (1945) as
described below:

Von Neumann Architecture

 It majorly show how the entire data is processed internally.

 Main Memory – it stores the data and set of instructions which are used to execute
the program. Majorly they are kept in the main memory and if required for faster
retrieval, it can be kept in cache also.
 CPU is the main unit where all the processing can happen.
 CPU contains ALU, CU and registers
 ALU contains circuits which can be used for performing arithmetic and logical
operations like addition, subtraction, AND, OR etc.
 Registers is the fastest memory which stores the temp data, having the smallest size.
 Registers are the sequence of bits (flip flops), whose size is around 16 to 32 bits.
 There are many types of registers which helps in faster processing of the data, which
are as follows:
o Address Register – It carries the address used to fetch the word or data from
the memory.
o Data Register – It is used to store the data, which is fetched by the address
register.
o Accumulator – It is used for the intermediary data storage, when executing
the ALU operation. It is ideally of same size as the data register.

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 o Program counter – It is used to the address of the next instruction. Its size is
same as the address register.
o Stack Pointer – It mainly stores the top element of the stack in the instruction
where the stacks are required for processing the output.
o Instruction Register – It stores the instruction to be executed. It contains
addressing modes, op code and operands.
o Temp Registers – It is used for storing the temporary data if required in case
of any processing.
o Input registers – It takes the data from I/O and gives that data to ALU for
processing.
o Output Registers – It takes the data from ALU and gives to back to the output
devices.
 Control Unit – Timing and control signal
o Timing signals – which instruction would execute first and which would
execute after. It handles the sequence of the steps in order to get proper
output.
o Control signals – Controls all the different types of registers for reading and
writing the data, such that we can efficiently use the register data as per
proper requirements.
 I/O System – which are the peripherals devices and can able to communicate
through outside by user interactive process.
 Now we have all the different types of the system, in order to connect them and
process the data, we have different types of buses, which are majorly use for the
transfer of the data.
o Address Bus – It is used to carry the addresses where the actual data are
stored. It is always unidirectional to either the memory or I/O devices, where
we need to send the address and compute the required data values.
Addresses are generally generated by the processor only, which means the
CPU unit.
System – 8 GB  2^33 (bytes) data  33 address bus size

Address Data
0
1
2
.
.
2^33
If  1 word = 1 byte (address – 33 bits, data bus – 8 bits)
1 word = 32 bits = 4 bytes
2^33 / 4 = 2^31 (31 bits – address bus size) (32 bits – data bus)
o Data Bus – It contains the data, which is a bidirectional bus, which can
communicate to and fro in case of I/O devices, memory or registers. The
length of the data bus is equal to the length of the data.

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 o Control Bus – It is used to transfer the control signals and timing signals and it
is handled solely by the Control unit only. It is also a unidirectional bus.
 Ideally, in COA, all the communication happens through word length. A word is
basically a smallest indivisible unit of the memory.
 All of these bus are connecting through multiplexers with different registers as well
as memory unit also.

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 Instruction Set Architecture
 An Instruction is basically a set of commands which we give to the processor, based
on which it performs operations and provide us some output.
 For example, we give a = b + c, so basically we told the processor to add b and c, and
store the result in a.
 Instruction flow  First CU  decide to send where (ALU, Memory, I/O, registers)
 We have 3 types of instructions for performing any type of operations in the real
scenarios:
o Data transfer instructions – basically used in a concept to transfer the data
between different registers or register to memory or memory to register via
any common bus or between any I/O devices.
Common instructions here are  MOV, PUSH, POP, LD, ST, XCHG
o Data manipulation instructions – Want to make any changes to the given
data.
It has basically 3 types
1. Arithmetic – ADD, SUB, MUL, DIV, MOD
2. Logical – AND, OR, XOR, NOT, NAND, NOR
3. Shift / Conversion – SHR, SHL, SHAL, SHAR, ROR, ROL, RORC, ROLC
o Program Control instructions – execution decision for processing the program
like if, for, while etc.
Common operation here are – BR, JMP, SKP, CALL, RET

100 If() – 101 else 105

101
.
110

 Data Transfer instructions (Default register  Accumulator  (default value - null))

o MOV R1, R2  R1 = R2
o MOV M[X], A or MOV A, M[X]
o LD M[X]  load data into ACC from Memory (By default in Acc)
o STA M[X]  Store into memory from ACC
o XCHG R1, R2  swap R1 and R2.
o PUSH and POP, when we store memory in form of stack. – SP is used here
o MOV M[R1], M[R2]  M[R1] = M[R2]
o MOV M[raj], R2
o MOV – op code, and R1, R2  operands.
 Data Manipulation Instructions
o Shift operations
1. SHL (Logical shift left) [<<]  consider R1 = 00001010  10
If we apply SHL R1  00010100  20 (10 * 2)
We shift all the bits to the left, MSB is ignored and add 0 at the end.
2. SHR R1  00000101  5 (10 / 2)
We shift all the bits to the right, LSB is ignored

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 Logical – all the bits are data bits
Arithmetic – MSB – signed bit and rest all – data bits
3. SHAR (We use the signed number here) – which means if the first bit is 1,
means the given number is negative.
Consider R1 = 10100011  SHAR R1  11010001
(Here the signed does not change)
4. SHAL – same as Logical shift left (Here, the changes could be happen in case
of negative sign or first 2 is not having the same value)

5. Rotate right and rotate left

10101101  ROR  11010110

10101101  ROL  01011011
6. RORC and ROLC happens same as ROL and ROR, but it happens through carry.

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 Data  10100010 and carry  1

RORC 11010001 and carry  0

Data  10100010 and carry  1

ROLC 01000101 and carry  1

o There are many flags which are set in the manipulation instructions:
1. Carry : Set to 1 if the carry out of the ALU is 1
2. Sign : The MSB bit of the ALU’s output
3. Zero: Set to 1 if the ALU’s output is all 0’s or null.
4. Overflow: Set to 1 if there is an overflow
3 bit data  4 and 5  4 + 5 = 9(cannot be stored in 3 bits) – overflow
4 – 100 and 5 – 101  100 + 101  1001 (requires 4 bits)
By default, flags checks the value of ACC, but we change if required for a specific
program.

 Program control instructions – these instructions majorly handles the entire flow of
execution of the program.
 Normally, when a program executes, it gets run in sequential mode (implicit mode),
means line by line, but we can change this flow by making certain conditions
checking into our program.
 Following are most common program control instructions:
o Branch – unconditional (always move to another location) and conditional
branch (move to another location based on certain condition)
o Conditional BR –
1. BE R1 R2 2000(Branch if equal to 2000) if(R1 == R2) go to 2000;
2. BN R1 R2 2000(Branch if not equal to 2000) if (R1 != R2) go to 2000;
3. BHI R1 R2 2000(Branch if R1 is higher than R2 to 2000)
4. BLO R1 R2 2000(Branch if R1 is lower than R2 to 2000)
5. BZ (Branch with zero) A, BNZ, BC, BNC, BV(overflow), BNV
Code – goto A; (Unconditional branch) or if(a > 0) goto A;(Conditional)
------------
A:
BR A (Unconditional) – BHI a 0 A (Conditional – branch if higher
o JMP – always unconditional. Here we don’t have to check condition, so we
would not waste space for condition, which results in larger jump.
Consider Instruction size – 16 bits
BR – op code (4 bits), conditions (8 bits), address (4 bits)
JMP – op code (4 bits), address (12 bits)
JMP can send the control to longer distance as compared to BR.
BRE – branch with return instead of CALL – not much effective.
o SKP – it would skip the next instruction

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 2000 – SKP; (PC – 2001), after execution (PC - 2002)
2001 – skip
2002 -- execute
o CALL – call 3000, we are calling some other function at 3000 location
o RET – RET 2000, after returning back to the previous program.
Function a(){
---- (2000) – PC (2001)
b(); (2001) – PC(2002) – CALL 3000; [store 2002 address in stack]
--- (2002)
}
B(){
---- (3000)
--- (3001) – RET 2002 [PC - 2002]
}
 Instructions contents
 Instructions contains 3 parts  Addressing modes, op code and operands.
 Addressing modes tells where exactly the operand is stored in the memory.
 Op code describes which operation to be perform in the given instruction.
 Operand is basically a constant, a register address or a memory location address, on
which actually the operation is to be performed.
 Example  ADD R1, R2 [ADD – op code, and R1 and R2 are operands]
 This instruction is stored in the Instruction Register.
 Normally we have 4 types of addressing instructions format.
o 3 address instructions (3 operands) - MOV
o 2 address instructions (2 operands) - MOV
o 1 address instructions (1 operands) – LD and ST
o 0 address instructions (0 operands) – PUSH POP
ADD R1, R2 – 2 address instructions
ADD R1, R2, R3 – 3 address instructions
 Any program written by us internally gets converted into set of micro instructions
which is easily understandable by the computer.
 Consider the following basic instructions, and need to convert the same into
instructions format:
o A = b * c + d [Consider a, b, c, d as registers only]
1. 3 address instructions (2) fast execution but takes extra memory
MUL b, b, c [b * c  b]
ADD a, b, d [b + d  a]
2. 2 address instructions (3)
MUL b, c [b * c  b]
ADD b, d [b + d  b]
MOV a, b [b  a]

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 A=b*c+d
Consider b is a memory location
LD M[b] // (b) M[b] acc
MUL M[c] // acc * M[c]  acc
3. 1 address instructions (Use default accumulator here) (4) [Acc Reg
Organization]
LD b [b  acc] // LDA
MUL c [acc * c  acc]  acc = b * c
ADD d [acc + d  acc]  acc = b * c + d
ST a [acc  a]  a = acc
4. 0 address instructions (Use stack here) (6) slow execution but takes less
memory [Stack organization]
PUSH b [push b into stack]
PUSH c [push c into stack]
MUL [pop b and c  multiply and push result in stack]
PUSH d [push d into stack]
ADD [pop b and d  add and push result in stack]
POP a [pop the result in output a]

b*c+d
a= b * c + d;
 We can check here, that we go from higher to lower address instructions, the size of
the instruction decreases (result in small word size and store more data), but the
number of instructions increases (results in more time for execution of the entire
command).
 Higher to lower [number of lines increases, but instruction size decreases]
 There is always trade off whether we need to optimize the memory or optimize the
time.
 As today majorly everyone needs to execute the program with less time, so always 2
or 3 address instructions are used in real scenarios.
 In each addressing mode, we calculate the Effective Address for fetching the data, on
which we need to perform the operation.
 For storing any data in any register or memory, addressing modes helps us to fetch
the actual data.
 An addressing mode is mainly used to fetching data and also reducing the size of the
instructions as need to store the address of the register only.
 There are different types of addressing modes as follows:

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o Immediate Addressing mode – We directly specify the value of the operand,
instead of passing any address. Here, there is no calculation required.
MVI A, 100  Data = 100. [MVI – Move Immediate]
Int a = b;, int a = 100;

o Implied Addressing mode – Operand is specified implicitly in the definition of

the instruction. It is used for 0 and 1 address instructions. Here, the EA value
is directly present in the instructions.
LD 7  load 7 to ACC
PUSH 4  Push 4 to the SP top.
CRC  clear the carry flag
CLA  complement the accumulator
INC  incrementing the accumulator (a++ (implied), a +=b (not implied))
Diff
1. Immediate – we always provide constant value,
Implied – may or may not provide constant value. If not provided, it get it
internally in program through common logic
2. Immediate – works with all types of operands instructions,
Implied – works only for 0 and 1

o Register direct Addressing Mode – Operand is present in the register directly

only. Register is written in the instruction. It would reduce the size of the
instruction as we just need to store the register only and not required to
store the entire size of memory.
LD R1  store the value of R1 in ACC.
EA = IR (R1)

o Register Indirect – Register contains the memory location of the operand,

hence we can fetch the operand from that address location.
LD R1  go to R1 register (let say data = 100)  go to address location 100
 fetch data and store in ACC.
EA = Address of IR (R).

o Auto increment and auto decrement

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 It is a special case of the register indirect addressing mode. The value of the
register is considered as the address and its value is incremented or
decremented by 1, as per the given instruction.
INC A  M[R (A)]  M[R (A)] + 1. Similarly, we can do the DEC A.

o Direct – Same as the register direct addressing mode, but stored the direct
memory location, and not the register.
LD M[M1]  load ACC with data of M1 memory location
EA = Memory address of M1

o Indirect – Same as register indirect addressing mode, and stored the memory
rather than register.
LD M[M[M1]]  first go to M1 location (Memory)  go to the location of M1
data (Memory) and store it in ACC.
EA = content of M1.
MID LD M[M1]
Advanced Addressing modes
o Relative – It gives the effective address based on the program and offset
(current instruction value)
Consider the following program

500 JMP 550

501
.
.
.
.
600
From 500, it would jump to 550, as the direct address given, but it would give
the error in case the program shift to 600 to 700.
So instead of storing directly the address, we store basically from the PC.
Here, EA = PC + offset (Displacement)
So, we keep JMP 49  501 + 49  we always get the correct one.

o Base Register – It is same as relative addressing mode, but here we use the
base register for calculating the EA instead of using the PC.
Here, EA = Base of program + offset (Displacement)
It also helps to reduce the size of the instruction.

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 Base Register PC Relative
We need to have any base register We don’t require any extra register
to the program in the program
It does not save memory as Saves memory for relocation part
compared to PC relative more than Base register
JMP from 310 to 350 JMP from 310 to 350
Base – 300 Base – 300, PC - 311
JMP 50 JMP 39
Easy calculation of EA as base Tough and dynamic calculation of
register value is same EA required as PC change always
Majorly used when many branch or Used for the simple or less complex
Jump instructions present programs

o Indexed – It is used to implement the array efficiently. Any element can be

accessed with changing instruction.

A[0] A[1] A[2] A[3] A[4]

100 101 102 103 104
Base Register – 100
A[5]  base register – 100
A[3]  base register + offset = 100 + 3 = 103
A[offset]  EA = base index + offset
Here, the Indexed Register stores the displacement, whatever we want to get
the output.
Suppose we want to access 104  EA = Base + Indexed  100 + 4 = 104, and
directly fetch the value from it.

 Interrupts – When a process is executed by the CPU, and when the request occur for
some other process, which would create disturbance in the current execution, which
is called as the interrupt. Here, the interrupt flag would be set to true in this case.
 There are 3 types of interrupts:
o Internal (Divide by zero) – basically hardware detects anything wrong, it
would generate the internal interrupt
 Arithmetic error
 Hardware malfunctioning
o External (I/O devices) – Whenever any interrupt happens from outside.
 Any I/O interrupt like mouse or keyboard click.
 I/O errors
o Software (System calls) – It is caused when the program or instruction
requires to call the system based functions. This can also be represented as
the switch from User mode to system mode and back.
A processor interrupt is caused by the electrical signals on the processor chip.
It is used by the devices to tell the driver that they require attention from the
system.

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  Ctrl + c, Ctrl + v
 Any types of system specific fork or exec operation.
 Types of Computer Architecture
o RISC
o CISC
 Others

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 Questions
Q.1. An architecture contains the direct, indirect and register based addressing modes only.
Which of the following cannot be achieved by this architecture?
A) Specifying the register no in instruction such that register contains value of the operand
that is used in the operation. Reg  register direct
B) Specifying the register no in the instructions such that register will serve as the
destinations of the operations output. Register Indirect AM
C) Specifying the operand value in the instruction. Immediate AM
D) Specifying the memory location in the instruction such that it contains value of the
operand that is used in the operation. LD M[X]  Direct
Ans. C
Q.2. A machine has 24 bit instruction format. It has 32 registers and each register is of 32
bit. It need to support the 49 instructions. Each register has 2 register operands and 1
immediate operand. If the immediate operand is signed integer, the minimum value of
immediate operand is _______.
A) -64 B) -128 C) -256 D) 0
In instructions  we have opcode and operand
49 instructions  6 bits
Each register  32 bits  5 bits
Total size = 24, so 24 – 10 – 6 = 8 bits (for immediate operand)
Concept understanding in 3 address instruction

ADD (6) R1 (5) R2 (5) Immediate

Now, as immediate is signed, so it is -2^7 to 2^7- 1  -128 to 127  -128 (Minimum)

GATE Questions
Q.1. the following are some events that occur after a device controller issues an interrupt
while process L is under execution.
(P) The processor pushes the process status of L onto the control stack.
(Q) The processor finishes the execution of the current instruction.
(R) The processor executes the interrupt service routine.
(S) The processor pops the process status of L from the control stack.
(T) The processor loads the new PC value based on the interrupt.
Which of the following is the correct order in the events above occur?

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 (A) QPTRS
(B) PTRSQ
(C) TRPQS
(D) QTPRS

Q.2. The most appropriate matching for the following pairs is (GATE 2000)

C
Q.3. (GATE 2001)

Whenever you pass an array in the parameter  would take it as a pointer, which is
why it is referenced as address of address (array)

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Q.4. (GATE 2007)

A) 10 B) 11 C) 20 D) 21
Q.4.A

Q.4.B

16
Q.5.

Q.6.

Q.7.

Q.8.

17
Q.9.

Q.10.

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Q.10.A
Consider the memory is word addressable with size 32 bits, and the program has
been loaded starting from the memory location 1000 (decimal). If an interrupt occurs
during the add instruction, the return address pushed on to the stack is _____.
A) 1007 B) 1004 C) 1005 D) 1006

Q.10.B

Q.11.

Q.12.

19
Q.13.

Q.14.

20
Q.15.

A) 2 B) 9 C) 5 D) 3
Q.16. Which of the following addressing modes permits relocation without any change
whatsoever in the code?
A) Indirect addressing mode B) Indexed addressing mode
C) Base register addressing mode D) PC relative addressing mode

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