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CHAPTER- 05
CENTERAL PROCESSOR
UNIT (CPU)

1
 Central Processing Unit
Is part of the computer
Performs the bulk of data processing operation.
CPU is made up of three major parts:
The Register-set: stores intermediate data used during the
execution of the instruction
The ALU: performs the required micro operations for
executing the instruction
The Control-Unit: supervises the transfer of information
among the registers and instructs the ALU to switch operation to
perform.
The CPU performs a variety of functions dedicated by the types of
instructions that are incorporated in the computer.

2
 Major components of CPU.
 Storage Components:
 Registers
Flip-flops
 Execution (Processing) Components:
Arithmetic Logic Unit (ALU):-Arithmetic calculations,
Logical computations, Shifts/Rotates
 Transfer Components:
 Bus
 Control Components:
Control Unit

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 Cont..
 When the CPU exchanges data with memory. For this purpose, it
typically makes use of two internal registers:
 A memory address register (MAR), which specifies the
address in memory for the next read or write
A memory buffer register (MBR), which contains the data to
be written into memory or receives the data read from
memory.
 Similarly, an I/O address register (I/OAR) specifies a particular
I/O device.
• An I/O buffer (I/OBR) register is used for the exchange of data
between an I/O module and the CPU

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 General Register Organization
 When a large number of registers are included in the CPU, it is
most efficient to connect them through a common bus system.
 The registers communicate with each other not only for direct
data transfers, but also while performing various micro
operations.
 Hence it is necessary to provide a common unit that can perform
all the arithmetic, logic, and shift micro operations in the
processor.
 A bus organization for seven CPU registers is shown in Fig. 5.2.
The output of each register is connected to two multiplexers
(MUX) to form the two buses A and B.
 The selection lines in each multiplexer select one register or the
input data for the particular bus.

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Cont..

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 Cont..
 The register that receives the information from the output bus is
selected by a decoder.
 The decoder activates one of the register load inputs, thus
providing a transfer path between the data in the output bus and
the inputs of the selected destination register.
For example, to perform the operation
 The control must provide binary selection variables to the
following selector inputs:
1. MUX A selector (SELA): to place the content of R2 into bus A.
2. MUX B selector (SELB): to place the content of R3 into bus B.
3. ALU operation selector (OPR): to provide the arithmetic
addition A+ B.
4. Decoder destination selector (SELD): to transfer the content of
the output bus into R 1.
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 Control Word
 The three bits of SELA select a source register for the A input of
the ALU.
 The three bits of SELB select a register for the B input of the
ALU.
 The three bits of SELD select a destination register using the
decoder and its seven load outputs.
 The five bits of OPR select one of the operations in the ALU.
 The 14-bit control word when applied to the selection inputs
specify a particular micro operation.

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Cont..
 The encoding of the register selections is specified in Table 5-1.

 The control unit directs the information flow through ALU by:
Selecting various Components in the system
Selecting the Function of ALU
Example: R1 <- R2 + R3
[1] MUX A selector (SELA): BUS A  R2
[2] MUX B selector (SELB): BUS B  R3
[3] ALU operation selector (OPR): ALU to ADD
[4] Decoder destination selector (SELD): R1  Out Bus
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 ALU CONTROL
 Encoding of ALU operations

 Examples of ALU Micro operations

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 REGISTER STACK ORGANIZATION
Stack
 Very useful feature for nested subroutines, nested loops control
 Also efficient for arithmetic expression evaluation
 Storage which can be accessed in LIFO
 Pointer: SP
 Only PUSH and POP operations are applicable
Register Stack:-

 The register that holds the address for the stack is called a stack pointer
(SP) because its value always points at the top item in the stack.
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 Cont..
Push, Pop operations
/* Initially, SP = 0, EMPTY = 1, FULL = 0 */
PUSH POP
SP  SP + 1 DR  M[SP]
M[SP]  DR SP  SP - 1
If (SP = 0) then (FULL  1) If (SP = 0) then (EMPTY  1)
EMPTY  0 FULL  0
 The two operations of a stack are the insertion and deletion of items.
 The operation of insertion is called push (or push-down) because it can
be thought of as the result of pushing a new item on top.
 The operation of deletion is called pop (or pop-up) because it can be
thought of as the result of removing one item so that the stack pops up.
These operations are simulated by incrementing or decrementing the
stack pointer register.

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MEMORY STACK ORGANIZATION
 Memory with Program, Data,
 and Stack Segments

 A portion of memory is used as a stack with a processor register as a stack

pointer
PUSH:SP  SP - 1
M[SP]  DR
POP:DR  M[SP]
SP  SP + 1
 Most computers do not provide hardware to check stack overflow (full stack) or
underflow(empty stack)
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 Cont..
 The implementation of a stack in the CPU is done by assigning a
portion of memory to a stack operation and using a processor
register as a stack pointer.
 The program counter PC points at the address of the next
instruction in the program.
 The address register AR points at an array of data.
 The stack pointer SP points at the top of the stack.
 The three registers are connected to a common address bus, and
either one can provide an address for memory.
 PC is used during the fetch phase to read an instruction.
 AR is used during the execute phase to read an operand.
 SP is used to push or pop items into or from the stack.

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 REVERSE POLISH NOTATION
 Arithmetic Expressions: A + B
 A + B Infix notation
 + A B Prefix or Polish notation
 A B + Postfix or reverse Polish notation
 The reverse Polish notation is very suitable for stack manipulation
Evaluation of Arithmetic Expressions:-
 Any arithmetic expression can be expressed in parenthesis-free
Polish notation, including reverse Polish notation

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 INSTRUCTION FORMAT
 The format of an instruction is usually depicted in a rectangular
box symbolizing the bits of the instruction as they appear in
memory words or in a control register.
 The bits of the instruction are divided into groups called fields.
The most common fields found in instruction formats are:
1. An operation code field that specifies the operation to be
performed.
2. An address field that designates a memory address or a processor
register.
3. A mode field that specifies the way the operand or the effective
address is determined.

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 Cont..
 Operands residing in processor registers are specified with a
register address. A register address is a binary number of k bits that
defines one of 2k registers in the CPU.
 Most computers fall into one of three types of CPU organizations:
1. Single accumulator organization.
2. General register organization.
3. Stack organization.
 Instruction Fields

OP-code field:- specifies the operation to be performed

Address field:- designates memory address(s) or a processor
register(s)
Mode field:- n specifies the way the operand or the effective address
is determined
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 Cont..
 The number of address fields in the instruction format depends on
the internal organization of CPU
 The three most common CPU organizations:

Single accumulator organization:

ADD X AC  AC + M[X]
General register organization:
ADD R1, R2, R3 R1  R2 + R3
ADD R1, R2 R1  R1 + R2
MOV R1, R2 R1  R2
ADD R1, X R1  R1 + M[X]
Stack organization:
PUSH X TOS  M[X]
ADD

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 Three .. Address Instructions
 Computers with three-address instruction formats can use each
address field to specify either a processor register or a memory
operand.
Three-Address Instructions:
Program to evaluate X = (A + B) * (C + D) :
ADD R1, A, B R1  M[A] + M[B]
ADD R2, C, D R2  M[C] + M[D]
MUL X, R1, R2 M[X]  R1 * R2
 Results in short programs
 Instruction becomes long (many bits)

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 Two .. Address Instructions

 Two-address instructions are the most common in commercial

computers. Here again each address field can specify either a
processor register or a memory word.
Two-Address Instructions:
Program to evaluate X = (A + B) * (C + D) :

MOV R1, A R1  M[A]

ADD R1, B R1  R1 + M[B]
MOV R2, C R2  M[C]
ADD R2, D R2  R2 + M[D]
MUL R1, R2 R1  R1 * R2
MOV X, R1 M[X]  R1

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 One .. Address Instructions

 One-address instructions use an implied accumulator (AC)

register for all data manipulation. For multiplication and division
there is a need for a second register.
 Program to evaluate X = (A + B) * (C + D) :
LOAD A AC  M[A]
ADD B AC  AC + M[B]
STORE T M[T]  AC
LOAD C AC  M[C]
ADD D AC  AC + M[D]
MUL T AC  AC * M[T]
STORE X M[X]  AC

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 Zero .. Address Instructions

 A stack-organized computer does not use an address field for the

instructions ADD and MUL.
Can be found in a stack-organized computer
 Program to evaluate X = (A + B) * (C + D) :
PUSH A TOS  A
PUSH B TOS  B
ADD TOS  (A + B)
PUSH C TOS  C
PUSH D TOS  D
ADD TOS  (C + D)
MUL TOS  (C + D) * (A + B)
POP X M[X]  TOS

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ADDRESSING MODES
Addressing Modes:
 Specifies a rule for interpreting or modifying the address field of
the instruction (before the operand is actually referenced)
 To variety of addressing modes
to give programming flexibility to the user
to use the bits in the address field of the instruction efficiently
 The control unit of a computer is designed to go through an
instruction cycle that is divided into three major phases:
1. Fetch the instruction from memory.
2. Decode the instruction.
3. Execute the instruction.

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 TYPES OF ADDRESSING MODES
Implied Mode
 Address of the operands are specified implicitly in the definition
of the instruction
No need to specify address in the instruction
EA = AC, or EA = Stack[SP], EA: Effective Address.
Immediate Mode
 Instead of specifying the address of the operand, operand itself is
specified
 No need to specify address in the instruction
 However, operand itself needs to be specified
Sometimes, require more bits than the address
Fast to acquire an operand

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Cont..
Register Mode
 Address specified in the instruction is the register address
Designated operand need to be in a register
Shorter address than the memory address
Saving address field in the instruction
Faster to acquire an operand than the memory addressing
 EA = IR(R) (IR(R): Register field of IR)
Register Indirect Mode
 Instruction specifies a register which contains the memory address
of the operand
Saving instruction bits since register address is shorter than the
memory address
Slower to acquire an operand than both the register addressing or
memory addressing
EA = [IR(R)] ([x]: Content of x)
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 Cont..
Auto-increment or Auto-decrement features:
 Same as the Register Indirect, but:
 When the address in the register is used to access memory, the
value in the register is incremented or decremented by 1 (after or
before the execution of the instruction)
Direct Address Mode
 Instruction specifies the memory address which can be used
directly to the physical memory
Faster than the other memory addressing modes
Too many bits are needed to specify the address for a large
physical memory space
EA = IR(address), (IR(address): address field of IR)

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 Cont..
Indirect Addressing Mode
 The address field of an instruction specifies the address of a
memory location that contains the address of the operand
When the abbreviated address is used, large physical memory
can be addressed with a relatively small number of bits
Slow to acquire an operand because of an additional memory
access
 EA = M[IR(address)]
Relative Addressing Modes
 The Address fields of an instruction specifies the part of the
address (abbreviated address) which can be used along with a
designated register to calculate the address of the operand

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 Cont..
 PC Relative Addressing Mode(R = PC)
EA = PC + IR(address)
Address field of the instruction is short
Large physical memory can be accessed with a small number
of address bits
Indexed Addressing Mode
 XR: Index Register:
EA = XR + IR(address)
Base Register Addressing Mode
 BAR: Base Address Register:
EA = BAR + IR(address)

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ADDRESSING MODES - EXAMPLES

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 Data Transfer and Manipulation
 Most computer instructions can be classified into three categories:
1. Data transfer instructions
2. Data manipulation instructions
3. Program control instructions
 Data transfer instructions cause transfer of data from one location
to another without changing the binary information content.
 Data manipulation instructions are those that perform arithmetic,
logic, and shift operations.
 Program control instructions provide decision-making capabilities
and change the path taken by the program when executed in the
computer.

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 Data Transfer Instructions
 Typical Data Transfer Instructions

 Data Transfer Instructions with Different Addressing Modes

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 DATA MANIPULATION INSTRUCTIONS
 Three Basic Types: Arithmetic instructions, Logical and bit manipulation
instructions and Shift instructions

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PROGRAM CONTROL INSTRUCTIONS

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Conditional Branch Instructions

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numerical example of conditional branch instructions
 Consider an 8-bit ALU as shown in Fig. 8-3. The largest unsigned number
that can be accommodated in 8 bits is 255. The range of signed numbers is
between + 127 and -128. The subtraction of two numbers is the same whether
they are unsigned or in signed-2's complement representation.
Let A = 11110000 and B = 00010100. To perform A - B, the ALU takes the 2's
complement of B and adds it to A.
A: 11110000
B + 1: + 11101100
A - B: 11011100 C=1 s = 1 V=O Z=O
 C = 1 because there is a carry out of the last stage.
 S = 1 because the leftmost bit is 1.
 V = 0 because the last two carries are both equal to 1, and
 Z = 0 because the result is not equal to 0.

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Subroutine Call and Return
 A subroutine is a self-contained sequence of instructions that
performs a given computational task.
 The instruction that transfers program control to a subroutine is
known by different names.
 The most common names used are call subroutine, jump to
subroutine, branch to subroutine, or branch and save address.
SUBROUTINE CALL:-
Call subroutine
Jump to subroutine
Branch to subroutine
Branch and save return address

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 Cont..
 Two Most Important Operations are Implied;
 Branch to the beginning of the Subroutine
Same as the Branch or Conditional Branch
 Save the Return Address to get the address of the location in the
Calling Program upon exit from the Subroutine
 Locations for storing Return Address:
 Fixed Location in the subroutine(Memory)
 Fixed Location in memory
 In a processor Register
 In a memory stack
 most efficient way

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 PROGRAM INTERRUPT
Types of Interrupts:
External interrupts
 External Interrupts initiated from the outside of CPU and Memory
 I/O Device:- Data transfer request or Data transfer complete
 Timing Device :-Timeout
 Power Failure
Internal interrupts (traps)
Internal Interrupts are caused by the currently running program
 Register, Stack Overflow
 Divide by zero
 OP-code Violation
 Protection Violation
Software Interrupts
 Both External and Internal Interrupts are initiated by the computer Hardware.
 Software Interrupts are initiated by executing an instruction.
 Supervisor Call -> Switching from a user mode to the supervisor mode
-> Allows to execute a certain class of operations
which are not allowed in the user mode
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 INTERRUPT PROCEDURE
 Interrupt Procedure and Subroutine Call
 The interrupt is usually initiated by an internal or an external
signal rather than from the execution of an instruction (except for
the software interrupt)
 The address of the interrupt service program is determined by the
hardware rather than from the address field of an instruction
 An interrupt procedure usually stores all the information necessary
to define the state of CPU rather than storing only the PC.
The state of the CPU is determined from;
Content of the PC
Content of all processor registers
Content of status bits
Many ways of saving the CPU state depending on the CPU
architectures
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The Control Unit
 What is the control unit (CU)?
The control unit is that portion of the processor that actually
causes things to happen.
The control unit issues control signals external to the processor
to cause data exchange with memory and I/O modules.
The CU also issues control signal internal to the processor to
move data between registers, to cause the ALU to perform a
specified function, and to regulate other internal operations.
 The inputs to the control unit from external sources are
Instruction register
Flags, and
Control signals

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 The Control Unit Operation
 What is cycle?
is the execution of a sequence of sub steps in the
execution of an instruction.
 The sequence of more fundamental operations called micro-
operations made up the cycle.
 A single micro-operation generally involves:
A transfer between registers
A transfer between a register and an external bus, or a simple
ALU operation.

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Cont..
 The CU of a processor performs two tasks:
1. It causes the processor to step through a series of micro-
operations in the proper sequence, based on the program
executed
2. It generates the control signals that cause each micro
operations to be executed.
 The control signals generated by the control unit causes the
opening and closing of logic gates, resulting:
Transfer of data to and from registers and
Operations of the ALU

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 Control of the Processor
 Defining the functional requirements is the basis for design and
implementation of the control unit.
 The functions are performed by the control unit and causes to happen.
 There are three- step process leads to a characterization of the control
unit:
1) Define the basic elements of the processor.
2) Describe the micro-operations that the processor performs.
3) Determine the functions that the control unit must performs to cause
the micro-operations to be performed.
 The basic elements of the processors are:
 ALU
 Registers
 Internal data paths
 External data paths
 Control unit
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 Instruction Pipelining
 The computer system evolve for greater performance achieved by
taking advantage of improvement in technology. Such as faster
circuitry.
 The organizational enhancement to the processor also improve
performance. Such as,
◦ Using of multiple registers rather than a single accumulator
◦ Use of cache memory.
◦ Another organizational approach is instruction pipelining.
 What is pipelining?
 A means of introducing parallelism into the essentially sequential
nature of a machine instruction program.

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 Cont..
 Instruction pipelining is similar to the use of an assembly line in a
manufacturing plant.
 In pipelining, new inputs are accepted at one end before
previously accepted inputs appear as output at the other end.
 to apply this concept to instruction execution, the instruction has
a number of stages.
 A simple approach, consider the instruction processing two stages.
Fetch instruction
Execution instruction

45
 Cont..
 There is time during execution of an instruction when no main
memory is not referenced
 This time will be used to fetch the next instruction in parallel with
executing the current one.
 The pipeline has two independent stages:
The first one is fetch an instruction and buffer it.
The second stage is executing the instruction. When the fetch
stage gates an advantage any unused memory cycles to fetch
the next instruction is called pre fetch or fetch overlap.
 Pipelining requires registers to store data between stages.
 If the time between the two stage is equal, the instruction cycle
time would be Halved.

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 Cont..
 There are two reasons unlikely to double the execution rate.
1. The execution will involve reading and storing operand and
performs some operations.
 The fetch stage waits until the execution buffer becomes free.
2. A condition branch instruction makes the address of the next
instruction to be fetched unknown.
 These factors reduce the potential effectiveness of the two stage
pipeline.

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 Cont..
 To gain further speedup, the pipeline must have more stages.
 Consider the following decomposition of the instruction processing.
Fetch instruction (FI): read the next expected instruction into a
buffer.
Decode instruction (DI): determine the opecode and the operand
specifies.
Calculate operands (CO): calculate the effective address of each
source operand.
Fetch operand (FO): fetch each operand from memory.
Execute instruction (EI): perform the indicated operation and
store the result,
Write operand (WO): store the result in memory.
 With this decomposition, the various stage will be of more nearly
equal duration.
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RISC: REDUCED INSTRUCTION SET COMPUTERS
 Historical Background, IBM System/360, 1964
 The real beginning of modern computer architecture
 Distinction between Architecture and Implementation
 Architecture: The abstract structure of a computer

 Continuing growth in semiconductor memory and

microprogramming
A much richer and complicated instruction sets
CISC(Complex Instruction Set Computer)

49
 Cont..
 Arguments advanced at that time
 Richer instruction sets would simplify compilers
 Richer instruction sets would alleviate the software crisis
 move as much functions to the hardware as possible
close Semantic Gap between machine language and the high-
level language
 Richer instruction sets would improve the architecture quality

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COMPLEX INSTRUCTION SET COMPUTERS: CISC
 High Performance General Purpose Instructions
Characteristics of CISC:
1. A large number of instructions (from 100-250 usually)
2. Some instructions that performs a certain tasks are not used
frequently.
3. Many addressing modes are used (5 to 20)
4. Variable length instruction format.
5. Instructions that manipulate operands in memory.

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 CHARACTERISTICS OF RISC
 Common RISC Characteristics
 Operations are register-to-register, with only LOAD and STORE
accessing memory
 The operations and addressing modes are reduced and Instruction
formats are simple
 More RISC Characteristics

A relatively large numbers of registers in the processor unit.

Efficient instruction pipeline
Compiler support: provides efficient translation of high-level
language programs into machine language programs.

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 Cont..
 RISC Characteristics
Relatively few instructions
Relatively few addressing modes
Memory access limited to load and store instructions
All operations done within the registers of the CPU
Fixed-length, easily decoded instruction format
Single-cycle instruction format
Hardwired rather than micro programmed control
 Advantages of RISC
 VLSI Realization
 Computing Speed
 Design Costs and Reliability
 High Level Language Support

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