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Module 4 - Cache Memory Problems

The document discusses the configuration and calculations related to digital computer memory, including cache memory specifications and address formats. It covers tag, block, and word fields for a 64K x 16 memory unit and provides solutions for determining cache line bits and hit/miss ratios for various cache mapping scenarios. Additionally, it analyzes memory block requests and their impact on cache performance using direct-mapped and fully associative caches.

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Nivedita Murugan
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15 views6 pages

Module 4 - Cache Memory Problems

The document discusses the configuration and calculations related to digital computer memory, including cache memory specifications and address formats. It covers tag, block, and word fields for a 64K x 16 memory unit and provides solutions for determining cache line bits and hit/miss ratios for various cache mapping scenarios. Additionally, it analyzes memory block requests and their impact on cache performance using direct-mapped and fully associative caches.

Uploaded by

Nivedita Murugan
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd
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A digital computer has a memory unit of

64K x 16 and a cache memory of 1K words. The


cache uses 2-way set associative mapping with a
block size of four words.
a. How many bits are there in the tag, block
and word fields of the address format?
b. How many blocks can the cache
accommodate?

Solution-

64 K × 16: 16 bit address; 16-bit data.


(a) 6 8 2 = 16 bits address
TAG BLOCK WRD

INDEX = 10 bit cache address.


b)1 6 16 = 23 bits in each word of cache
V TAG DATA

(b) 28 = 256 blocks of 4 words each


2.Consider a 64KB direct-mapped cache with a line length of 32
bytes.
c. Determine the number of bits in the address that refer to the
byte within a cache line.
d. Determine the number of bits in the address required to select the
cache line.
Solution-

a. For
the given cache, the number of bits in the address to
determine the byte within the line=
n = 2 5 = 5 bits
b. There are 64K/32= 2048 lines in the given cache. The number
of bits required to select the required line 2 11 = 11 bits

2.Consider a direct mapped cache with 8 cache


blocks (0-7). If the memory block requests are in
the order-
3, 5, 2, 8, 0, 6, 3, 9, 16, 20, 17, 25, 18, 30, 24, 2, 63, 5,
82, 17, 24

Which of the following memory blocks will be in


the cache at the end of the sequence? Also, calculate
the hit ratio and miss ratio.
We have,
 There are 8 blocks in cache memory numbered from 0 to
7.
 In direct mapping, a particular block of main memory
is mapped to a particular line of cache memory.
 The line number is given by-
Cache line number = Block address modulo Number of
lines in cache
Solution-

For the given sequence-


 Requests for memory blocks are generated one by one.
 The line number of the block is calculated using the above relation.
 Then, the block is placed in that particular line.
 If already there exists another block in that line, then it is replaced.
 Hit ratio = 3 / 21
 Miss ratio = 17 / 21
3.Consider a fully associative cache with 8 cache
blocks (0-7). The memory block requests are in the
order-
4, 3, 25, 8, 19, 6, 25, 8, 16, 35, 45, 22, 8, 3, 16, 25, 7
If LRU replacement policy is used, which cache block
will have memory block 7? Also, calculate the hit ratio
and miss ratio.

Solution-

We have,
 There are 8 blocks in cache memory numbered from 0 to 7.
 In fully associative mapping, any block of main memory can be mapped to
any line of the cache that is freely available.
 If all the cache lines are already occupied, then a block is replaced in
accordance with the replacement policy.
Thus,
 Line-5 contains the block-7.
 Hit ratio = 5 / 17
 Miss ratio = 12 / 17

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