MICROPROCESSOR

SE-SEM IV
UNIT III
MEMORY MANAGEMENT

Q1. Differentiate and explain GDTR, LDTR, and IDTR. in 80386 microprocessors.

ANS-Registers in the 80386 microprocessor:

1. GDTR (Global Descriptor Table Register):
o The GDTR is a 32-bit register that plays a crucial role in memory
management.
o It stores the base address of the Global Descriptor Table (GDT) in the
linear address space.
o The GDT contains segment descriptors, which provide information for
mapping logical addresses to linear addresses.
o These descriptors include details such as the segment’s base address,
size, type, privilege level, and whether the segment is present or not.
o The GDTR also holds the segment limit (size) of the GDT.
o Instructions like LGDT and SGDT allow access to the GDTR.
2. LDTR (Local Descriptor Table Register):
o Similar to the GDTR, the LDTR is also a 32-bit register.
o It points to the Local Descriptor Table (LDT) in memory.
o The LDT is an optional table used for process-specific segment
descriptors.
o Each process can have its own LDT, distinct from the GDT.
o The LDT provides additional flexibility in segment management.
o Instructions like LLDT and SLDT allow access to the LDTR.
3. IDTR (Interrupt Descriptor Table Register):
o The IDTR is another 32-bit register with a specific purpose.
o It holds the base address of the Interrupt Descriptor Table (IDT).
o The IDT contains descriptors for various interrupt and exception
handlers.
o When an interrupt occurs (such as a hardware interrupt or a
software-generated exception), the processor consults the IDT to find
the appropriate handler.
o The IDT descriptors include information about the handler’s location,
privilege level, and other relevant details.
o Instructions like LIDT and SIDT allow access to the IDTR.

In summary:

● GDTR deals with segment descriptors for the entire system.

● LDTR handles process-specific segment descriptors (if an LDT is used).
● IDTR manages interrupt and exception descriptors.

OR

1. GDTR (Global Descriptor Table Register):

o Holds the base address and limit of the GDT.
o GDT defines memory segments for the entire system.
 o Created by compilers, linkers, loaders, or the operating system.
o Segments described in the GDT include code segments, data segments,
and system segments.
o The processor uses GDT descriptors to map logical addresses to linear
addresses.
o GDT can contain up to 8192 descriptors.
o The first entry (INDEX=0) is not used by the processor.
o GDTR is set using the lgdt instruction.
2. LDTR (Local Descriptor Table Register):
o Holds the base address and limit of the LDT.
o LDT is specific to a particular task or process.
o LDT descriptors define memory segments for a specific context.
o LDT is set using the lldt instruction, which takes a selector pointing
into the GDT.
o LDT is optional and not commonly used in modern operating systems.
3. IDTR (Interrupt Descriptor Table Register):
o Contains the base address and limit of the IDT.
o IDT is used for handling interrupts and exceptions.
o IDT descriptors define interrupt and exception handlers.
o IDT entries correspond to specific interrupt vectors.
o IDTR is set using the lidt instruction.

Q2. Demonstrate General Selector Format in brief.

ANS- Segment selector contain a 13 bit index field that is used to select one of 8192
segment descriptor that resides either in Global Descriptor Table (GDT) or Local
Descriptor Table (LDT).

There is only one GDT in protected mode.

• Protected mode tasks, however, may each have their own LDT.
• The TI bit in the segment selector picks the appropriate descriptor table during
translation.
• TwoRequestor Privilege Level (RPL) bits are used in protection check to determine
if access to segment is allowed. Selector may be loaded into any of the six segment
registers (CS, DS, SS, ES, FS, GS).
• Aselector that has an index value of zero and points to GDT is called a Null
Selector.
• This selector value is reserved to provide a method if initializing segment registers,
since any access using a null selector generate an exception (General-protection
Exception- INT 13).

Q3. Explain the Segment Translation Process with a neat diagram of 80386.
ANS-

Logical Address to Linear Address Conversion:

● The 80386 transforms logical addresses (as viewed by programmers)

into linear addresses (actual addresses in physical memory) in two steps.
● The logical address consists of a segment selector and a segment offset.

Segment Translation:
 ● The processor uses the following data structures for segment translation:
o Descriptors: These provide the necessary information to map a logical
address to a linear address.
o Descriptor tables: Segment descriptors are stored in either the Global
Descriptor Table (GDT) or the Local Descriptor Table (LDT).
● Linear Address to Physical Address Conversion:
o Once we have the linear address, it undergoes further translation
using paging hardware to obtain the physical address.

Q4. Demonstrate General Descriptor Format available in various descriptor tables.

ANS- A descriptor is a series of 8 bytes that describe and locate a memory segment.

• It contains 32-bit base address that specifies the beginning of the segment of
memory controlled by the descriptor.

• The size of segment is indicated by a 20-bit limit field and the state of the
Granularity Bit (G bit)

• A segment descriptor provides the 80386 with the data it needs to map a logical

address into a linear address.

• These descriptors are not created by programs, but created by Compilers, Linkers,

Loaders, or the Operating System.

• When G (Granularity bit) is set, the limit bit represents the number of 4kb pages
contains in the segment.

• This allows the size of segment to be of any length from 4KB to 4GB.
• When this bit is cleared (G = 0) the 20-bit limit field is assumed to be measured in
units of 1 byte. If it is set (G = 1), the limit field is in units of 4 KB.

• Two Descriptor Privilege Level (DPL) bits specifies the privilege level required to
access the segment.

• An attempt by less privilege task to use the segment result in exception.

P (Present Bit): Indicate whether the segment is present in memory. A

segment-not-present exception is generated if this bit is clear when the segment
descriptor is accessed.

S (Segment Descriptor): When set, indicate that the segment is a system segment.
When clear, the segment is a code or data segment.

D (Default Operation Size): For code segment, D controls the default operand and
address size (16 bit when D is clear versus 32 bit when set).

For data segment, D controls how stack is manipulated (via SP /ESP with 16/32 bit

pushes/pops)

AVL : Available to programmer.

The AVL (available) field specifies whether the descriptor is available for user or it is
for use by operating system.

– AVL=0 not available for user, used by OS

– AVL=1 available for user

E (Executable):

Executable selects a stack segment (E=0) or a code segment (E=1) .E also defines
the function of the next two bits.

X (Expansion):

If E=0, then X indicates the direction of expansion for the data segment. If X=0, the
segment expands upward, as in a data segment.

RW(Read/Write):

If E=0, then the read/write bit indicate that the data segment may be written or not.

If E=1, then RW indicate that the code segment maybe read (RW=0) or not read
(RW=1).

A (Accessed Bit):
Accessed is set each time that the microprocessor accesses the segment. It is
sometimes used by operating system to keep track of which segments have been
accessed.

Q5. With the necessary diagram, explain the page translation process in 80386.

ANS-

• Page translation

Once the logical address converted into linear address in segment translation, the
80386 transforms a linear address into a physical address.

• This phase of address transformation implements the basic features needed

for page oriented virtual memory systems page level protection.
• The page translation step is optional. Page translation is in effect only when
the PG bit of CR0 is set or operating system has to implement multiple virtual
8086 tasks, page oriented protection, or page oriented virtual memory.
• This bit is typically set by the operating system during software initialization.
• The PG bit must be set if the operating system is to implement multiple virtual
8086 tasks, page oriented protection, or page oriented virtual memory.
• Page translation allows the physical memory space used by the system to be
smaller than the linear address space.
• E.g. 80386 ‘s 4 GB linear addressing space may be mapped to physical
memory of 16 MB.
• When paging is turned on (PG=1),the physical address space consists of
1,048,496 pages.

Each page is of 4096 bytes long.

 • Figure shows how the processor converts the DIR, PAGE, and OFFSET fields of
a linear address into the physical address by consulting two levels of page
tables.
• The addressing mechanism uses the DIR field as an index into a page
directory, uses the PAGE field as an index into the page table determined by
the page directory, and uses the OFFSET field to address a byte within the
page determined by the page table.

PDE (Page Directory Entry )

• The page directory have 1024 directory entries of 4 bytes each.

• Each page directory entry addresses a page table that contains 1024 entries.
Each Page Directory Entry contains the

1. Address of the next level of tables

2. Page Tables and information about the page table.

• The upper 10 bits of the linear address (A22±A31) are used as an index to select
the correct Page Directory Entry.

• D: The D (Dirty) bit 6 is set to 1 before a write to an address covered by that page
table entry occurs.

• A: The A (Accessed) bit 5, is set by the Intel386 DX for both types of entries before
a read or write access occurs to an address covered by the entry.

• U/S and R/W: These bits are used to provide User/ Supervisor and Read/Write
protection for individual pages.

• P: The P (Present) bit 0 indicates if a Page Directory or Page Table entry can be
used in address translation. – If P=1theentry can be used for address translation.

• User which corresponds to level 3 of the segmentation-based protection, and

supervisor which encompasses all of the other protection levels (0, 1, 2).

PTE (Page Table Entry)

• Each Page Table is 4K bytes and holds up to 1024 Page Table Entries.

• Page Table Entries have the starting address of the page frame and statistical
information about the page.
• The 20 upper bit page frame address is concatenated with the lower 12 bits of the
linear address to form the physical address.

• Page tables can be shared between tasks and swapped to disks.

Q6. Explain the use of following instructions in detail:

i) LGDT ii) SIDT iii) LLDT
ANS-
1. LGDT (Load Global Descriptor Table):
o Purpose: The LGDT instruction is used to load the Global Descriptor
Table Register (GDTR) with information about the Global Descriptor
Table (GDT).
▪ The GDT is a data structure used in protected mode to manage
memory segments. It contains segment descriptors that define
the attributes and base addresses of various memory segments.
▪ When an operating system switches to protected mode, it sets
up the GDT to describe the memory layout.
▪ The LGDT instruction loads the GDTR with the base address and
limit of the GDT.
▪ If a 16-bit operand is used with LGDT, the GDTR is loaded with
a 16-bit limit and a 24-bit base.
▪ If a 32-bit operand is used, a 16-bit limit and a 32-bit base are
loaded.
▪ LGDT m16&32: Load the GDTR with the base address and limit
from the specified memory location.
▪ LGDT is primarily used in operating system software and is not
typically used in application programs.
▪ It directly loads a linear address (not a segment-relative
address) in 80386 protected mode.

2. SIDT (Store Interrupt Descriptor Table):

o Purpose: The SIDT instruction stores the contents of the Interrupt
Descriptor Table Register (IDTR) into memory.
 ▪The IDTR holds information about the Interrupt Descriptor Table
(IDT), which contains descriptors for interrupt and exception
handlers.
▪ The SIDT instruction allows an operating system to save the
IDTR’s contents for later use.
▪ SIDT m16&32: Store the IDTR’s base address and limit into the
specified memory location.
▪ Like LGDT, SIDT is primarily used in operating system software.
▪ It also directly deals with linear addresses in 80386 protected
mode.
3. LLDT (Load Local Descriptor Table):
o Purpose: The LLDT instruction loads the Local Descriptor Table Register
(LDTR) with information about the Local Descriptor Table (LDT).
▪ The LDT is another data structure used in protected mode. It
contains segment descriptors specific to a particular task or
process.
▪ The LLDT instruction sets up the LDTR to point to the LDT for the
current task.

▪ Similar to LGDT, LLDT can use either a 16-bit operand (16-bit limit,
24-bit base) or a 32-bit operand (16-bit limit, 32-bit base).
▪ LLDT m16&32: Load the LDTR with the base address and limit
from the specified memory location.
▪ LLDT is used less frequently than LGDT and SIDT.
▪ It is essential for managing per-task segment descriptors.

Q7. What is call gate? Explain how it is used in calling functions with higher
privilege levels.

ANS-

o A call gate is a mechanism within Intel’s x86 architecture that

facilitates changing the privilege level of a process during the execution
of a predefined function call using the CALL FAR instruction.
o It serves as a gateway for transitioning from lower privilege code (such
as user-mode code) to higher privilege code (such as kernel-mode
code).

How Call Gates Work:

o Privilege Levels: The 80386 microprocessor operates with different

privilege levels (also known as protection rings). These levels
determine the access rights and permissions of code executing within
them.
o Segment Descriptors: In the 80386, protection is applied at the
segment level. Each segment descriptor stores protection parameters,
including base address, limit, type, and privilege level.
o Type Checking:
 ▪ The TYPE field of a descriptor serves two purposes:
▪ Distinguishing among different descriptor formats.
▪ Specifying the intended usage of a segment.
▪ For example:
▪ Data-segment descriptors have a writable bit to indicate
whether instructions can write into the segment.
▪ Executable-segment descriptors have a readable bit to
allow instructions to read from the segment.
o Call Gate Descriptors:
▪ A call gate descriptor defines an entry point of a procedure and
specifies the privilege level of that entry point.
▪ It can reside in the Global Descriptor Table (GDT) or a Local
Descriptor Table (LDT) but not in the Interrupt Descriptor Table
(IDT).

• A Word Count which specifies how many parameters are to be copied from the
caller's stack to the stack of the called routine.
• The Word Count field is only used by call gates when there is a change in the
privilege level, other types of gates ignore the word count field.

Q8. Differentiate and explain the Interrupt gate and Trap gate descriptor.

ANS-
• Interrupt and Trap Gates use the destination selector and destination offset fields of
the gate descriptor as a pointer to the start of the interrupt or trap handler routines.

• The difference between interrupt gates and trap gates is that the interrupt gate
disables interrupts (resets the IF bit) while the trap gate does not.

Q 9. Explain the use of following instructions in detail: i) SGDT ii) LIDT iii) SLDT.
ANS-
1. SGDT (Store Global Descriptor Table Register):
o Opcode: 0F 01 /0
o Description: Copies the contents of the Global Descriptor Table
Register (GDTR) into the six bytes of memory indicated by the operand.
o Operand Size: If the operand-size attribute is 32 bits, the next three
bytes are assigned the base address of the GDTR.
o Usage: Primarily used in operating system software, not in application
programs.
o Flags Affected: None.
o Exceptions:
▪ #GP (0) if the result is in a non-writable segment.
▪ #GP (0) for an illegal memory operand effective address in the
CS, DS, ES, FS, or GS segments.
▪ #SS (0) for an illegal address in the SS segment.
▪ #PF (fault-code) for a page fault.
o Real Address Mode Exceptions: Interrupt 6; SGDT is not recognized in
Real Address Mode.
o Virtual 8086 Mode Exceptions: Same exceptions as in Real Address
Mode; #PF (fault-code) for a page fault.
2. LIDT (Load Interrupt Descriptor Table Register):
o Opcode: 0F 01 /3
 o Description: Loads the contents of the Interrupt Descriptor Table
Register (IDTR) from the six bytes of memory indicated by the operand.
o Operand Size: If the operand-size attribute is 32 bits, the next three
bytes are loaded into the IDTR.
o Usage: Used to set up interrupt handling in protected mode.
o Flags Affected: None.
o Exceptions:
▪ #GP (0) if the result is in a non-writable segment.
▪ #GP (0) for an illegal memory operand effective address in the
CS, DS, ES, FS, or GS segments.
▪ #SS (0) for an illegal address in the SS segment.
▪ #PF (fault-code) for a page fault.
o Real Address Mode Exceptions: Interrupt 6; LIDT is not recognized in
Real Address Mode.
o Virtual 8086 Mode Exceptions: Same exceptions as in Real Address
Mode; #PF (fault-code) for a page fault.
3. SLDT (Store Local Descriptor Table Register):
o Opcode: 0F 00 /0
o Description: Stores the contents of the Local Descriptor Table Register
(LDTR) in the two-byte register or memory location indicated by the
effective address operand.
o Usage: Exclusively used in operating system software, not in
application programs.
o Flags Affected: None.
o Exceptions:
▪ #GP (0) if the result is in a non-writable segment.
▪ #GP (0) for an illegal memory operand effective address in the
CS, DS, ES, FS, or GS segments.
▪ #SS (0) for an illegal address in the SS segment.
▪ #PF (fault-code) for a page fault.

o Real Address Mode Exceptions: Interrupt 6; SLDT is not recognized in

Real Address Mode.
o Virtual 8086 Mode Exceptions: Same exceptions as in Real Address
Mode; #PF (fault-code) for a page fault.

Q 10. Enlist various types of system and non-system descriptors in the 80386.
Explain their use in brief.

ANS-
1. System Descriptors:
o Global Descriptor Table (GDT): The GDT contains segment descriptors for
both system and user programs. It’s a crucial data structure used by the
processor to map logical addresses to linear addresses. Descriptors in the
GDT provide information about segment location, size, and access
permissions.
o Interrupt Descriptor Table (IDT): The IDT holds descriptors for interrupt
service routines (ISRs). These descriptors define how the processor handles
various hardware and software interrupts.
 o Local Descriptor Table (LDT): The LDT is an optional table that can be used to
store additional segment descriptors. It’s similar to the GDT but is specific to a
particular task or process.
o Task State Segment (TSS): The TSS descriptor provides information about the
task state, including stack pointers, privilege levels, and other task-related
data. It’s used during task switching and context switching.

2. Non-System Descriptors:
o Code Segment Descriptor: Used for executable code, such as program
instructions. It specifies the base address, limit, and access rights for code
segments.
o Data Segment Descriptor: Used for data storage. Similar to the code segment
descriptor, it defines the base address, limit, and access rights for data
segments.
o Stack Segment Descriptor: Used for stack operations. It provides information
about the stack’s location and size.
o Gate Descriptors: These are special descriptors used for interrupt gates, trap
gates, and call gates. They facilitate transitions between different privilege
levels and handle interrupts and exceptions.

Code and Data Descriptions

 System Descriptor Formats

Q11. Explain Translation Look-aside Buffer with diagram.

Ans-

• The Intel386 DX keeps a cache of the most recently accessed pages, this cache is
called the Translation Look-aside Buffer (TLB).

• The 32-entry TLB coupled with a 4K page size,results in coverage of 128K bytes of
memory addresses.
• The paging unit hardware receives a 32-bit linear address from the segmentation
unit.

• The upper 20 linear address bits are compared with all 32 entries in the TLB to
determine if there is a match.

• If there is a match (i.e. a TLB hit), then the 32 bit physical address is calculated and
will be placed on the address bus.

Q12. Explain Demand Paging in detail.

ANS-

• Demand Paging follows that pages should only be brought into memory if the
executing process demands them.

• This is often referred to as Lazy Evaluation as only those pages demanded by the
process are swapped from secondary storage to main memory.

Steps involved in Demand Paging

1. Determining Memory Requirement

2. Allocating Memory

3. Saving the Contents of Reallocated Memory

4. Remapping a Page Memory

5. Restoring Reallocated Pages

1. Determining Memory Requirement

• Theoretically, a program gives best performance when it is completely loaded into

primary memory, but practically it is not possible.

• Majority of memory is used by OS, Memory resident Programs and other user’s
programs, or memory maynotbeavailable.

• So as per requirement of new task, memory will be made free by swapping out data
to secondary memory.

2. Allocating Memory

• System will check A bit (Bit 5) from PTE of every page, and accordingly pages will
be allocated.

• If accessed bit has not be set by the system, meaning is that 4 KB page frame is
never references by the processor.

• If required, System will use LRU (Least recently used) algorithm.

3. Saving the Contents of Reallocated Memory

• Contents from page frame will be copied to secondary memory.

• During copying, D bit (bit 6) from PTE will be checked.

4. Remapping a Page Memory

• After completing copy from the page, P bit from PTE will be set again, as new valid

entries are added to page of new task.

• Also entries from TLB will be updated accordingly.

5. Restoring Reallocated Pages

• Data may be restored to pages as per system requirement.