1. Tell me about yourself.?

2. how much you rate yourself in digital, Verilog, SV & UVM

3. convert hexadecimal no (57.4) to decimal

4. 10. What are the types of Logic gates?

There are three basic logic gates, two universal gates, and a few other combinational logic gates in digital
electronics.

Basic Gates:

 AND gate.

 OR gate.

 NOT gate.

Universal Gates:

 NAND gate

 NOR gate

Other Gates:

 XOR gate

 XNOR gate

Nand gate to e-xor= 9 (nand gate require in total 5 nand gate)

5. multiplexer and demultiplexer?

What Is Difference Between Latch And Flip-flop?

The main difference between latch and FF is that latches are level sensitive while FF is edgesensitive.
They both require the use of clock signal and are used in sequential logic. For a latch, the output tracks
the input when the clock signal is high, so as long as the clock is logic1, the output can change if the
input also changes.FF on the other hand, will store the input only when there is a rising/falling edge of
the clock.Latch is sensitive to glitches on enable pin, whereas flip-flop is immune to glitches. Latches take
fewer gates (also less power) to implement than flip-flops. Latches are faster than flip-flops
//////////////////////////////////////////////////////////////////////////////////////////////////////////////

Verilog

Write a Verilog code to swap content of two registers with and without a temporary register?

6.
Q. Write a verilog code for asynchrounus reset.
Verilog: 2:1 MUX using conditional operator

module mux_2_1(

input sel,

input i0, i1,

output y);

assign y = sel ? i1 : i0;

endmodule

………………………………………………….
Q. Verilog code for Rising Edge D Flip-Flop with Asynchronous Reset High Level:

// FPGA projects using Verilog/ VHDL

// fpga4student.com

// Verilog code for D Flip FLop

// Verilog code for Rising edge D flip flop with Asynchronous Reset high

module RisingEdge_DFlipFlop_AsyncResetHigh(D,clk,async_reset,Q);

input D; // Data input

input clk; // clock input

input async_reset; // asynchronous reset high level

output reg Q; // output Q

always @(posedge clk or posedge async_reset)

begin
if(async_reset==1'b1)

Q <= 1'b0;

else

Q <= D;

end

endmodule
……………………………………………………………………………………………………………………………
 System verilog

1. Module vs Program block

2. Use of Program Block. Ans: To overcome the race-around condition
3. In which region program block will execute?
4. In which region module block will execute?
5. Concurrent Assertions are Non-temporal or Temporal?
6. Are immediate assertions non-temporal or temporal?
7. Which region are the Assertions sampled in? Preponed region
Assertions are evaluated at which region? Observed region
8. Which region are the assertions executed? Reactive region
9. What is there in the Property Block?
10. How can we connect Class with the BFM’s? Ans: MAILBOX
11. Where do we declare clocking blocks?
12. What is the use of the End of the Elaboration phase?
13. Difference between Reg and Logic?
14. What is Enum data type?
15. What is the use of Factory registration?
16. What is the use of Config_DB?
1. Difference between verilog and SV
17. 2. Advantages of SV over Verilog
18. 3. Advantages of UVM over SV
19. 4. Write a verilog code for synchronous and Asynchronous D-flipflop
20. 5. Write an assertion once request is asserted high, acknowledge should be asserted from 0 to
10 clock cycles
21. 6. Write a verilog code to generate a clock frequency of 100 Mhz
22. 7. Implement FSM for the sequence 10111 & write a verilog code for it.
23. 8. Write a c code to detect prime numbers.
24. 9. Difference between Blocking & NonBlocking statements.
25. 1. Create AND gates using mux
26. 2. Difference between n++ and n+1 and which one is more memory efficient in c programming
27. 3. Difference between D-latch & D-flipflop
28. 4. What is race around condition? How can we avoid it?
29. 5. what is the code of config_db?
30. 6. Difference between RAM and Flipflop ?
31. 7. Difference between new and create methods?
32. 8. Difference between Blocking and NonBlocking assignments
33. 9. Difference between == and === operator
34. 10. how can you verify a 32- bit register give me the verification plan?
35. 11. Difference between mealy and moray state machine
36. 12. swapping of 2 numbers in Verilog and different ways
37. 13. Code for delay flip flop in verilog
38. 14. C code for A>B how to verify without using arithmetic operation and logical operator
39. 15. We have 2 block, APB as DUT and AHB as T.B, but APB working slow and AHB working fast
how can they communicate without delay?
40. 16. How can we use signal in sequence which is not present is seq_item class
41. 17. Difference b/w $finish and global_stop_request
42. 18. In a clock how many times minutes hand and hours hand will meet in 24 hours.
43. 19. You have three mislabeled jars. The first jar contains apples, the second contains oranges,
and the third contains a mix of apples and oranges. You need to label the jars. You can pick as
many fruits as you want from each jar. What is the least number of fruits you have to pick from
each jar to label them correctly?
44. 1. Discussion on previous projects
45.
46. 2.Debugs I done in previous projects
47.
48. 3.Explain any difficult scenario which you have debugged and how do you root cause the failure?
49.
50. 4.Design a circuit for which input is f Mhz and output is f/4 Mhz.
51.
52. 5.difference between below statements and explain the necessity
53. #1 A=B;
54. A=#1 B;
55.
56. 6.Verilog Event queue
57.
58. 7.how can you verify a 32- bit register give me the verification plan
59.
60. 8.Among 32 bits 2nd and 11th bit got swapped how can you verify these scenario?
61.
62. 9.rite a program for bit reversal
63.
64. 10.We have a memory it's completely filled, we know the last element only. By using the pointer
traverse through the memory only once and find the exact mid location of the memory
65.
66. 11.swapping of 2 numbers in Verilog and different ways
67.
68. 12.generate a clock for 100 mhz with 50% duty cycle
69.
70. 13.Design nand gate using 2x1 mux
71.
72. 14.system A has clock frequency of 100 mhz and B have clock frequency of 25 mhz what will be
the fifo depth
73.
74. 15.design invertor using XOR gate
75.
76. 16.mealy and moray state machine
77.
78. 17.what is glitch and when can it occurs how to overcome glitch
79.
80. 18.why glitches in circuit
81.
82. 19.difference between latch and flipflop
83.
84. 20.difference between ternary operator and if else condition
85.
86. 21.Explain UVm testbench and how can you assure that driver is driving the exact values to the
DUT and some questions on the same
87.
88. 22.In a clock how many times minutes hand and hours hand will meet in 24 hours.
89.
90. 23.Discussion on previous projects
91.
92. 2.ebugs I done in previous projects
93.
94. 3.Explain any difficult scenario which you have debugged and how do you root cause the failure?
95.
96. Assertion to find the frequency of clock when time period is given and without time period
97.
98. what is duty cycle how can be the 50% duty cycle will appears
99.
100. design 2x1 mux Verilog code and write test bench and different approaches
101.
102. constraint to generate unique values of an single dimensional and multi dimensional
array.
103.
104. different questions on array declaration and initialization.
105.
106. we have 10 bags each bag have 1000 coins ,1 out of it's a faulty bag how can you find the
faulty bag.
107. 1.Discussion on previous projects
108.
109. 2.Debugs I done in previous projects
110.
111. 3.Write a constraint scenario given by interviewer
112.
113. 4.create logic gates using mux
114.
115. 5.Difference between n++ and n+1 and which one is more memory efficient in c
programming
116.
117. 6.Some c programming related questions
118.
119. 7.explain about unique in constraints with code
120.
121. 8.explain about weighted distributions in constraints with code
122.
123. 9.how you will debug test case hang issue
124.
125. 10.Difference between D-latch & D-flipflop
126.
127. 11.Explain about program block
128.
129. 12.What is race around condition? How can we avoid it?
130.
131. 13.Write a verilog code to generate a clock with frequency 5MHz
132.
133. 14.Implement in C code for palindrome
134.
135. 15. what is config_db? what are the methods we have in config_db? and where we can
write config_db methods ?
136.
137. 16.write driver code for apb
138.
139. 17.Difference between SRAM and Flipflop ?
140.
141. 18.You have three mislabeled jars. The first jar contains apples, the second contains
oranges, and the third contains a mix of apples and oranges. You need to label the jars. You can
pick as many fruits as you want from each jar. What is the least number of fruits you have to pick
from each jar to label them correctly?
142.
143. 19.If you have 8L, 5L and a 3L bucket with you. The buckets have no measurement lines
on them and you are asked to measure exactly 4L of water using the three buckets. How could
you measure exactly 4L water using only those buckets and provided you have as much extra
water as you need ?
144.
145. 20.multiple logical reasoning questions
146.
147. Discussion on previous projects
148.
149. Write an Assertion for APB protocol
150.
151. Difference between Overlapped & Non Overlapped Implication Operator
152.
153. Difference between casex and casez
154.
155. Difference between == and ===
156.
157. Difference between D-latch & D-flipflop
158.
159. What is race around condition? How can we avoid it?
160.
161. Verilog code for D-Latch
162.
163. Write a verilog code to generate a clock with frequency 5MHz
164.
165. Implement in C code for palindrome
166.
167. what is config_db? what are the methods we have in config_db?
168.
169. Difference between new and create methods
170.
171. Difference between Blocking and NonBlocking assignments
172.
173. Difference between SRAM and FIFO?
174.
175. 1) difference between # and ## in sv
176.
177. 2) what is the use of gray code
178.
179. 3) explain sv event queue with following example
180.
181. always@(posedge clk)
182.
183. begin
184.
185. a=b;
186.
187. b<= c;
188.
189. end
190.
191. 4) which component is consuming more power flipflop or latch?
192.
193. 5) explain verilog event scheduler
194.
195. 6)cisc and risc architecture
196.
197. 7)what is cache memory
198.
199. 8)what is uart?
200.
201. 9) explain factory in uvm
202.
203. 10)clock skew
204. 1. Write uvm_Sequence_item and uvm_Sequence code for Ethernet packet?
205.
206. 2. How to connect Driver and Sequncer?
207.
208. 3. What is Sequnce and driver Handshake?
209.
210. 4. How to connect sequnce with a sequncer?
211.
212. 5. What are the applications of p_sequncer?
213.
214. 6. What are the different types of verbosities in UVM?
215.
216. 7. What is Exclusive Access in AXI?
217.
218. 8. What is the test flow in IP and SoC project?
219.
220. 9. Write an assertion for signal "b" should be high throughout signal "a"?
221. 1.implement 4*1 mux using 2*1 mux
222.
223. 2.implement nand gate using 2*1 mux
224.
225. 3.verilog code to swap values of 2 variables
226.
227. 4.clock skew
228.
229. 5.how to verify a register
230.
231. 6.whether interface can be declared in sequence
232.
233. 7.overloading and overriding
234.
235. 8.if there is a mismatch error, how to find whether its scb error or data is wrong
236.
237. 9. Explain any debug you did
238.
239. 10.2 blocks a and b, a running with freq 100mhz and b with 50 mhz. what should be the
fifo depth for data tranfer to happen11. For the sam case if freq is reversed what should be the
fifo depth
240.
241. 11.logical question-You have rope that take 60 min to burn. Speed of burning is not
uniform. Example: it doesn't take 30 min to burn half Using two ropes, how would you get 45
min?
242.
243. 12.A Father & his Son was travelling in the car, they had an accident..
244.
245. Father died on the spot & Son loses his consciousness..
246.
247. He was taken to hospital..
248.
249. The doctor said I can't operate this boy, bcoz he is my son..
250.
251. Who was the Doctor?
252. 1.Can assertion written in class
253.
254. 2.assertion for when req is asserted ack should come in 2 to 4 cycles
255.
256. 3.assertion for when req is asserted ack should come in exactly 3 cycles
257.
258. 4.Write a constraint to generate random values in an array without inbuild functions
259.
260. 5.A 32 bit register, need to flip 11th bit
261.
262. 6.How to verify 32 bit register and develop verification env for the same
263.
264. 7.If 2 signals a and b, which is asserted after 2 clk cycles, which needs to be updated as 3
clk cycles.What can be done other than overriding
265.
266. 8.Suppose a memory with 1000 locations and we can traverse oly once, how can we get
the middle location
267.
268. 9.implement d latch with 2*1 mux
269.
270. 10.logical question- 7 coins in that 6 are identical and one defective .How many least
number of weighing required to identify the defective one
271. 1) Generate a clock for 1GHz?
272.
273. 2) Explain and implement packed array and unpacked array?
274.
275. 3) Write a constraint to generate a dynamic array with size 10 and all elements should be
divisible by 8?
276.
277. 4) Using fork-join_any replicate the functionality of fork-join_none?
278.
279. 5) Explain the Exclusive transfers in AXI ?
280. what is casting?
281.
282. what are the types of casting?
283.
284. What is upcasting and down casting.
285.
286. What is project related questions.
287.
288. Constraint for generating different elements in an array which are different random
elements.
289.
290. Signals in AXI.
291.
292. Why is AXI ID present?
293.
294. what is in order and out of order transaction
295.
296. What is an ISR(Interrupt Service Routine)?
297.
298. How will you develope an ISR
299.
300. what is assertion and its types
301.
 302. write an assertion when req is asserted after 5 to 10 clock cycles only grant should be
asserted.

Test bench architectute of sv.

Phases in uvm ?