SystemVerilog Randomization Examples
FPGA and Verification
Basic Randomization
SystemVerilog allows random values to be generated using the rand keyword.
1 class RandomTest ;
2 rand bit [7:0] data ; // 8 - bit random variable
3
4 function void display () ;
5 $ display ( " Random Data : % d " , data ) ;
6 endfunction
7 endclass
8
9 module test ;
10 initial begin
11 automatic RandomTest r = new () ;
12 repeat (5) begin
13 void ’( r . randomize () ) ; // Calls randomization
14 r . display () ;
15 end
16 end
17 endmodule
Listing 1: Simple Randomization
Expected Output:
Random Data: 137
Random Data: 24
Random Data: 211
Random Data: 89
Random Data: 56
Randomization with Constraints
We can limit the range of generated values using constraints.
1 class C o n s t r a i n e d R a n d o m T e s t ;
2 rand bit [7:0] data ;
3 constraint c1 { data > 50; data < 200; }
4
5 function void display () ;
6 $ display ( " Constrained Random Data : % d " , data ) ;
7 endfunction
8 endclass
9
10 module test ;
11 initial begin
12 automatic C o n s t r a i n e d R a n d o m T e s t r = new () ;
13 repeat (5) begin
14 void ’( r . randomize () ) ;
15 r . display () ;
16 end
17 end
18 endmodule
Listing 2: Constrained Randomization
Expected Output:
1
Constrained Random Data: 78
Constrained Random Data: 132
Constrained Random Data: 165
Constrained Random Data: 199
Constrained Random Data: 120
Randomizing Multiple Variables
Randomizing multiple variables and applying constraints between them.
1 class MultiVarTest ;
2 rand bit [7:0] a , b ;
3 constraint sum_limit { a + b < 200; }
4
5 function void display () ;
6 $ display ( " A : %d , B : %d , Sum : % d " , a , b , a + b ) ;
7 endfunction
8 endclass
9
10 module test ;
11 initial begin
12 automatic MultiVarTest r = new () ;
13 repeat (5) begin
14 void ’( r . randomize () ) ;
15 r . display () ;
16 end
17 end
18 endmodule
Listing 3: Sum Constraint
Expected Output:
A: 85, B: 72, Sum: 157
A: 120, B: 55, Sum: 175
A: 45, B: 80, Sum: 125
A: 30, B: 60, Sum: 90
A: 99, B: 80, Sum: 179
Excluding Specific Values
We can prevent specific values from being generated.
1 class E x c l u d e V a l u e s T e s t ;
2 rand bit [7:0] x ;
3 constraint exclude_zero { x != 0; }
4 constraint exclude_255 { x != 255; }
5
6 function void display () ;
7 $ display ( " Random Value : % d " , x ) ;
8 endfunction
9 endclass
10
11 module test ;
12 initial begin
13 automatic E x c l u d e V a l u e s T e s t r = new () ;
14 repeat (5) begin
15 void ’( r . randomize () ) ;
16 r . display () ;
17 end
18 end
19 endmodule
2
Listing 4: Excluding Zero and 255
Expected Output:
Random Value: 145
Random Value: 89
Random Value: 250
Random Value: 33
Random Value: 124
Weighted Randomization
Assigning weights to specific values to control probability distribution.
1 class Wei ghtedRan dom ;
2 rand int x ;
3 constraint weighted {
4 x dist {10 := 5 , 20 := 2 , 30 := 1}; // 10 appears most frequently
5 }
6
7 function void display () ;
8 $ display ( " Random X : % d " , x ) ;
9 endfunction
10 endclass
11
12 module test ;
13 initial begin
14 automatic Weig htedRand om r = new () ;
15 repeat (10) begin
16 void ’( r . randomize () ) ;
17 r . display () ;
18 end
19 end
20 endmodule
Listing 5: Weighted Randomization
Expected Output:
Random X: 10
Random X: 10
Random X: 20
Random X: 10
Random X: 30
Random X: 10
Random X: 20
Random X: 10
Random X: 10
Random X: 10
Randomizing an Array
We can randomize all elements of an array.
Code: Randomizing an Array of 5 Elements
3
1 class ArrayRandom ;
2 rand bit [7:0] arr [5]; // Array of 5 random values
3
4 constraint range { foreach ( arr [ i ]) arr [ i ] > 50 && arr [ i ] < 200; }
5
6 function void display () ;
7 foreach ( arr [ i ]) $ display ( " arr [%0 d ] = % d " , i , arr [ i ]) ;
8 endfunction
9 endclass
10
11 module test ;
12 initial begin
13 automatic ArrayRandom r = new () ;
14 void ’( r . randomize () ) ;
15 r . display () ;
16 end
17 endmodule
Listing 6: SystemVerilog Array Randomization
Expected Output
arr[0] = 78
arr[1] = 125
arr[2] = 162
arr[3] = 145
arr[4] = 89
