Desinging Analog Chips

Copyright 2004, 2005 Hans Camenzind.
February 2005
This book is can be downloaded without fee from

www.designinganalogchips.com
Re-publishing of any part or the whole is prohibited.
The author is indebted to the following for comments, suggestions and corrections:
Bob Pease, Jim Feit, Ted Bee, Jon Fischer, Tim Camenzind, Jules Jelinek, Brian
Attwood, Ray Futrell, Beat Seeholzer, David Skurnik, Barry Schwartz, Dale Rebgetz,
Tim Herklots, Jerry Gray, Paul Chic, Mark Leonard, Yut Chow, Gregory Weselak, Lars
Jespersen and Wolfgang Horn.
Camenzind: Designing Analog Chips Table of Contents
Table of Contents
Analog World
1 Devices 1-1
Semiconductors 1-1
The Diode 1-5
The Bipolar Transistor 1-6
The Integrated Circuit 1-13
Integrated NPN Transistors 1-14
The Case of the Lateral PNP Transistor 1-22
CMOS Transistors 1-23
The Substrate PNP Transistor 1-27
Diodes 1-27
Zener Diodes 1-28
Resistors 1-29
Capacitors 1-32
Other Processes 1-33
CMOS vs. Bipolar 1-34
2 Simulation 2-1
What You Can Simulate 2-2
DC Analysis 2-2
AC Analysis 2-3
Transient Analysis 2-4
The Big Question of Variations 2-6
Models 2-8
The Diode Model 2-8
The Bipolar Transistor Model 2-10
The Model for the Lateral PNP Transistor 2-13
MOS Transistor Models 2-14
Resistor Models 2-16
Models for Capacitors 2-17
Pads and Pins 2-17
Just How Accurate is a Model? 2-18
3 Current Mirrors 3-1
4 The Royal Differential Pair 4-1
5 Current Sources 5-1
Bipolar 5-1
CMOS 5-7
The Ideal Current Source 5-7
6 Time Out: Analog Measures 6-1
dB 6-1
RMS 6-2
Noise 6-4
Fourier Analysis, Distortion 6-6
Frequency Compensation 6-9
7 Bandgap References 7-1
Low-Voltage Bandgap References 7-11
Edition February 2005 All rights reserved

Camenzind: Designing Analog Chips Table of Contents
CMOS Bandgap References 7-13

8 Op Amps 8-1
Bipolar Op-Amps 8-1
CMOS Op-Amps 8-9
Auto-Zero Op-Amps 8-15
9 Comparators 9-1
10 Transconductance Amplifiers 10-1
11 Timers and Oscillators 11-1
Simulation of Oscillators 11-14
LC Oscillators 11-15
Crystal Oscillators 11-16
12 Phase-Locked Loops 12-1
13 Filters 13-1
Active Filters, Low-Pass 13-1
High-Pass Filters 13-6
Band-Pass Filters 13-6
Switched-Capacitor Filters 13-8
14 Power 14-1
Linear Regulators 14-1
Low Drop-Out Regulators 14-4
Switching Regulators 14-8
Linear Power Amplifiers 14-12
Switching Power Amplifiers 14-15
15 A to D and D to A 15-1
Digital to Analog Converters 15-1
Analog to Digital Converters 15-7
The Delta-Sigma Converter 15-8
16 Odds and Ends 16-1
Gilbert Cell 16-1
Multipliers 16-3
Peak Detectors 16-5
Rectifiers and Averaging Circuits 16-7
Thermometers 16-10
Zero-Crossing Detectors 16-12
17 Layout 17-1
Bipolar Transistors 17-1
Lateral PNP Transistors 17-5
Resistors 17-6
CMOS Transistors 17-7
Matching 17-9
Cross-Unders 17-10
Kelvin Connections 17-11
Metal Runs and Ground Connections 17-11
Back-Lapping and Gold-Plating 17-12
DRC and LVS 17-12
References
Index

Camenzind: Designing Analog Chips Analog World
Analog World
"Everything is going digital". Cell phones, television, video disks,

hearing aids, motor controls, audio amplifiers, toys, printers, what have you.
Analog design is obsolete, or will be shortly. Or so most people
think.
Imminent death has been predicted for analog since the advent of the
PC. But it is still here; in fact, analog ICs have been growing at almost
exactly the same rate as digital ones. A digital video disk player has more
analog content than the (analog) VCR ever did.
The explanation is rather simple: the world is fundamentally analog.
Hearing is analog. Vision, taste, touch, smell, analog all. So is lifting and
walking. Generators, motors, loud-speakers, microphones, solenoids,
batteries, antennas, lamps, LEDs, laser diodes, sensors are fundamentally
analog components.
The digital revolution is constructed on top of an analog reality.
This fact simply won't go away. Somewhere, somehow you have to get into
and out of the digital system and connect to the real world.
Unfortunately, the predominance and glamour of digital has done
harm to analog. Too few analog designers are being educated, creating a
void. This leaves decisions affecting analog performance to engineers with
a primarily digital background.
In integrated circuits, the relentless pressure toward faster digital
speed has resulted in ever-decreasing supply voltages, which are anathema
to high-performance analog design. At 350nm (3.3V) there is still enough
headroom for a high-performance analog design, though 5 Volts would be
better. At 180nm (1.8V) the job becomes elaborate and time-consuming
and performance starts to suffer. At 120nm (1.2V) analog design becomes
very difficult even with reduced performance. At 90nm, analog design is
all but impossible.
There are "mixed signal" processes which purportedly allow
digital and analog circuitry on the same chip. A 180nm process, for
example, will have some devices which can work with a higher supply
voltage (e.g. 3 Volts). While such an addition is welcome (if marginal), the
design data (i.e. models) are often inadequate and oriented toward digital
design.

Camenzind: Designing Analog Chips Analog World
Hence this book. It should give you an overview of the world of

analog IC design, so that you can decide what kind of analog function can
and cannot, should and should not be integrated. What should be on the
same chip with digital and what should be separate. And, equally
important, this book should enable you to ask the right questions of the
foundry, so that your design works. The first time.
* * *
You will find that almost all analog ICs contain a number of
recognizable circuit elements, functional blocks with just a few transistors.
These elements have proven useful and thus re-appear in design after
design. Thus it makes sense to first look at such things as current mirrors,
compound transistors, differential stages, cascodes, active loads, Darlington
connections or current sources in some detail and then examine how they
are best put together to form whole functions.
* * *
Academic text books on IC design are often filled with mathematics.

It is important to understand the fundamentals, but it is a waste of time to
calculate every detail of a design. Let the simulator do this chore, it can do
it better and faster than any human being. An analysis will tell you within
seconds if you are on the right track and how well your circuit performs.
Assuming that you have competent models and a capable simulator, an
analysis can teach you more about devices and circuits than words and
diagrams on a page.

Camenzind: Designing Analog Chips Chapter 1: Devices
1 Devices
Let's assume your IC design needs an operational amplifier. Which

one? If you check the data-books of linear IC suppliers, you'll find
hundreds of them. Some have low current consumption, but are slow.
Others are quite complex, but feature rail-to-rail inputs and outputs. There
are inputs which are factory-trimmed for low offset voltages, outputs for
high currents, designs for a single supply voltage, very fast devices, etc.
Here is the inherent problem with analog building blocks: there are
no ideal designs, just configurations which can be optimized for a particular
application. If you envisioned a library from which you can pull various
analog building blocks and insert them into your design, you are about to
experience a rude shock: this library would have to be very large,
containing just about every operational amplifier (and all other linear
functions) listed in the various data-books. If it doesn't, your IC design is
bound to be inferior to one done with individual ICs.
In short: There are no standard analog cells. If your application is
the least bit demanding, you find yourself either modifying previously used
blocks or designing new ones. In either case you need to work on the
device level, connecting together transistors, resistors and rather small
capacitors.
To do this you need to know what devices are available and what
their limitations are. But above all you need to understand devices in some
detail. The easiest way to learn about complex technical things is to follow
their discovery, to have the knowledge gained by the earlier men and
women (who pioneered the field) unfold in the same way they brought it to
light.
Edition February 2005 1-1 All rights reserved

Semiconductors
In 1874 Ferdinand Braun was a 24-year old teacher in Leipzig,
Germany. He published a paper which was nothing short of revolutionary:
he had found that some materials violated Ohm's law. Using naturally
formed crystals of Galena (lead sulfite, the chief ore mineral of lead) and
other sulfites, he pressed a spring-loaded metal tip against their surfaces and
observed that the current through this arrangement was dependent on the
polarity of the applied voltage. Even more puzzling was the fact that, in the
direction which had better conduction, the resistance decreased as the
current was increased.
What Braun (who later would give us the CRT) had discovered, we
now know as the diode, or rectifier. It was not a very good one, there was
only a 30% difference between forward and reverse current. And there
were no practical applications. Braun could not explain the effect, nor
could anybody else.
In 1879 Edwin Hall of Johns Hopkins University discovered what
was later named the Hall Effect: when you pass a magnetic field through a
piece of metal it deflects the current running through the metal. In all the
metals he tried the deflection was to one side; he was greatly relieved to see
that this confirmed the negative charge on the electron.
But then the surprise came. In some materials the deflection went
the other way. Where there perhaps positive electrons?
Nothing much happened until about 1904. Radio appeared on the
scene and needed a "detector". The signal was amplitude modulated and to
make the music or speech audible the radio frequency needed to be rectified
(i.e. averaged). Thus, 30 years after Braun's discovery, the "odd behavior"
of a wire touching Galena (and now many other materials, such as silicon
carbide, tellurium and silicon) found a practical application. The device
was called the "Cat's whisker", but it actually didn't work very well; one
had to try several spots on the crystal until one was found which produced a
loud enough signal.
And it was replaced almost immediately by the vacuum tube, which
could not only rectify but amplify as well. Thus the semiconductor rectifier
(or diode) went out of fashion.
It was not until 1927 that another practical application appeared:
large-area rectifiers. These were messy, bulky contraptions using copper-
oxide (and later selenium) to produce DC from line voltage, chiefly to
charge car batteries. But there was still no understanding of how these
devices worked.

In the background, mostly at universities and large corporate

laboratories, some research went on, despite the fact that there was no
semiconductor industry yet. In 1931 A.H. Wilson came up with a complete
model of energy bands: electrons exist only at discrete levels, each with a
higher energy than the lower one; only two electrons can exist at the same
level, but they have opposite spins; at the last (or highest level) are the
valence electrons and there is a gap in energy to the ultimate one, the
conduction band; once they reached that last level, conduction happens by
accelerating the electrons in an electric field.
The theory was fine, but it took 15 years for someone to make a
connection between it and the diode.
There were two problems masking the real semiconductor effects.
First, all the behaviors so far noticed were surface effects. The cat's whisker
applied a metal wire, the copper-oxide and selenium rectifier metal plates.
Today this is recognized as a rather specialized configuration, only
surviving in the Schottky diode. Second, the semiconductor material was
anything but pure, containing elements and molecules which counteracted
the desired behavior.
Then World-War II happened and with it came radar. To get
adequate resolution, radar needed to operate at high frequencies. Vacuum
tubes were too slow, so the discarded "cat's whisker" came into focus again
(employed right after the antenna to rectify the wave so it could be mixed
with a local oscillator and produce a lower frequency, which could be
handled by vacuum tubes).
This time a world-wide emergency drove the effort, with plenty of
funding for several teams. They started with the "cat's whisker" and tried
to determine what made it so fickle and unreliable. It became immediately
obvious that purer material was required, and that this material should be in
the form of a single crystal. When they heated part of a crystal close to the
melting point and moved the heated zone, the foreign materials moved with
it. And now they realized that some of these impurities were actually
required to get the diode effect. And these impurities all fell into very
specific places within the periodic table of elements.
Silicon and germanium both have a valence of four. Valence
simply means that in the outermost layer of electron orbits there are four
electrons. Silicon, for example, is element number 14, meaning it has a
total of 14 electrons. The first orbit (or energy level) has two electrons, the
second eight and the third four.
The outermost orbits of the atoms touch each other and the electrons
in this orbit don't stay with one particular atom, they move from orbit to
orbit. It is this sharing of electrons that hold the atoms together. And this

ability to move from atom to atom is also the basis of electrical conduction:
in conductors the electrons roam widely and are easily enticed to move in
an electrical field, whereas in an insulator they stay close to home.
Electrically, pure silicon is a terribly uninteresting material. It is an
insulator, but not a very good one. The fun begins when we add the right
impurities, or dopants.
Just to the right of silicon in the periodic table is phosphorus,
element number 15. Like Silicon, it has two electrons in the first orbit,
eight in the second but there are five in the third. Now let's say we were
able to pluck out an atom in a block of silicon and replace it with a
phosphorus atom. Four of the valence electrons of this new atom will
circulate with the silicon electrons, but the fifth one won't fit in. This
excess electron creates a negative charge and the silicon becomes what we
now call n-type.
This introduction of excess electrons is unlike static charge. When
you brush your hair so that it stands upright, you have simply moved some
electrons temporarily. When you "dope" silicon, the charge is permanent,
fixed in the crystal lattice (and does not become a battery).
Similarly, to the left of Silicon and one space up in the periodic table
is boron, element number 5. It has two electrons in a first level and three in
a second, a valence of three. If we replace a silicon atom with a boron one,
there is an electron missing and we create a positive charge, or p-type
material. As with the excess electron in n-type silicon, we can apply an
electric field and cause a current to flow, but the net-effect is the flow of
holes, not electrons. This is what makes the Hall effect go the wrong way.
It is important to understand this mechanism of moving holes and
electrons in doped semiconductors. In n-type material an excess
phosphorus electron wanders into the path of a neighboring silicon electron
and displaces it. The displaced electron then takes the orbit of another one
and so on until the last electron ends up at the starting point, the phosphorus
atom.
This endless game of musical chairs - proceeding at near the speed
of light - depends greatly on the temperature. At absolute zero there is no
movement. At about -60oC the movement is sufficient for semiconductor
effect to start in silicon. At about 200oC there is so much movement that
silicon practically becomes a conductor. It is only within a relatively
narrow range, about -55oC to 150oC, that silicon is a useful semiconductor.
In p-type material the movement starts with an electron in the
neighborhood of the boron atom. It fills the vacancy and then is itself
replaced by another electron and so on until the first electron moves away

from the boron atom again. The moving is done by electrons, but the net
effect is a moving hole.
When an electric field is present the movement takes on a direction:
electrons flow toward the positive electrode and are replaced by other
electrons flowing out of the negative electrode.
It is amazing how few dopants it takes to make n-type or p-type
material. Silicon has 5x1022 atoms per cubic centimeter. A doping level
can easily be as low as 5x1015 boron or phosphorus atoms per cubic
centimeter, i.e. one dopant atom for every 10 million silicon atoms. No
wonder it took so long to discover the true nature of the semiconductor
effects; in nature, the number of miscellaneous impurities is far larger than
one in 10 million.
The Diode
Even with a dopant present silicon is uninteresting. It is not a good
conductor and as a resistor it is inferior to metal film or even carbon. But if
we have both n-type and p-type atoms in the same silicon crystal, things
suddenly happen.
Opposite charges attract each other, so the excess electrons near the
border of the n-type section move into the p-type material and stay there.
An electron fills a hole and the electric charges cancel each other.
This only happens over a short distance, as far as an electron (or
hole) can roam. The resulting region is called the space-charge layer or
depletion region.
Now suppose you
connect a voltage to the
two terminals. If the p-
region is connected to the
negative terminal of the
supply and the n-region to
the positive one, you
simply push the charges
away from each other,
enlarging the depletion
region.
Fig. 1-1: A depletion region forms between p-
doped and n-doped semiconductor areas.
If, however, the p-
region is positive and the
n-region negative, you push the charges closer together as the voltage
increases. The closer proximity forces more and electrons and holes to

cross the depletion region. The effect is exponential: at 0.3 Volts (at room
temperature) very little current flows; at 0.6 Volts the current is substantial
and at 0.9 Volts very large.
The expression for the diode voltage is:
 Vd⋅q 
I1 = Is  e kT − 1
kT I1
Vd = ln or
q Is  
 
where Vd = voltage across the diode
k = Boltzman constant (1.38E-23 Joules/Kelvin)
T = the absolute temperature in Kelvin
q = the electron charge (1.6E-19 Coulombs)
I1 = the actual current through the diode
and Is = diffusion current
Note that 1.38E-23 is a more convenient notation for 1.38x10-23.
The diffusion current Is depends on the doping level of n-type and
p-type impurities, the area of the diode and (to a very high degree) on
temperature. A reasonable starting point for a small-geometry IC diode is
Is=1E-16.
The equations neglect a few things. There is a limit in the voltage
that can be applied in the reverse direction. Similar to an arc-over in any
insulator, there comes a point when the electric field becomes too large and
the opposing charges crash into each other. This breakdown voltage
depends on the concentration of dopants: the higher the concentration, the
lower the breakdown voltage.
There is a price to be paid for high breakdown voltage. As the
dopant concentration is lowered, the depletion layer becomes larger and the
higher voltage pushes it deeper yet. This distance must be accommodated
in the design.
The opposing charges in a semiconductor junction are no different
from those on the plates of a capacitor. So every junction has a capacitance;
but since the distance between the electrons and holes changes with applied
voltage, the capacitance becomes voltage dependent. The lower the
voltage, the higher the capacitance, increasing right into the forward
direction.
Lastly, there is resistance in the semiconductor material not taken up
by the depletion region. For our "typical" concentration of 5E15 (atoms per
cubic centimeter, giving a practical breakdown voltage in an IC of about 25
Volts), the resistivity is about 1 Ohm-cm for phosphorus (n-type) and 3
Ohm-cm for boron (p-type). For comparison, aluminum has a resistivity of
2.8 microOhm-cm, copper 1.7 microOhm-cm. Resistivity (ρ or rho) is

measured between opposite surfaces of a cube of material with a side-length

(w, h, l) of 1cm (10mm):
R∗ w∗ h Ohm∗ cm∗ cm
ρ= = = Ohm∗ cm (or Ohm-cm)
l cm
The (Bipolar) Transistor

At the time of the first serious work on the semiconductor diode,
Bell Laboratories in New Jersey was already world-famous. It attracted the
brightest scientists and, even among those, Bill Shockley was a stand-out.
In 1938 Shockley teamed up with Walter Brattain to investigate
semiconductors.
The depletion layer intrigued Shockley. There was a faint similarity
to the vacuum diode. It occurred to Shockley that, if he could somehow
insert a grid into this region, it might be possible to control the amount of
current flowing in a copper-oxide rectifier, creating the solid-state
equivalent of the vacuum triode. Shockley went to Brattain with the idea
and Brattain was amused. The same idea had occurred to him too; he had
even calculated the dimensions for such a grid, which turned out to be
impractically small. Shockley tried it anyway and couldn't make it work.
Brattain had been right.
Shockley was not a man easily defeated, though. He modified his
idea and came up with a different principle of operation. He conceived that,
since a relatively small number of electrons or holes are responsible for
conduction in semiconductors and they each carry a charge, he could place
a metal electrode near the surface, connect it to a voltage and thus either
pull these carriers toward the surface or push them away from it. Therefore,
he thought, the conduction of the region nearest the surface could be altered
at will. He tried it -- and it didn't work either. The idea was identical to
today's MOS transistor.
The work stopped there; both Shockley and Brattain were assigned
to other projects during the war. But in 1945 Shockley was made co-
supervisor of a solid-state physics group which included Brattain. Shockley
was 35, Brattain 43. The progress made in refining silicon and germanium
was not lost on Shockley; he decided to try his idea for an amplifying
device again and had a thin film of silicon deposited, topped with an
insulated control electrode. It still didn't work; no matter what voltage was
applied to the control electrode, there was no discernable change in current
through the silicon film. Shockley was puzzled; according to his

calculations there should have been a large change. But the effect - if there
was any - was at least 1500 times smaller than theoretically predicted.
It was at this time, that John Bardeen, 37, joined Shockley's group.
He looked at Shockley's failed experiment and mulled it over in his head for
a few months. In March 1946 he came up with an explanation: it was the
surface of the silicon which killed the effect. Where the silicon stops, the
four valence electrons are no longer neatly tied up by the neighboring
atoms. Bardeen correctly perceived that some of them were left dangling
and thus produced a surface charge (or voltage), which blocked any voltage
applied to an external control electrode.
With this theoretical breakthrough the group now decided to change
directions; instead of attempting to make a device, they investigated the
fundamentals of semiconductor surfaces. It was a long, painstaking
investigation; it took more than a year. On November 17, 1947 Robert B.
Gibney, another member of the group and a physical chemist, suggested
using an electrolyte to counteract the surface charge. On November 20 he
and Brattain wrote a patent disclosure for an amplifying device as tried by
Shockley but using electrolyte on the surface. Then they went to the lab and
made one. The electrolyte was extracted from an electrolytic capacitor with
a hammer and nail. The device worked, the electrolyte did precisely the job
that Gibney thought it would.
But, although this "field effect" device amplified, it was very slow,
amplifying nothing faster than about 8Hz. Brattain and Bardeen suspected
that it was the electrolyte that slowed down the device so, on December 16,
1947, they tried a different approach: a gold spot with a small hole in the
center was evaporated onto germanium, on top of the insulating oxide. The
idea was to place a sharp point-contact in the center without touching the
gold ring, so that the point would make contact with the germanium, while
the insulated gold ring would shield the surface. And now, for the first
time, they got amplification.
There was only one thing wrong with this device: it didn't work as
expected. A positive voltage at the control terminal increased the current
through the device when, according to their theory, it should have decreased
it. Bardeen and Brattain investigated and found they had inadvertently
washed off the oxide before evaporating the gold, so that the gold was in
contact with the germanium. What they were observing was an entirely
different effect, an injection of carriers by the point contact. They realized
that, to make such a device efficient, the distance between the two contacts
at the surface needed to be very small. They evaporated a new gold spot,
split it in half with a razorblade and placed two point contacts on top. Now
the device worked even better and they demonstrated it to the Bell

management on December 23, 1947.

For half a year Bell kept the breakthrough a secret. Bardeen and
Brattain published a paper on June 25. 1948 and on June 30 a press
conference was held in New York. The announcement made little
impression; the New York Times devoted a few lines to it on page 46.
Shockley had been disappointed by the turn of events, he had not
been part of the final breakthrough. But he realized that, even though there
was a working device, the battle wasn't over yet. No-one within the group
really understood precisely how the transistor worked. So, in the early days
of January 1948 Shockley sat down and tried to figure out what was going
on between the two point contacts. And in the process he conceived a much
better structure: the junction transistor.
It was a brilliant analysis and holds up to this day. In a bipolar
transistor there is a current flowing between the base and emitter terminals,
which is a diode. Thus electrons flow from the emitter to the base (so
named because in the original point-contact transistor it was the bulk of the
material). Since the base is p-doped, these electrons are the minority
carriers in the base (hence the name bipolar transistor - carriers of both
polarities are needed for the effect). A few of them will reach the base
terminal. But if the base is
lightly doped and very thin
most of them will be
attracted by the positive
collector voltage before
they re-combine with a
hole in the base. In a good
transistor 100 or even 500
of the electrons will be
side-tracked to the
Fig 1-2: The electrons in the base of an NPN collector while one goes to
transistor are intended to flow to the base terminal
but, if the base is very thin, most of them are the base terminal. Thus we
diverted by the positive potential of the collector.
have a current gain of 100 or even 500.

The bipolar transistor is an odd
amplifier, quite non-linear and somewhat
difficult to use. Consider the input
terminal, the base. It is a diode (with
respect to the emitter). You need to lift its
voltage up to at least 0.6 Volts (at room
temperature) for any current to flow.
From that point on the current increases Fig. 1-3: The current flow and gain
of an NPN transistor.

exponentially, both in the base and the collector. It is not a linear voltage
amplifier; only the currents have a (more or less) linear relationship.
Also notice that the emitter current is always larger than that of the
collector, since it contains both the collector and base current.
We have shown here an NPN transistor. If we reverse all the doping
and the voltages we create a PNP transistor. It works the same way in every
respect except that it is a bit handicapped: it is slower and has a lower gain;
holes, now the minority carriers in the base, just don't move as well as
electrons.
The point-contact transistor was a nightmare to manufacture and had
very poor reliability. Also, these devices were made from germanium,
which has a rather limited useful temperature range. The junction
transistors were made by alloying dopant materials on either side of a flat
piece of germanium or silicon. It was difficult to make the base uniformly
thin and the process created considerable leakage current.
The next big step was again invented at Bell Labs: diffusion. At
room temperature gases mix even if they are held perfectly still. This
happens because each atom or molecule moves around randomly due to the
energy it receives by temperature. The higher the temperature, the more
pronounced is this movement and thus the mixing or diffusion. If the
temperature is high enough (e.g. over 1000oC) such gases can even diffuse
into solid material, though their diffusion speed decreases enormously.
Thus, for example, silicon exposed in a high-temperature furnace to n-type
impurity (gas) atoms develops an n-layer at its surface with a depth as far as
the impurities penetrate. This may require a temperature close to the
melting point of silicon and take several hours for a penetration of just a
few micro-meters, but it is far more controlled than alloying.
Moreover, you can dope repeatedly. Suppose you have a piece of
silicon which has been doped n-type. If you diffuse p-type impurities into
the surface, you convert a layer from n-type to p-type if there are more p-
type impurities than n-type. The junction is located at the depth at which
the two impurities are equal in concentration. A second diffusion of a yet
higher concentration can then convert the material back to n-type again.
However, you have to pay attention to the fact that subsequent exposure to
high temperature causes any previous layer to diffuse further.
There are a few more dopants available too: p-type gallium (rarely
used) and n-type arsenic and antimony. The latter two have the advantage
that they diffuse more slowly than phosphorus or boron. For this reason
they are primarily used early in the process and are thus less affected by
subsequent diffusions.
When, in 1956, the three inventors of the transistor were awarded

the Nobel Prize for physics, only Walter Brattain was still at Bell
Laboratories. John Bardeen had left in 1951 to become a professor at the
University of Illinois and, for his research there in superconductivity, he
received a second Nobel Prize in 1972.
Bill Shockley left Bell Labs in 1954. Banking on his reputation,
which had risen proportionally to the acceptance of the transistor, he
managed to strike a deal with the Beckman Instruments Company. A
subsidiary, called the Shockley Semiconductor Laboratories, was set up in
Palo Alto, California. Shockley's fame had risen to such a height that he
could pick some of the best people. Within a year he had some 20 people -
predominantly Ph.D.s - working for him, among them Robert Noyce, 28,
Gordon Moore, 27, and Jean Hoerni, 32.
For all of these people there was a brief period of fascination after
they joined. But then the true Bill Shockley appeared from behind the glitter
of fame and they discovered that Shockley was, in fact, a rather erratic and
unpleasant man. He would fire his employees for minor mistakes, throw
tantrums over trivial problems and change directions for no apparent
reasons. He incessantly tried innovative management techniques, such as
posting everybody's salaries on the bulletin board.
Noyce and Moore were pushing Shockley to make silicon transistors
using the diffusion approach. Shockley wasn't interested; his hope was for
his laboratory to come up with an entirely new device, a device which
would represent as large a step over the transistor as the transistor had been
over the vacuum tube.
Now totally dissatisfied, the crew talked to Arnold Beckman, the
president of the parent company, and informed him of the impossible
situation. Beckman promised to hire a business-minded individual who
could act as buffer between Shockley and his staff. But the solution didn't
work, Shockley refused to let go of the day-to-day decision-making. Out of
patience, eight staff members reached a deal with the Fairchild Camera and
Instrument Company and, in October 1957, the group departed.
The new company, called Fairchild Semiconductor, was at first an
independent operation, with Fairchild Camera and Instrument holding an
option for a buy-out. The product they began to develop was the one they
had proposed to Shockley. The detailed structure of this device, called the
Mesa transistor, had been tried in germanium before, but not in silicon. It
required two diffusions, both into the same side of a silicon wafer. The first
diffusion was p-type, the second n-type, and the difference in depth between
the two layers created the base region which, for the first time, could be
made with a high degree of accuracy. The top surface of the transistor was
then masked with wax and the exposed silicon etched away, giving the

remaining piece a mesa-like shape.

Because of its superior performance, sales of the Mesa transistor
took off almost immediately, reaching $ 7 million in 1959. But there were
also problems. The most serious one concerned the reliability of the Mesa
transistor. The etched silicon chip was soldered onto the bottom of a small
metal case, leads were attached to the top regions and then the case was
welded shut. Tiny metal particles, ejected during the welding process,
floated around inside the case and kept on shorting out the exposed p-n
junctions.
Silicon rapidly grows a thin oxide layer when it is exposed to air.
This is better known as glass (silicon-dioxide) and its growth can be
enhanced by moisture at high temperature. Some of the dopant gases used
in diffusion (such as gallium) can penetrate this oxide layer, while others
are stopped by it. There was, therefore, a possibility that the oxide layer
could be used as a mask. If the oxide were to be etched off in some places
but not in others and suitable dopant gases used, diffusion would take place
only in the areas without oxide. But a study done at Bell Laboratories came
to the conclusion that an oxide layer exposed to a diffusion is left
contaminated and must subsequently be replaced by a freshly grown one.
This bothered Hoerni. He didn't see any reason why the oxide layer
could not be used as a diffusion mask for both diffusions -- provided he
would use dopant gases which were stopped by the oxide - and why the
oxide should subsequently be regarded as contaminated. So he tried it -- as
an unofficial side project -- and out of the trial came an advance ranking in
importance second only to the transistor itself: the planar process.
In preparation for the first diffusion Hoerni spread a photosensitive
and etch-resistant coating (photoresist) over the top of the oxide and
exposed it through a photographic plate (mask) carrying the patterns of the
base regions, using the photographic techniques already developed for
"printed" circuits. The subsequent etching then only removed the oxide in
the regions where p-type impurities were to be diffused. After the diffusion
he closed these oxide "windows" again by placing the wafer in high-
temperature moisture and then repeated the steps for the second (emitter)
diffusion. In a third masking step windows could then be etched in the
oxide to make contact to the two diffused layers. He then evaporated
aluminum onto the top surface of the wafer and patterned it with the same
photographic techniques. The wafer could then be scribed (like glass) and
broken into individual transistor chips.
The planar process had a whole series of advantages. Of most
immediate importance was the fact that the junction was automatically
protected by the oxide, one of the best insulators known. No longer could

the metal particles from the welding of the case short it out. Secondly,
photographic methods could be used to delineate not just one but hundreds
of transistors simultaneously. Thus individual, delicate masking of each
transistor was no longer required, giving the planar transistor a huge
potential for reduced cost. Noyce, who was by now the general manager,
saw the advantage of the planar process and quietly moved it into
production.
There was another advantage to the planar transistor: once the
dopant enters the silicon it diffuses in all directions, including sideways.
The P-N junction, therefore, ends up underneath the oxide, never exposed to
either human handling or the contamination of air. For this reason the planar
junction is the cleanest (and most stable) junction ever produced. Fairchild's
customers who, in early 1959, didn't know that their transistors were now
being manufactured by an entirely new process, were surprised to find
leakage currents one thousand times smaller than those of previous
shipments.
While Fairchild flourished, Shockley Transistor went downhill. It
was sold twice, then closed in 1969. Shockley became interested in
sociology and announced a theory called "dysgenics", which proposed that
poor people were doomed to have low IQs. By the time he died in 1989 his
reputation was ruined.
The Integrated Circuit

In July 1958 Jack Kilby of Texas Instruments conceived that a block
of germanium or silicon could be host to not only transistors and diodes, but
resistors and (junction) capacitors as well. This appeared to be enough of a
variety to make a small circuit, all of it in the same block of silicon.
The idea was good, but his approach cumbersome. To insulate the
various components from each other Kilby etched the silicon, in some areas
all the way through. To connect them together he used gold wires. The
circuit was very small to be sure, but it was a production nightmare. Each
tiny block of silicon had to be made individually, including the patterning,
etching and wiring. When TI's attorneys prepared a patent application they
looked in horror at the Rube Goldberg-like drawings and had Kilby put in
some words saying that interconnection could also be made by laying down
a layer of gold. How this could be done over this three-dimensional
landscape he didn't say.
While Kilby was working on his circuits in Texas, a similar but far
more elegant idea occurred to Robert Noyce in California. Noyce's

motivation was primarily cost, not size. He realized that it didn't make
sense to fabricate precisely arranged transistors on a wafer, cut them apart,
place them in a housing and arrange them again in on a circuit board; if the
additional components on the circuit board could be placed on the wafer, a
considerable number of manufacturing steps could be saved. Noyce had no
problem visualizing capacitors and resistors made in silicon, he was
constantly dealing with these (unwanted) effects. What was needed,
though, was an inexpensive way to connect all these components on the
wafer. The idea of using wires had no chance in Noyce's mind, it would
have simply been too expensive. But he saw that, in the planar process, this
problem was already solved: the aluminum layer used to connect the
transistors and the wires could also be used between the components.
In1959 Noyce entered his idea into his notebook and filed for a
patent application. Kilby's and Noyce's patent applications were clearly in
interference and a bitter battle between the two companies started in the
courts. Texas Instruments won because Kilby application mentioned a thin
film of gold, thus seemingly anticipating Noyce. Fairchild appealed.
While the two patents were fought over in the courts, neither TI nor
Fairchild could collect any royalties for integrated circuit, which were
already showing explosive growth. So the two companies came to an
agreement, declaring Kilby and Noyce co-inventors of the integrated circuit.
Shortly after this the appeals court handed down its decision: Noyce, not
Kilby, was declared the inventor of the IC.
It could not have been otherwise. Even today every single IC is
made exactly as Noyce described it, while Kilby's approach has long been
abandoned. But the most important contributor to the invention of the IC
was clearly Jean Hoerni with his planar process, for which he has never
been adequately recognized. The planar process rates as one of the great
inventions of the 20th century.
Robert Noyce died in 1990 at age 62. In 2000 Jack Kilby won the
Nobel Prize for the invention of the integrated circuit
Let's take a closer look at a basic processing step in the Planar

process. First, you need a mask, a piece of flat glass, with an opaque
pattern on it. The pattern has been generated optically or, more likely, with
an electron beam.
The silicon wafer is first oxidized, i.e. a thin SiO2 layer is grown, for
example by exposing the wafer to steam in a furnace. Instead of oxide,
nitride or a combination of oxide and nitride is also used. On top of the
oxide a thin layer of "photoresist" is spread, a light-sensitive emulsion
similar to that on a photograph.

Light is then projected through the mask onto the wafer. The higher
the frequency of the light, the
greater the detail, so ultra-violet
light or even x-rays are used.
The photoresist is then
developed and the portions not
exposed to light are washed off.
Fig. 1-4: The first step: A light-sensitive and etch (There are both positive and
resistant layer (photoresist) is spread on the wafer
and exposed to light through a mask.
negative photoresists; you have
the choice of removing the areas
Fig. 1-4: The first step: A light-sensitive and which are either exposed or not
etch-resistant layer (photoresist) is spread on
the wafer and exposed to light through the
exposed to light).
mask. Next the entire wafer is
immersed in an acid which
removes the oxide in the areas
where it is not protected by the
photoresist. In more modern
processes a plasma is used; acid
etches not only downward but
also slightly sideways
underneath the photoresist, while
Fig. 1-5: The photoresist is developed like a plasma etches downward only.
photograph and the wafer is ready for etching. The wafer is then placed
into a furnace (a quartz tube
heated to greater than 1000oC).
A gas carrying the desired
dopant (in this case boron,
arsenic or antimony) swirls
around the wafer and slowly
Fig. 1-6: The oxide is etched away and the diffuses into the surface.
photoresist is removed.
Note two important facts
here: 1. There is a crowding of
dopants near the surface of the
silicon. With time they will
diffuse deeper into the silicon,
but there will always be more
dopants near the surface. Thus
any diffused region has a marked
gradient. 2. Dopants not only
Fig. 1-7: A gas containing N-type dopants
(boron, arsenic or antimony) diffuses slowly into diffuse downward, but also side-
the surface of the wafer at high temperature. ways. (Since supply is more

limited at the very edge, the side-ways diffusion extends to only about half
the distance of the downward one). This places the junction (where n = p)
underneath the oxide and is thus never exposed to the (dirty) environment.
After diffusion the exposed silicon surface is covered again by an
oxide layer so that the wafer is ready for the next masking step, which could
be another diffusion or the
etching of contact holes.
There is an important
feature here, which should not
go unnoticed. SiO2 is glass,
Fig. 1-8: After the diffusion the oxide is re- which is transparent to light.
grown, ready for the next masking step.
The light is reflected at the
bottom of the oxide by the
silicon and interference patterns are created, i.e. the sum of direct and the
reflected light eliminates some frequencies. Thus the color of the oxide
layer depends on its thickness. This not only makes for beautiful
photographs but, more importantly, it allows subsequent masks to be
precisely aligned with previous ones.
Here then is one form of an NPN transistor made with the planar
process. The substrate (the starting wafer) is doped p-type as the silicon is
grown. There are three diffusions in succession, the first being rather deep.
After the diffusions, contact holes are made (with the same basic photoresist
process), aluminum is deposited over the entire wafer, patterned (another
photoresist step) and etched away where it is not wanted.
Alas, this transistor
has a rather significant
shortcoming: high collector
resistance. The current has
to flow through the region
between the base and the
substrate. That is the far end
of the collector diffusion, the
end which has the fewest
Fig. 1-9: A simple planar NPN transistor. dopant atoms and therefore
the highest resistance.
Since the invention of the planar process a few more ways of
fabricating have been added:
Epitaxy. If you strip a silicon wafer of its oxide and put it into a
furnace which is filled with gas containing not only a dopant but also
silicon, you can grow a doped single-crystal layer. As the atoms carried by
the gas deposit themselves on the surface of the wafer, they will align

themselves according to the existing crystal structure.

You can also precede this by diffusing regions into the original
wafer, so that you will have areas of high concentration underneath the
epitaxial layer. Even though these regions are buried, it is still possible to
align subsequent diffusions to them. When a diffused area is re-oxidized, a
small amount of silicon is consumed (the Si in SiO2), thus creating a small
depression in the surface. The edges of these depressions are visible at the
top surface of the epitaxial layer, though the image tends to be blurry and is
shifted (in most processes) along the crystal axis (around 45o).
Ion Implantation. You can literally shoot dopant atoms into silicon
by electrically charging (ionizing) them and then accelerating them with a
high voltage (several hundred thousand volts). The treatment is somewhat
brutal, the newly arrived atoms don't end up neatly aligned in the crystal
structure and an annealing heat cycle is necessary to let the atoms align
themselves into a crystal structure.
The number of dopant atoms introduced is generally more accurate
in ion implantation than in diffusion. Also you can aim implantation for a
certain depth (but not very deep). In the subsequent heat cycle (and during
subsequent diffusions) the dopant atoms will diffuse and thus widen the
layer. The maximum concentration, however, is then not at the surface, but
at a chosen depth.
We now have arrived at a modern NPN transistor as made in a
bipolar (or BICMOS) process. Before growing the epitaxial layer, a heavily
doped (thus N+) buried layer is diffused (or ion implanted) into the p-type
substrate. During epitaxy it diffuses somewhat, both into the substrate and
the new epitaxial layer.
The next
diffusion is the
isolation. It is deep
(and, therefore, also
wide); it has to connect
up with the substrate,
so that the entire n-type
collector region is
surrounded by p-type
Fig. 1-10: A much improved planar, integrated NPN
transistor. The buried layer and sinker lowers the regions. A second n-
collector resistance. type diffusion connects
up with the buried layer
(and the emitter N+ diffusion is used on top of it simply because it's
available at no cost). Now the collector current has a (fairly) low-resistance
path.

This transistor is isolated from its neighbors (and other components)

as long as the substrate is held at the most negative voltage in the circuit
(junction isolation). In this way the collector-substrate junction is always
reverse-biased and only leakage current (pico-amperes) flows.
There are some flaws and limitations in the performance of this or
any other bipolar transistor:
Early Effect, named after Jim Early (then at Bell Labs, later at
Fairchild), who explained it first. Ideally the collector current should be
equal to the base current multiplied by a constant gain (hFE or beta). But,
as we have seen above, each p-n junction has two depletion layers. For the
collector-base junction, one depletion layer extends into the collector, the
other into the base. The base is almost always more heavily doped than the
collector, so its depletion layer
is fairly shallow. However, the 240
220
base is also very thin, so even a 200
shallow depletion layer takes 180

Early Effect
160
up a significant portion of the 140
Ic / µA
base depth. As the collector 120

100
voltage increases, the depletion 80
layers widen. In the collector 60

40
region this has little effect (as 20
long as it doesn't hit the other 00 1 2 3 4
side of the collector), but in the Vc/V 1V/div
base region it narrows the

base-width. Since the gain of a Fig. 1-11: Even with a constant base
bipolar transistor is very much current the collector current increases with
the collector-emitter voltage because the
dependent on the base-width, the depletion layer narrows the base-width.
gain simply increases as the
effective base-width decreases.
If you draw a straight line, extending the slope (from 0.4 to 5 Volts)
into the negative quadrant and let it intersect with the zero-current line, you
get the Early Voltage. In this case, for a 5-Volt process, the Early voltage
is -15 Volts (but is generally expressed as 15V). Depending on the chosen
base-width, it can be less than that and the slope correspondingly steeper.
Gain versus Current. For any bipolar transistor the current gain falls off
both at low and high current.
First, the low end. There is always a leakage current across any
junction; for a perfectly clean surface this is the diffusion current. In the
base-emitter junction this leakage current takes away a portion of the
supplied base current. In our graph here the current shunted by leakage at

the low end (10nA Ie, or about 50pA Ib) amounts to 33% of Ib, i.e. the gain
has dropped by one third.
If you extend this plot to much lower current, you will see the gain
rise to almost infinity. This is nothing more than the effect of the collector-
base leakage current.
At the high end two effects take place simultaneously: 1. The
number of electrons present in the base simply becomes so large that they
are no longer the minority carriers and the whole effect comes to a halt. 2.
The base current must flow
350
from the contact to the flat
area between the emitter and 300
collector. At low current this 250

is no problem, the resistance Current Gain /
in the base is sufficiently 200
small. But as the collector 150
current increases (and with it

100
the base current), the
resistance in this flat region 50
of the base causes a

10n 100n 1µ 10µ 100µ 1m 10m
significant voltage drop, and
Emitter Current / A
the far end gets less current.
Eventually, as the current is Fig. 1-12: The current gain (hFE) of a
increased even more, only the bipolar transistor drops off both at low and
edge of the emitter on the side of high currents.
the base contact is active. Thus
the high-current capability of a bipolar transistor is determined not by the
emitter area, but by the
active emitter length, i.e.
emitter periphery to which
the base can supply current
through low resistance. A
good starting point for the
maximum current (at which
the gain drops to 50%) is
1.5mA per um of active
emitter length, but this value
varies from process to
process.
To increase the
Fig. 1-13: Minimum-geometry NPN transistor on current capability of a
the left and higher-current design on the right. bipolar transistor you can

place base contacts on both sides of the emitter and lengthen the emitter.
Shown here on the left is the top view of a minimum-geometry transistor
and on the right a version for higher current.
To make the life of a designer easier, the isolation pattern is usually
drawn as a rectangle and then inverted when making the mask, i.e. the
isolation diffusion is actually between devices, not in the device area.
Many processes require that all contacts be the same size, in which
case the contact rectangles must be broken up into small, identical (and
properly spaced) squares.
Be aware, that transistors of different sizes (as drawn here) do not
match well. At low current a large emitter area produces a higher gain than
a small one, because the minority carriers have a higher chance to be
captured by the collector. If you want to produce a precise ratio, use only
one emitter size and identical base contacts. The emitters can be in a
common base area and the collector size is of no consequence except for
collector resistance (or saturation voltage).
Substrate Current. There is only leakage current across the
collector-substrate junction, unless the transistor saturates.
Assume the collector is connected through a resistor to the positive
supply voltage and the base is driven so hard that the collector voltage drops
to near the potential of the emitter (termed
Collector
saturation).
There are now two diodes in parallel and
the base current has two paths; the new one forms a Base NPN
PNP transistor with the NPN base becoming the
emitter, the NPN collector the base and the
PNP
substrate the collector. Since the NPN collector is
much larger than its emitter, some (or all) of the
base current flows to the substrate.
Emitter Substrate
There is little danger in this, except when
you drive the base very hard, trying to get the Fig. 1-14: When an NPN
lowest possible collector voltage, or if you have transistor saturates a
stray PNP device leaks
many saturating NPN transistors. The path in the current to the substrate.
substrate from a transistor to the -V connection has
some resistance. If the substrate current is so large
that the voltage drop across this resistance can forward-bias some substrate-
collector junction on the way, you may get some really bad effects,
including latch-up.
Maximum Voltage. To get a high operating voltage requires high
resistivity - low doping concentration. But there is a price to be paid: the
depletion regions become wide.

Let's use the integrated NPN transistor as an example. There are

two depletion regions, one extending into the epitaxial layer from the base
(downward and side-ways), the other into the epitaxial layer from the
isolation. To make sure the first one does not reach the substrate (and thus
cause premature
breakdown or punch-
through), the epitaxial
layer must be deep -
which means that the
isolation diffusion must
be deep, and thus wide.
Fig. 1-15: At higher operating voltage the depletion Look at the left
regions around the NPN transistor become larger. side of the transistor.
The spacing between the
isolation (as drawn) and the base must accommodate the following:
the side-ways diffusion of the isolation,
the isolation-collector depletion region,
a safety margin for possible misalignment,
the collector-base depletion region and
the side-ways diffusion of the base.
In addition there is also a high-voltage depletion layer each between the
base and the sinker and the sinker and the isolation, as well as a deeper (and
thus wider) sinker. All this adds up to a painfully large area.
The increase in area can be curbed somewhat by two measures: 1.
Use an additional diffusion for the isolation by creating a P+ region directly
underneath the normal one before growing the epitaxial. The two halves
will then diffuse toward each other (up-down diffusion) and meet in the
middle, thus requiring only half the depth and width; 2. Add more
processing steps, creating both low-voltage and high-voltage devices on the
same wafer.
The Miller Capacitance. As we have seen above, the bipolar
transistor is a very non-linear (exponential) voltage amplifier and cannot
thus normally be used as one. But it has a voltage gain, and a high one at
that (several hundred is not uncommon).
There is an unavoidable junction capacitance between the collector
and the base. If you feed a current with an ac signal into the base, the
voltage change on the collector will be much larger than that on the base.
Thus, looking into the base, the junction capacitance appears multiplied by
the voltage gain (the Miller effect). Instead of a tiny fraction of a pico-
Farad you have to deal with 10 or even 100pF. If the base is fed from a
high impedance (e.g. a current source), the frequency response is then

nowhere near the advertised ft (cutoff frequency).

This Miller effect can be reduced by circuit design techniques (e.g. a
Cascode Stage), but even so most circuits cannot operate much above say
1/20 of ft. (ft is the frequency at which the current gain drops to 1).
On the other hand, there is also a benefit. In feedback amplifiers
you almost always need a compensation capacitor (more of this later).
Using the Miller effect you can get away with a 5pF capacitor, which
appears to be as large as 1nF, a value which would be much too large to be
integrated.
The Case of the Lateral PNP Transistor

It is the world's worst transistor, you couldn't sell it as a discrete
component: low cutoff frequency, very limited current range and an
inferior noise figure. But no self-respecting analog IC designer would want
to be without it. The reason: In either a CMOS or bipolar process no
additional diffusions are required.
The emitter and collector are
formed by the base diffusion (in a
bipolar process) or the p-channel
source/drain diffusion (in a CMOS
process). The current thus flows
radially (or laterally) along the surface
from the emitter to the collector.
The doping levels are all
wrong. For optimum performance you
would want the emitter to have a very
high concentration, the base somewhat
lower and the collector quite low (to
accommodate the higher collector
voltage). Here the emitter and
collector doping levels are equal, and
Fig. 1-16: The lateral PNP transistor.
the base is much higher. Thus, to
allow space for the depletion regions,
the base width (the distance between the collector and emitter, minus the
side-ways diffusions) needs to be quite large. Hence the slow speed (it
takes time for the carriers to travel across the base). Figure on an ft in the
neighborhood of 30MHz with an operating voltage of 15 Volts; at lower
voltages the base-width can be narrower which increases ft but also makes
the Early effect more pronounced.

Despite of all of this, with good surface control you can get a gain
in excess of 100. But the current range is limited, rarely exceeding 100uA
for a minimum geometry device.
And there is somewhat of a problem with substrate current. There is
a competing PNP transistor, using the same emitter and base, but with the
substrate (and the isolation diffusion) as the collector. In normal operation
a current about half the magnitude of the base current flows from the
emitter to the substrate terminal. When the lateral PNP transistor saturates,
the substrate current becomes almost equal to the collector current. If you
don't have a buried layer, it gets quite a bit
worse.
One advantage of the lateral PNP
transistor: the collector can be split into two
(or more) sections. The emitter current,
flowing radially outward is collected by the
segments according to their length at the
inside. There is a small loss in gain because
of the gaps, but the matching between the two
collector currents is excellent.
In a CMOS process emitter and
collector are usually formed by the p-type
diffusion of a p-channel MOS transistor. The
intervening space (the base-width) is the same
as a p-channel gate, with poly-silicon on top.
Connect the poly region to the PNP emitter; it Fig. 1-17: A split-collector
will act as a static shield and have a (slight) lateral PNP transistor.
beneficial effect.
CMOS Transistors
It took almost 20 years after the invention of the bipolar transistor
for MOS to make its appearance. Shockley (and many others) had thought
of this device first, it was (or should have been) much more simple: put a
plate close to the surface of silicon, connect it to a voltage and move the
carriers inside the silicon electro-statically.
The problem was the surface of silicon. Here the silicon atoms are
no longer neatly tied up with each other by sharing the outermost electrons.
They face an entirely different material, SiO2 (or worse, some covering
with unknown impurities mixed in). This material doesn't even have a
crystal structure, it is amorphous.

In 1964 a startup, General Microelectronics, felt it had licked the

problem with CMOS and brought out the first digital MOS integrated
circuit. It was one of the worst products ever to hit the market: a large
portion stopped working within days. The reason: there were elements with
the silicon-dioxide (chiefly sodium) that carried an electric charge and could
move. One day the MOS transistor was perfectly functional, the next day it
was permanently turned on.
It took another few years to gain an understanding of MOS surface
physics and make stable MOS transistors. Today the silicon surface is so
well understood that we can deliberately place a charge into the oxide layer
that stays there for years, probably even centuries. It is now the dominant
integrated device, being much smaller than the bipolar transistor. (The
number of MOS transistors produced every year has long surpassed the
number of ants in the world. At the time of writing this book,
semiconductor manufacturers produced some 500 million transistors for
every person in the world per year).
The figure
shows a cross-section
of the most often
used (n-well) process.
There are many
variations and
refinements; this is
only the basic one.
In the gate
Fig. 1-18: Cross-section of an N-well CMOS process. area the insulating
layer (SiO2 or nitride,
or a combination) is
thinned down and silicon is grown on top of it. Since the insulator is
amorphous, the grown silicon is not single-crystal, it consists of many small
crystals which do not fit together very well (thus it is called poly-crystalline
silicon or simply poly).
Next the source and drain regions are implanted, using a mask. The
inside edges are masked by the gate, so they align perfectly to the gate (i.e.
they are self-aligning). The device is also self-insulating: as long as the
source and drain are at or above the substrate potential (usually ground), the
junctions to the substrate are reverse-biased and no bulky isolation diffusion
is necessary.
For the p-channel transistor the polarities for the source and drain
implants are reversed and these regions are placed inside an n-type
diffusion. In most applications one such n-well hosts many p-channel

transistors and is simply connected to the positive supply voltage; in this

way the devices are insulated from each other as long as each source and
drain is at or below the positive supply.
In both the n-channel and p-channel transistors, sources and drains
are identical, i.e. you can arbitrarily call one the source and the other the
drain. Or one region can do double-duty, being the drain for one transistor
and the source for the next one, connected in series.
The p-channel transistor is always at a disadvantage, because holes
are more difficult to move than electrons. Thus it will have a lower gain
than an n-channel device (for the same gate oxide thickness) and be
somewhat slower. (MOS
transistors, by the way,
are called unipolar
devices, because they
employ only one type of
carrier, as opposed by the
bipolar transistor, in
which both electrons and
holes are important for
the operation).
Now let's look at
an (n-channel) MOS
transistor in more detail.
The basic idea is to create
a region (a channel)
between source and drain
which has the same Fig. 1-19: As the drain voltage is increased, a
polarity (n-type), so that depletion region pinches off the channel.
40
there is direct conduction between
35
the two. This is done with a positive
30
voltage at the gate which pushes
holes away from the surface and the
Drain Current / µA
25
20
device is called an enhancement-
15
mode transistor (there are also
10
depletion-mode devices in which a
5
channel is implanted or diffused and
00
then cut off with a negative gate
0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8
voltage).
Drain Voltage/V 200mV/div
This is true only at zero or
Fig. 1-20: Drain current vs. drain voltage very low drain voltage. As the drain
with the gate voltage held constant. voltage is increased, a depletion

region forms around it. Since there is now a voltage drop along the
channel, with the drain side at a higher voltage than the source, the
depletion region along the channel gradually increases toward the drain,
cutting more and more into the channel. Thus the resistance of the channel
increases.
The initial slope of the
drain voltage / drain current 200
curve is the resistance of the 180
channel without any depletion 160
layers. The final slope at the 140
Drain Current / µA
120
highest drain voltage represents
100
its resistance with the depletion
80
layer almost pinching off the 60
channel. It is an unfortunate 40
fact that this region is called 20
the "saturation region", which 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8
clashes badly with the earlier Gate Voltage/V 200mV/div
definition for the bipolar
transistor. Fig. 1-21: Drain current vs. gate voltage
with the drain voltage held constant.
Above a certain gate
potential, which has to be exceeded
to attract any carriers to the surface (the threshold voltage) an MOS
transistor is basically a square-law device: doubling the gate voltage results
in four times the drain current. The measure of gain is the
transconductance, drain current divided by gate voltage. So again, like the
bipolar transistor, this is a non-linear device:
Id = k
W
L
(Vgs − VT )
2
where Id = drain current

k = transconductance
W = channel width
L = channel length
Vgs = gate-to-source voltage
VT = threshold voltage
or Vgs - VT = gate voltage above the threshold
The region below the channel also influences the gain. It forms a
back-gate. In an n-well n-channel transistor this is the substrate, common
to all devices. You have no choice but to connect it to the lowest negative

voltage. But there is a choice for the p-channel transistor. If you place all
the p-channel transistors in a common n-well, you get the smallest total area
and therefore the lowest cost. But if the source of such a transistor is
operated below the positive supply, the back-gate (the n-well) pinches off
the channel further and you get a reduced gain (by perhaps 30%). You can
avoid this by placing this transistor in its own n-well.
The Substrate PNP Transistor

In either a bipolar or CMOS process there exist layers which can
form a PNP transistor with the substrate as the collector. Since the collector
is permanently connected to the most negative supply voltage, such a device
has limited use. In a bipolar process a lateral PNP transistor has greater
flexibility and better performance and is thus almost always preferred.
In a CMOS process the same is true, but because of historical
reasons or limited information the substrate transistor is still present. The p-
type implant for the p-channel transistor forms the emitter, the n-well the
base and the substrate the collector. The n-well has a large depth, thus the
PNP base-width is large and the gain rather small (e.g. 10).
Diodes
There are several p-n junctions in an integrated circuit, each and
every one a diode. But few of them can actually be used by themselves
without unpleasant side-effects.
Take a simple bipolar process. There are three types of junctions:
emitter/base, base/collector and collector/substrate
P (all referring to the NPN transistor). The last one is
hardly ever useful because the substrate is
permanently connected to the most negative supply
voltage. The base/collector diode is, as we have
seen, part of a substrate PNP transistor with a gain; a
N current perhaps ten times the magnitude of the diode
Fig. 1-22: Properly current will flow to the substrate.
connected diodes in The emitter/base junction makes a good
a bipolar process.
diode, but it has a low breakdown voltage (about 6
Volts) and the base has a fairly high resistance. You

could connect the surrounding collector to the most negative supply voltage
and thus keep it always reverse-biased. But a much better diode results if
you short collector and base together, creating a diode-connected
transistor. The transistor is active, it has gain. Only a small fraction of the
current flows through the base, which divides the base resistance by the
current gain. This connection in fact gives you an almost ideal diode over
about five decades of current.
If the emitter/base breakdown voltage is too low, consider a diode-
connected lateral PNP transistor. This devices has the full operating voltage
of the process, but it is limited in current (see above).
In a CMOS process the restrictions are even more severe. The only
free-floating junction is between the p-channel source/drain and the n-well.
But, as we have seen, these are also part of the substrate PNP transistor.
Were you to run a current through this junction, a current of about ten times
its magnitude would flow to the substrate.
The term "diode-connected" is often used for an MOS transistor
with its gate and drain connected together. Don't be misled by this term:
there is no diode as in "junction" diode.
Zener Diodes
In a bipolar process the base-emitter diode almost always has a low
breakdown voltage (perhaps 6 Volts) with a fairly low temperature
coefficient, which makes it useful as a reference voltage.
But exercise care with this device: the same junction is also used as
a fusible device.
At low current (e.g. less than 100uA for a minimum-geometry
device) the Zener diode behaves well. As you increase the current the
region between the emitter contact and the edge of the emitter diffusion
lights up faintly (a plasma, which you can observe under a microscope, with
all lights turned off). At some high current level a thin aluminum strip is
formed abruptly underneath the oxide, which converts the Zener diode into
a short-circuit. This effect is used for trimming and carries the earthy name
Zener-zapping.
Such a Zener diode is also somewhat noisy. For lower noise (and
better accuracy) use a bandgap reference.
Moving an n-channel and p-channel source/drain diffusion in a
CMOS process close together so that they intersect can also result in a
useful low breakdown voltage, but data for such a device are rarely
available from the wafer-fab.

There are also buried Zener diodes, devices with a special

diffusion below the surface of the wafer. Such devices have lower noise,
but the addition to the process tends to be costly.
Resistors
Every free-floating layer in an integrated circuit can, when properly
patterned, become a resistor. But for all of them this is only a secondary
duty; their intended application is in a transistor, which is the hardest device
to make. It shouldn't come as a surprise then that their values have a higher
variation and greater temperature coefficient and their range is more
restricted than that of even the least expensive discrete resistor.
Discrete resistors can be tested and adjusted during manufacturing.
In ICs the manufacturing is done while the silicon is red-hot, at which
temperature it is no longer a semiconductor; you have to wait until it cools
down to measure any parameter.
What saves the integrated resistor is its natural ability to match well.
Whatever error may have occurred in making one applies to any other on
the same wafer. They may both be as much as 25% high in value, but both
will be high by (almost) exactly the same amount.
The resistance of any material is given by
rho ⋅ l
R=
A
where rho (ρ) = resistivity in Ohm-cm
l = length
A = area (cross-section)
If we make a square, i.e. w = l, then we get a measure of resistance
which is independent of size, the sheet resistance, in Ohms per square (or
Ohms/o).
Note the term is sheet resistance, not sheet resistivity. A square in a
layer with a sheet resistance of 100 Ohms per square always measures 100
Ohms from one side to the other no matter how large the square.
In a bipolar process the layer most often used for resistors is the
(NPN) base (about 200 Ohms/¨). The emitter layer is more heavily doped
and thus has a lower sheet resistance (as low as 5 Ohms/¨).
In a CMOS process you have a wider choice: the n+ and p+
diffusions (implants) for the drains and sources, the n-well and usually two
different poly layers. Of these the p+ diffusion (about 150 Ohms/¨) and
one of the poly layers (around 50 Ohms/¨) are generally best suited.
Sheet resistances depend greatly on the process; you should use the

values given here only as a starting point and get the actual data (including
temperature coefficients and tolerances) from the wafer fab.
Diffused resistors must be placed in an island of opposite doping
and this island must be connected to a bias voltage so that the junction is
reverse-biased. For example, a (p-type) base resistor must be in an n-type
(epi) island. This island (sometimes called the "tub") can contain just one
resistor or all of them, but its voltage must be at a level equal to or greater
than the largest voltage on any resistor. In this case the easiest and safest
connection is to +V.
Diffused resistors (and to a lesser degree, poly resistors) have a
voltage coefficient. The biased surrounding layer pushes a depletion region
into the resistor, reducing its cross-section. As the difference in voltage
between the resistor and the surrounding layer becomes larger, the depletion
region widens, the cross-section becomes smaller and the resistance
increases. This effect is especially pronounced in lightly doped layers: the
n-well in CMOS and implanted resistors in a bipolar process. (The latter
uses an additional implant to create a high sheet resistance).
This voltage dependence is especially critical if you have two (or
more) resistors which need to match but are at different DC levels. You can
place each resistor in a separate island, biased at the positive end of its
resistor. Or you can simply accept the change caused by the depletion layer
and adjust the ratio. For this, however, you need a model for the resistor
which includes its voltage dependence. (in a 200 Ohms/¨ base layer, for
example, the change in resistance is about 1% for a 5V bias difference).
There is also a (distributed) capacitance associated with an
integrated resistor, low for poly, higher (and voltage dependent) for diffused
ones. If you make a high-value (i.e. very long) resistor, this stray
capacitance can seriously cut frequency response. Also, if there is noise on
the supply which biases the surrounding region for diffused resistors, it will
be capacitively coupled into the resistor. Again, a
good model is required to show these effects in a
simulation.
Two correction factors have to be used when
designing a resistor. The first concerns the width of
the resistor. In diffused (or implanted) resistors there
is always a sideways diffusion, which makes the
actual resistor wider than drawn. The effect of the
side-ways diffusion is dependent on the width of the
resistor.
The second correction factor recognizes the Fig. 1-23:
end-effect. If the resistor has minimum width, you Resistor contacts.

will need to enlarge both ends to place a contact inside. You will then need
to estimate the resistance of this additional area and of the contact itself
(totaling perhaps 0.4 squares from the end of the narrow part).
If you draw a wide resistor, the contacts can be fitted inside the
resistor, but they will not cover the entire width, even if converted to one
long contact. There is, therefore a small additional resistance (about 0.2
squares from the inside edge of the contacts).
The matching of resistors depends entirely on the width. Sub-
micron processes are not developed to get good matching, just maximum
speed. You will find that minimum-dimension devices (all devices, not just
resistors) match very poorly. When greatly magnified under a microscope
all edges appear somewhat ragged. The width of a resistor, for example,
fluctuates considerably. It is only when you make a relatively large device
that these fluctuations become insignificant and thus devices match well.
Figure on using something like ten times the minimum width for matching
of 0.5% or better.
Because of the end-effect you cannot expect resistors of different
lengths to match well. For optimum matching use only identical resistors.
It also helps divide resistors into identical sections and intermingle them
with other resistors (in the same identical sections) which are intended to
match.
One more thing about IC resistors: the Seebeck effect. Discovered
in 1821 by Thomas Seebeck (and used by Ohm four years later for his
measurements of resistance), it is the thermocouple effect: metallic
interfaces at the ends of a wire produce a voltage if the ends are at different
temperatures. For the contacts of a diffused or poly resistors this voltage is
between 0.2mV/oC and 1.4mV/oC, depending on the doping level and
composition of the metal. This is a danger if thermal gradients are present,
e.g. with a power transistor on the chip. To avoid it, lay the resistor out so
that beginning and end are close together.
Pinch resistors (or pinched
resistors) are sometimes used in bipolar
processes to get a high resistance without
wasting a lot of area. The base-pinch
resistor is simply a base resistor with the
emitter diffusion placed over part of it.
This reduces the effective cross-section
(only the deepest part of the base diffusion
is left, which has also the highest
Fig. 1-24: Top view and cross- resistance). The device needs to be in its
section of base-pinch resistor. own epi island, with the epi (and emitter

diffusion) connected to the positive terminal. A base-pinch resistor is non

linear, has a low (e.g. 6-Volts) breakdown and a large variation (about
10:1), but you can cram 100k Ohm of resistance into the space of a
transistor.
The second device is the epi-
pinch resistor. The cross-section of
a long and narrow epi region is
further reduced by moving the
isolation diffusions on either side
very close together. Since the epi
region usually is of fairly high
resistivity, a substantial depletion
region extends into the remaining
Fig. 10-25: Bulk or Epi-Pinch Resistor. epi region, pinching it off at an
operating voltage (above the
substrate potential) in excess of about 5 Volts. Thus, at any voltage higher
than that, the epi-pinch resistor becomes a current source. The variation of
this current is high (8:1), but you can create a small current (a few micro-
amperes) in relatively little space.
Capacitors
The oxide insulating the metal interconnection from the silicon (or
between metal layers) is dimensioned to give minimum stray capacitance.
Even a small capacitor (say 5pF) would take up an enormous amount of
space. Enormous at least in microelectronic dimensions.
Thus fabricators often provide an additional mask step to outline an
area where the oxide (or nitride) is thinned down considerably, producing a
higher capacitance (about 2fF/um2 - that's femto-Farads, or 10-15F/um2).
With this figure (which of course varies from process to process) a
50x50um area gives you all of 5pF, easily be the most expensive component
in your chip. If you specify anything greater than 100pF, your colleagues
may think you have a degree in macroeconomics.
One plate of the capacitor is always either metal or poly. For the
second plate you could use a diffusion, but that creates a slight voltage
dependence (there is always a depletion layer in silicon which widens as the
voltage increases, adding to the distance between the plates). Poly or metal
for the second plate are better choices.
The oxide underneath an MOS gate is already thinned down to
achieve a reasonable transconductance, so it too has a higher capacitance

per unit area than the ordinary (field) oxide. But be careful here. At zero
(DC) voltage there is no channel (source and drain form the lower plate, the
gate the upper one), so the only capacitance is the one from the gate to the
overlapping parts of drain and source. When the voltage exceeds the
threshold, the channel comes into existence and the capacitance increases
markedly. Figure 1-26 shown here depicts the behavior of a large
6
(10x20um) 3V n-channel
device.
5
MOS Gate Capacitance There is also junction
vs Gate Voltage
capacitance, which you should
Capacitance / µuF
not dismiss lightly. The

3
capacitance of a collector-base
2 junction per unit area competes
1
quite well with that of an oxide
capacitor, but is voltage
00 0.5 1 1.5 2 2.5 3
dependent (though not as much
V1/V 500mV /div as the MOS gate capacitance)
Fig: 1-26: The gate capacitance of an MOS and the stray capacitance for
transistor is greatly dependent on voltage. one plate (collector to
substrate) is higher. An even
higher capacitance per unit area is offered by the base-emitter junction,
though its breakdown is limited (about 6 Volts). The advantage of the
junction capacitor is the elimination of the additional mask step.
Other Processes
What we have considered so far are two simple, basic processes,
requiring as few as 8 masks. There are many variations, all based on these
two:
- "Mixed Mode" CMOS, with devices for (somewhat) higher
operating voltages and additional poly (and metal) layers;
- BICMOS processes which add full-fledged bipolar transistors to
CMOS;
- Bipolar processes with vertical (high-speed) PNP transistors;
- CMOS processes with some high-voltage devices (500V).
All of these variations have one factor in common: they increase the
number of masks (and processing steps) required and are thus more
expensive. However, they tend to make the design of high-performance
analog circuits easier, especially when both CMOS and bipolar transistors
are available.

CMOS vs. Bipolar

The debate as to which is better for analog design is as old as the
devices themselves. Let's examine some of the main points:
! The bipolar transistor requires an input (base) current, the CMOS
devices does not. This is strictly true only at DC; at higher frequencies
there is the input capacitance, which does result in a current. Also, some
analog designs (see chapter 8) manage to bring this current down to a very
low level.
! Bipolar transistors have lower offset voltages. Generally true, but
offset voltage depends on size. Make a CMOS transistor larger than a
bipolar one (or use trimming) to achieve equally low offset voltage.
! Bipolar transistors have lower noise. Again generally true,
especially at low frequency (1/f noise, see chapter 6). One exception: the
auto-zero (or chopper stabilized input, see chapter 8).
! CMOS devices have smaller dimensions. Generally not true. To
get the required performance in an analog design (matching, gain, low
noise), CMOS transistors need to be much larger than the minimum
dimensions of the process would allow. At reasonably high supply voltages
(3 Volts and above) CMOS and bipolar devices end up about equal in size.
! Bipolar transistors are better for low-voltage design. True.
Transconductance in a CMOS device increases as the square of the gate
voltage above the threshold. If the gate voltage can only go, say, 0.5 Volts
above the threshold, it takes a painfully large gate-width to get a substantial
drain current. In the bipolar transistor a ten-fold increase in collector
current is obtained with only a 60mV (at room temperature) increase in base
voltage. It is ironic that CMOS is marching toward lower and lower
voltages, where it is at a serious disadvantage.

Camenzind: Designing Analog Chips Chapter 2: Simulation
2 Simulation
In 1972 the Electrical Engineering Department of the University of

California at Berkeley released the first version of SPICE (Simulation
Program with Integrated Circuit Emphasis). Donald Pederson, the head of
the department decided to do this free of charge; after many additions,
revisions and improvements (done by a “cast of thousands” of graduate
students) it is still free today.
The Berkeley SPICE program (originally written in Fortran) has
been modified and sold by dozens of companies under various names.
Some of the modifications were useful (such as the adaptation to PC use),
many others merely served to make these programs incompatible with each
other.
So, be aware that there are differences in capabilities and notation
between Spice programs. Also, it is no longer true that such analysis
programs running on more expensive workstations under Unix are better or
faster; some PC programs (notably Simetrix) have outdistanced their Unix
cousins in both speed and added features.
Simulation for analog ICs differs greatly from any kind of digital
simulation. The most important factor in the latter is speed. This has led to
an ever finer representation of internal capacitances and other stray-effects
in the models used. In an analog IC, speed is just one of many
requirements. We rely heavily on matching, and need to know the effect of
the variations of many parameters in an almost unlimited number of
combinations with great certainty. Each device also needs to be represented
accurately over the entire operating range, not just in two states. The
models, therefore, become the most important factor.
Unfortunately, the quality of models for analog or mixed-mode ICs
varies greatly. Some - few - are very accurate and from simulations alone
you can tell with great certainty how well your design will work in silicon,
down to the exact distribution of each circuit parameter in production. But
most models issued by foundries are not in this category, lacking
information crucial to analog design.
In the second half of this chapter there is a fairly detailed discussion
of device models for Spice. This is a somewhat tedious task, but necessary

to judge the quality of the models available to you. Read this part lightly
and then use it for later reference.
What Can You Simulate?

A good analog simulator can tell you all you need to know about a
design. But be aware that simulators which fall into the average category -
including the most popular one - lack several of the most desirable features.
In Spice there are three basic simulations:
DC Analysis
Let's use a simple example, a Q3

buffer, a very simple circuit with a Q4
voltage gain of one. Two NPN Vcc
transistors (Q1, Q2) form a differential Q1 Q2 Out
5V
stage, Q3 is a current mirror and Q4 an
emitter follower (more about this in Vin 40k 10k
the next two chapters). For the current R1 R2 SUB
mirror we use a lateral PNP transistor

with a split collector (see chapter 1).
Fig. 2-1: A simple example for
In the first DC analysis we simulation, a bipolar buffer.
continuously change (sweep) Vin from
zero to 5 Volts and observe the
4
output. The simulator tells us that
3.5
the output follows the input, but
3
only above about 0.6 Volts and
below 4.1 Volts (the common-
Output Voltage / V
2.5
2
mode range).
1.5
You could enhance this
analysis by repeating it at various
1
temperatures, i.e. by automatically
0.5
"stepping" the temperature, either
0 1 2 3 4
at regular intervals or at three or
Input Voltage/V 1V/div
four points. While you do all this
you can measure the input current
Fig. 2-2: A DC analysis, showing the
common-mode range. (either at the base of Q1 or at
either terminal of Vin), the current

consumption (at one of the terminals of Vcc), the substrate current (out of
the symbol SUB) and even the power dissipation of the entire circuit or any
component.
Place a current source from Out to ground and you can determine
how well the circuit handles a load, i.e. determine the output impedance.
There are two sub-categories in a DC Analysis. The Transfer
Function gives you the relationship between two nodes (not used very
often) and the Sensitivity Analysis tells you which parameters (including
transistor parameters) are most responsible for a change in a particular
voltage or current at any node.
AC Analysis
The one thing you never want to forget about a Spice AC analysis is
this: The signal is treated as if it were insignificantly small. You may
specify a 1-Volt input signal (most people do, it represents zero dB and is
thus very convenient), but the analysis program will process it without
disturbing any of the bias levels. If you have a high gain, say 60dB, the
output plot will show a voltage of 1000 Volts without even blushing. What
it is intended to show you is the gain relative to the input; the actual values
taken out of context are often absurd.
Our plot shows the
0
output response of our buffer in
-1
the most simple AC analysis: a
-2
1-Volt ac signal at the input on
-3 top of a DC Voltage of 2V, with
Gain / dB
-4 the frequency swept from

-5 200kHz to 200MHz. The output
-6 is in dB relative to the input, so
-7 0dB is a "gain" of 1, -3dB is a
-8 "gain" of 0.708 (or a loss of
200k 400k 1M 2M 4M 10M 20M 40M 100M200M 29.2%).
Frequency / Hertz We could also move the
Fig. 2-3: AC analysis: gain (in dB) vs. AC source into the Vcc supply
frequency. (make sure there is only one AC
source per circuit). If we do this
we can measure how much of a supply's ripple gets into the output, i.e.
power supply rejection.

With equal ease you can measure the AC response of an output

current relative to an input current. But when it comes to the relationship
between a voltage and a current a measurement in dB makes little sense.
Spice also lets you measure the phase of any voltage or current
(relative to the phase of an input signal). This is of particular interest in
circuits which employ feedback, but more of this in chapters 6 and 8.
Remember though, this is a small-signal analysis, done at one
particular bias point. The AC response (particularly the phase) may be
different as a real-life signal moves operating voltages and currents.
An adjunct to AC
100n
Analysis is the Noise Analysis.
Here the AC source is turned off 40n
and the combined effect of all
Output Noise / V/rtHz
noise sources inside the circuit 20n
(resistors, currents) at the output 10n
is displayed. The measure is

nanovolts (or microvolts) per 4n
root-Hertz. Despite the awkward 2n

name, it is in fact an elegant
measure. To get the actual noise 10 100 1k 10k 100k 1M
(usually in uVrms) you simply Frequency / Hertz
multiply the value taken from the

curve by the square-root of the Fig. 2-4: Output noise vs. frequency.
frequency interval of interest. For
example, between 100Hz and 1kHz we read an average of about 12nV/rtHz.
Multiply this by the square root of 900 and you get 360nVrms of noise, if
you look at it with filter which cuts out everything below 100Hz and above
1kHz. Similarly, in the flat (white noise) region between 10kHz and 1MHz
we would measure about 24uVrms; even though the curve has a lower
value, the total noise is much larger because of the wider frequency range.
Transient Analysis
Here we convert Vin to a pulse source (instead of DC or AC) and

look at the output not over a voltage or frequency range, but time. You may
have to make a few trial runs to get the appropriate pulse-width and total
analysis time. At first the program will choose its own time steps,
shortening the intervals when a lot of changes happen and lengthening them
when no changes are taking place. But, if you are not satisfied with the
resolution, you can dictate what maximum (or minimum) time-step it is
allowed to take.

3.4
2.9
3.2
2.8
3
2.7
Output Voltage / V
2.8
Output Voltage / V
2.6
2.6
2.5
2.4
2.4
2.2
2.3
2
2.2
1.8
2.1
1.6
0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2
0 20 40 60 80 100 120 140 160 180 200
Time/mSecs 200µSecs/div
Time/nSecs 20nSecs/div
Fig. 2-5: Transient analysis 1: a 1-Volt Fig. 2-6: Transient analysis 2: a 1Vpp
pulse at the input. sine-wave at the input.
Change the input to a sine-wave and you will learn a great deal more
about the circuit. It will be immediately obvious if the circuit can reproduce
the waveform without clipping it at either the high or low excursions. But
that is only a rough impression of fidelity. What you need to know is the
amount of distortion in the waveform.
In some programs you simply display the sine-wave, click on
distortion and get the result. But if you want to have the entire information,
nothing beats a Fourier Analysis.
The Fast Fourier Transform (FFT) is a routine which extracts the
frequency components from a waveform. It is rather tricky to use and
sometimes produces errors. Shown here is the result of a continuous
Fourier analysis (Simetrix),
which is both more detailed 1
and more reliable. 100m
What we see in the 10m
graph is amplitude versus 1m

Spectrum(Out) / V
frequency. At 1kHz there is 100µ

the fundamental frequency with 10µ
an amplitude of nearly (but not 1µ
quite) 1 Volt. At 2kHz is the 100n
second harmonic with an 10n
amplitude of 100uV, or 0.01%.
0.5 1 1.5 2 2.5 3
The third harmonic measures
Frequency/kHertz 500Hertz/div
about 12uV, or 0.0012%.
To get this kind of resolution you need to run the sine-wave for
many cycles (at least 1000) with Fig. 2-7: Fourier analysis.
small enough time steps.

Noise analysis in the small-signal (AC) mode has strict limitations.

It presumes that the operating voltages and currents are steady. This is fine
for a circuit which is perfectly linear, but it falls down if a design is non-
linear, either by design or by mishap. Take, for example, the case of a
mixer (or modulator). A signal of a particular frequency enters a
deliberately non-linear block, such as a diode mixer or the phase-detector of
a phase-locked loop. The non-linearity creates other frequencies (usually
much lower ones, such as frequency differences), one of which we use and
amplify. An AC noise analysis is useless here, because it cannot follow
what happens to the noise as it is transformed by the mixer.
What we need in such a case is a transient analysis program which
pays attention to noise sources. Few have this capability; a notable
exception (again) is Simetrix.
The Big Question of Variations

As pointed out in chapter 1, device parameters in an IC vary from
run to run and from wafer to wafer. The devices are made at temperatures
at which the material is no longer a semi-conductor. You have to wait for
the wafer to cool down to measure the parameters of a diffusion.
Fig. 2-8: The normal or Gaussian distribution.
Most parameters follow a "normal" (Gaussian) distribution. There is

a mean value, at which the number of occurrences is maximum. A
deviation of ±s (sigma) from this point contains 68.3% of all measured

values. If you allow the deviation to be three times as large (±3s ) you
enclose 99.73% of all measurements.
This sounds like you are discarding only 0.27% of all values, but the
figure is deceiving. So far we have considered one parameter only, but
there are many in an integrated circuit. Suppose your design is influenced
by 50 of them. The total parameter "yield" then is .997350, or 87.4%. In
other words, you would discard 12.6% of all chips on a wafer.
Unless you simply don't care about cost, you need to design an
analog IC so no chips are lost because of parameter variations, i.e. the
design can withstand a variation of each and every device parameter to at
least 3σ; 4σ would be better.
But how do you find out how much parameter variation your design
can take? The answer is Monte Carlo analysis, and only Monte Carlo
analysis.
There is in use what is called a "four-corner analysis". Device
parameters are bundled together in four groups, representing extremes, or
worst cases. The plain fact is this: it doesn't work for analog circuits. The
four-corner models are just barely able to predict the fastest or slowest
speed of digital ICs, but the grouping simply doesn't apply to analog ones.
In fact, no grouping is possible; a parameter's influence differs from design
to design. Analog designers who are satisfied with a four-corner analysis
simply fool themselves into believing that they have a handle on variations,
when in truth the result is quite meaningless.
A true Monte Carlo analysis varies the device parameters in a
random fashion, so that every combination of variations is covered. This is
also what you get in production.
You don't need to vary every parameter of a device, only the major
ones. For example, varying IS, BF and the capacitances in a bipolar
transistor model is sufficient; the same is true for the threshold voltage, the
transconductance and the capacitances in MOS transistors. If matching is
expected, there must be two additional entries, one for the absolute
variation, and one for the variation between devices on the same chip.
These "tolerances" are either inserted into the model file directly or
contained in a separate file, depending on the analysis program used. The
Monte Carlo program then simply runs the chosen analysis repeatedly, each
time with a different set of variations, randomly chosen. Our example
shows the variation over temperature for a bandgap reference (untrimmed).
How many runs need to be specified for a Monte Carlo analysis?
There is an easy way to find out. Start with 20. Then increase this number
until the extremes no longer change. For this analysis 50 runs were used,

which is more than needed. But with today's fast computers you can afford
to go overboard: the analysis took all of 8 seconds!
This one picture gives
you the variation of a 1.27
reference voltage over 1.26
temperature, exactly as it will

1.25
happen in production. You
notice a Gaussian distribution 1.24
(more curves at the center,
Vref / V
1.23
fewer at the extremes). 1.22
Between the top and bottom

1.21
curves lie 99.73% (3-sigma)
of all circuits. 1.2
Without the Monte 1.19
Carlo analysis we would not -40 -20 0 20 40 60 80 100 120
Temperature/Centigrade 20Centigrade/div
know how much variation to
expect until several wafers Fig. 2-9: The result of a Monte Carlo analysis.
Each curve represents the behavior of one circuit
from several different lots (among 50) in production.
have been tested (a single
prototype wafer cannot tell you what the variations in production will be).
Models
The Diode Model
As we have seen in chapter 1, there isn’t any one junction in an IC

which can be used directly as a diode; a “diode-connected” transistor does
this job with greater accuracy and far fewer side-effects.
However, a bipolar transistor consists of junctions,
at least two of them. Thus a model for a junction diode is a
fundamental element in models, even in CMOS. In the RS
model file (which is always in ASCII) you might see the

following: CJO I1
.MODEL Diode1 D IS=1E-17 RS=20 CJO=0.85E-12
Fig. 2-10: a simple

A model statement always starts with a dot. "Diode1" diode equivalent
is the name of the device (which can be anything) and circuit.

D says the device is a diode. The remaining entries are in Amperes, Ohms
and Farads.
This is about as simple a diode model as you can possibly make it;
just three parameters are specified. IS, together with the series resistance
RS, determine the DC characteristics, CJO the junction capacitance. Let's
first look at the DC behavior.
As we have seen in chapter 1, the current/voltage relationship of an
ideal junction is given by:
Vd⋅q
I1 = Is e k⋅T
where Is = the diffusion current
Vd = the voltage across the current source (i.e. not including RS)
q = the electron charge
k = the Boltzmann constant
T = the temperature in Kelvin
In Spice this diode equation is greatly expanded:
 Vd⋅q  ( ∆T −1)⋅ NEG⋅k⋅⋅qT XTI  Vd⋅q    Vd  2 M


I1 = IS  e N⋅k⋅T  ⋅ e ⋅ ∆T + ISR  e NR ⋅k⋅T  ⋅  1 −  + 0 . 005 2 
 
  N     VJ  
At first this equation might appear utterly complicated, but it isn’t.

If you look at the first portion (to the left of the + sign), you see three
multiplied constants:
N = the Forward Emission Coefficient (1)
EG = the energy gap, which depends on the material (1.11 for
silicon); you set this to 0.69 for a Schottky diode, 0.67 for
germanium and 1.43 for Gallium-arsenide.
XTI = the temperature coefficient of IS (3).
∆T = the quotient of operating (i.e. junction) temperature to room
temperature (usually 300K or about 27oC).
With these three constant you can shape the basic exponential curve
to what is actually measured. If you don't list them in the model statement,
they assume the values shown in parentheses.
The portion of the equation to the right of the + sign adds a leakage
current, i.e. a small current in excess of the (reverse) current predicted by
the ideal diode equation. You can modify the shape of its curve with the
constants NR, M and VJ.
As shown, the model makes the breakdown voltage of the diode
infinite. You can limit this with the parameter BV and three companions:
TBV1 (its first-order temperature coefficient)

TBV2 (second-order temperature coefficient)

IBV (the current at which breakdown is specified)
There is also a parameter, IKF, which splits the DC curve into two
regions. In ICs this is very rarely used.
The series resistance, RS, which also influences the DC behavior,
has first and second-order temperature coefficients, TRS1 and TRS2.
The junction capacitance shown in the model, CJ0 (or CJO) is
measured at zero voltage. Since its value at different voltages (forward or
reverse) depends on the grading of the junction (abrupt, diffused, implanted
etc.), it too is modified by three constants, VJ (1), M (0.5) and FC (0.5). If
you don't list them in the model statement, the default values in parentheses
will be used.
For a voltage across the diode (not including RS) equal to or less
than the product of FC and VJ, the formula is:
C = CJO ⋅ 1− ( )
Vd − M
VJ
If the voltage across the diode is greater then FCxVJ:

⋅ (1 − FC ⋅ (1 + M ) + M ⋅ Vd
VJ )
− (1+ M )
C = CJO ⋅ (1 − FC )
There are two noise sources in a diode: the resistor RS and the
current I1. Without any additional parameters these are treated as white
noise sources, i.e. the noise is the same at any frequency. (For a more
detailed look at noise see chapter 6). Since there is also flicker noise (which
increases at low frequency), two constants, KF and AF are used and the
following expression is added to the current source noise:
KF ⋅ I1 AF
f
The Bipolar Transistor Model
42 parameters are used to represent a bipolar transistor in Spice.

While the number may look a bit daunting, it is actually quite straight-
forward once you are familiar with the Spice diode, and they are placed into
five groups:
Base-Emitter Diode. Here we have the plain diode Spice parameters as

discussed above, but re-named; the abbreviations in parentheses refer to the
ordinary diode parameters: IS (IS), NF (N), ISE (ISR), NE (NR), RE (RS),
EG, XTI, CJE (CJO), VJE (VJ), MJE (M), FC. The series resistance of the
diode is divided into two parts: RE (at the emitter end, with the emitter
current flowing through it) and RB (at the base-contact end). The latter

starts at RB at low current and drops gradually to the value RBM at a

current specified by IRB; this reflects the use of the entire emitter at low
current and only the emitter edge facing the base contact at high current, as
discussed in chapter 1.
Current Gain: The main parameter here is BF (the forward beta, or hFE)
and its temperature coefficient XTB. Without any additional parameter the
current gain would be the same at any collector voltage or current. The
Early effect is represented by VAF (the Early voltage, see chapter 1). The
drop-off at high current is produced by IKF (the current at which hFE starts
to drop) and NK (the steepness of the drop). ISE and NE of the base-
emitter diode are responsible for the drop in hFE at the low-current end;
simply shunting a small amount of base current to the emitter.
Reverse Current Gain: You may be convinced that you will never operate
a transistor with the collector and emitter interchanged, but just in case
provided the parameters BR, NR, VAR, IKR and TR .
Base-Collector Diode: Here again we have the basic diode Spice

parameters, again renamed: ISC (IS), NC (N), RC (RS), XTF (XTI), CJC
(CJO), VJC (VJ), MJC (M) and TF (TT). The last one is the transit time
(now through the base to the collector) which accounts for any delay which
cannot represented by capacitance alone; it is embellished by ITF (which
makes TF dependent on current), VTF (showing dependence of TF on base-
collector voltage) and PTF (an excess phase at a frequency 1/(TFx2π)).
Noise: As in a simple diode, additional low-frequency (flicker) noise is

represented by the parameters KF and AF, but here they work on the
collector current.
The Spice model for an integrated bipolar transistor can have either
three or four terminals. The fourth terminal (of an NPN transistor) is the
substrate and between it and the collector there is a diode, represented by
the five parameters ISS, NS, CJS, VJS and MJS. This is a major flaw in
Spice, for a mere diode here is inadequate. When the transistor saturates, a
substantial portion of the total current flows to the substrate, which this
model simply ignores.
Fortunately Spice also contains a solution to this problem. To
represent an NPN transistor correctly, you need to add a second transistor;
Spice lets you combine the two (or any number of devices) in a subcircuit.

When N1 saturates (i.e. the collector drops below the base

potential), the PNP transistor P1 becomes active and draws base current to
the substrate. This is what happens in real life: there is a stray PNP
transistor, formed by the base (P), the collector (i.e. the epitaxial layer, N)
and the substrate (P). 1 (Collector)
Rather than put the stray
capacitance (and leakage current) between N1
2 (Base) DCS
collector and substrate into the PNP
transistor (which is somewhat
P1
cumbersome) a separate diode DCS is DZ
inserted. DZ, a Zener diode, corrects

another flaw of Spice: there are no
3 (Em itter) 4 (Subs trate)
breakdown voltages in the bipolar
transistor model; for the base-emitter Fig. 2-11: Equivalent circuit for
diode we need this effect, it is sometimes an integrated NPN transistor.
used as a Zener diode. If you also want
to have a collector-emitter breakdown, place an additional Zener diode
between collector (cathode) and base.
The model for this subcircuit looks as follows:
.SUBCKT NPN1 1 2 3 4
Q1 1 2 3 N1
Q2 4 1 2 P1
D1 2 3 DZ
D2 4 1 DCS
.ENDS
The first line, after the .SUBCKT (all models start with a dot) lists
the name of the subcircuit and the order of connections (which will be
followed in the netlist). The next four lines list the device types, the
connections and the name of the model. The last line signified the end of
the subcircuit listing.
Spice lets you define global nodes. This is especially convenient
for the substrate and avoids cluttering up the schematic with unnecessary
lines. This feature is used throughout this book for bipolar devices.
However, you will have to remember to place the contact to the substrate
(SUB) at the appropriate point (almost always the most negative supply).
Spice now needs a model for each of the devices used. For example
(for a 20-Volt process):
.MODEL N1 NPN IS=3.8E-16 BF=220 BR=0.7
+ ISE=1.8E-16 IKF=2.5E-2 NK=0.75 IKR=3E-2 NE=1.4 VAF=60
+ VAR=7 RC=63.4 RB=300 RE=19.7 XTB=1.17 XTI=5.4
+ TF=1.5E-10 TR=6E-9 XTF=0.3 VTF=6 ITF=5E-5 CJE=0.21E-12

+ MJE=0.33 VJE=0.7 ISC=5E-12 KF=2E-13 AF=1.4

.MODEL P1 PNP IS=1E-15 BF=100 CJE=0.175E-12 XTI=5.4
+ MJE=0.38 VJE=0.6
.MODEL DZ D IS=1E-18 RS=250 BV=5.9 IBV=10UA
+ TBV1=1.8E-4
.MODEL DCS D IS=1E-17 RS=10 ISR=5E-12 CJO=0.85E-12
+ M=0.42 VJ=0.6
Note that the model for DZ has no capacitance; this is already
present in the base-emitter diode of N1.
The Model for the Lateral PNP Transistor
For a lateral PNP transistor the Spice bipolar transistor model alone
is woefully inadequate. This type of transistor 3 (Emitter)
not only produces a substrate current when it

saturates but also in its normal operation;
Q11 Q31
neither of these is present in the Spice model.
To correct this flaw, we need to use a 2 (Base)
Q21
subcircuit again, only this time two additional
transistors are required, one to cause the
substrate current at saturation (Q21) and one at
normal operation (Q31); the parameters of the 1 (Collector) 4 (Substrate)
latter (particularly IS and BF) are chosen so that
Fig. 2-12: Equivalent circuit
the substrate current is smaller than that of Q11 for a lateral PNP transistor.
(generally about 20%).
The model for this subcircuit looks like this:
.SUBCKT PNP1 1 2 3 4
QP11 1 2 3 QP1
QP21 4 2 1 QP2
QP31 4 2 3 QP3
.ENDS
And the models, again for an arbitrary example of a 20-Volt
process:
.MODEL QP1 PNP IS=1E-16 BF=89 VAF=35
+ IKF=1.2E-4 NK=0.58 ISE=3.4E-15 NE=1.6 BR=5
+ RE=100 RC=800 KF=1E-12 AF=1.2 XTI=5 ISC=1E-12
+ CJE=0.033E-12 MJE=0.31 VJE=0.75 CJC=0.175E-12
+ MJC=0.38 VJC=0.6 TF=5E-8 TR=5E-8
+ XTF=.35 ITF=1.1E-4 VTF=4 XTB=2.3E-1
.MODEL QP2 PNP IS=5E-15 BF=150 RE=100 TF=5E-8 XTI=5

.MODEL QP3 PNP IS=1E-18 BF=25 CJC=0.85E-12

+ MJC=0.42 VJC=0.6 XTI=5 RE=100
MOS Transistor Models
Once upon a time there was a company which brought out its own
variation of the Berkeley Spice program: HSPICE. It specialized in making
refined models for MOS transistors, many of them. The models were called
levels and many companies bought their own levels, like boxes at the opera.
AMD had three of them, Siemens acquired two. Motorola, National
Semiconductor, Sharp, Cypress, Siliconix and a few others only got one.
By 1995 there were 39 such levels and us poor ordinary folks couldn't
access most of them: they could only be used by the company who had
sponsored them.
At last good old Berkeley came to the rescue. A team of researchers
developed the BSIM model (Berkeley Short-channel IGFET Model). The
team stayed with it, through BSIM1, BSIM2, BSIM3 and even BSIM4.
These models divided the MOS transistors in ever finer structures, tracking
the trend toward geometries far below 1um. As of this writing BSIM3.3 is
the dominant model in the industry, leaving the many HSPICE levels in the
dust.
Naturally HSPICE took the BSIM models and made its own version,
adding more levels.
The increasing BSIM refinements have its toll: the number of
parameters has become very large, so large that it takes an entire book to
explain them. For digital ICs, which require utmost speed, this simply has
to be accepted. For analog designs, which invariably use larger dimensions
to obtain adequate performance (especially for matching), it is a burden
only grudgingly tolerated. MOS model-making has become an art
dominated by the digital realm, of limited use to the analog designer.
In a modern BSIM model you are confronted by a mass of data
which almost always is presented in an arbitrary way, lacking an
organization which would make it more understandable. To help in a minor
way, they are grouped here; the bold-faced parameters are absolute values;
all others are modifiers. Parameters in square brackets are temperature
coefficients.

Threshold Voltage: VTHO, K1, [KT1, KT1L], K2, [KT2], K3, K3B,
DVT0, DVT0W, DVT1, DVT1W, DVT2, DVT2W, VBM, VOFF, KETA,
PSCBE1, PSCBE2.
Mobility: UO, UA, [UA1], UB, [UB1], UC, [UC1].
Saturation: VSAT, [AT], A0, AGS, A1, A2, B0, B1, DELTA, EM, PCLM,
PDIBLC1, PDIBLC2, PDIBLCB, DROUT, PVAG, AGS, ALPHA0,
BETA0.
Sub-Threshold: ETA0, ETAB, NFACTOR, DSUB.
Geometry: W0, DWB, DWG, LL, LLN, LW, LWL, LWN, WL, WLN,
WW, WWL, WWN.
Capacitances: CGS0, CGD0, CGB0, CJ, MJ, MJSW, PBSW, CJSW,

MJSW, CJSWG, MJSWG, PBSWG, PB, CGSL, CGDL, CKAPPA, CF,
CLC, CLE, DLC, DWC, ELM, CDSC, CDSB, CDSCD, CIT,
Resistances: RSH, RDSW, [PRT], PRWB, PRWG, WR, LINT, WINT
Process Parameters: TOX, XJ, XT, NCH (PCH), NGATE, NLX, NSUB,
GAMMA1, GAMMA2, JS, [XTI], NJ, JSSW.
Noise: AF, KF, EF, EM, NOIA, NOIB, NOIC
BSIM models also allow "binning": several models are written for
different geometries of the same device, and then selected to fit into a range
of gate width and length with the parameters LMIN, LMAX, WMIN and
WMAX. While this is not really necessary for the parameters listed above
(some foundries, notably AMS, manage to create equally accurate model
without binning), the Monte Carlo variations should be tied to channel
width and length (i.e. area). Note that the multiplier M is used for
transistors with a channel width beyond WMAX.
To get into more detail on the many parameters, you will need to
consult the original Berkeley documentation (see references). Be
forewarned: this is a lengthy document.

Resistor Models
A Spice resistor model has no stray capacitance, nor does it

recognize any possible effect by surrounding layers. There are some cases
where such a simple model is inadequate. For example, the frequency (and
phase) response of large-value resistors (50kΩ and more) can be significant
enough to bring about oscillation in a feedback path. Also, an error is
introduced in a divider, if the resistors are diffused and placed in the same
pocket (or "tub"); each resistor is at a different DC potential and their
voltage dependence will result in slightly different values. This error
becomes large with ion-implanted resistors.
Some simulation programs have the capability to extract stray
capacitances from the layout, but few pay heed to voltage dependence. If
you want the complete behavior before the layout is done, here is a model:
3 1
.SUBCKT RCV 1 2
R1 1 4 RB {m/3} D1 R1
R2 4 5 RB {m/3}
R3 5 6 RB {m/3} 4 I1
D2 R2
V1 6 2 0
B1 6 1 I=I(V1)*(0.0033*((V(3)-(V(1)+V(2))/2))^0.6) 5
D1 1 3 DRSUB {m/2} D3 R3
6
D2 4 3 DRSUB {m}
D3 5 3 DRSUB {m} D4
V1
D4 6 3 DRSUB {m/2}
.ENDS
.MODEL DRSUB D IS=1E-16 RS=50 2
+ CJO=2.7E-14 M=0.38 VJ=0.6
Fig. 2-13: Equivalent
circuit for a 3-
This is again a subcircuit. The resistor is segment integrated
divided into three equal sections and the stray resistor.
capacitance is represented by four diodes to the
surrounding n-type material (assuming that the resistor is p-type).
To model the voltage dependence, the current is measured in the
dummy voltage source V1 (with zero voltage) and from it a current I1 is
created and subtracted from the total current through the resistor. The value
of this current is:
0.6
  V (1) + V ( 2 )  
I1 = I (V 1) ⋅  0.0033 ⋅  V ( 3) − 
  2 
where 0.0033 and 0.6 determine the amount and shape of voltage
dependence. Note that the bias voltage is applied from terminal 3 to the

mid-point of the resistor. B

(in Simetrix) is an arbitrary
-10
function, serving as a 160 Sections
current-controlled current -15
source.
Contrary to -20
common belief, a three
dB
-25
section lumped model is
remarkably accurate. -30
3 Sections
Compare the frequency

response of such a model -35
with one that has 160 -40

sections. 100k 200k 400k 1M 2M 4M 10M 20M 40M
Frequency / Hertz
Fig. 2-14: Comparison of lumped resistor

models.
Models for Capacitors
There are only two cases where a simple capacitor model (i.e. an
ideal capacitor) is inadequate:
1. There is a requirement for unusual precision. If one plate of an
oxide capacitor is a diffused layer (or a poly layer with a high sheet
resistance) the capacitance will decrease slightly as the potential across the
plates is increased. A competent model will reflect this non-linearity.
2. The capacitor is used at the high-frequency end. Here it is not of
great importance for the model to show the non-linearity, but to reflect any
series resistance and stray capacitances from both the lower and the upper
plate to neighboring regions.
Pads and Pins
If you are working at high frequencies - say above 50MHz - you

need to consider the properties of the pads, the ESD protection devices, the
bonding wires and the package pins. A pad has a capacitance to the
underlying layer (usually ground); with an ESD protection device this can
easily amount to more than 1pF. The bonding wire has an inductance; it
may be small (perhaps 7nH, but this depends on the length of the wire), but
it begins to play a role above about 100MHz. Then there is the package pin
capacitance, which is not to ground but between pins (about 1pF, but
greatly dependent of the package).

Just How Accurate is a Model?
The quality of device models from wafer-fabs varies greatly. A few

are outstanding, unerringly accurate and complete. Others are so bad that
they will almost guarantee major flaws in your design. The majority of
them are incomplete for analog design.
It pays to examine the models before starting to simulate. If the
NPN transistor model is not a subcircuit, use it with caution; behavior in
saturation is going to be different in the real circuit. If the lateral PNP
model is not a subcircuit, it doesn't make much sense to use it at all.
A set of device models is not really ready for use until it has been
tested in actual circuits. Unfortunately models are commonly put together
by people who are not designers (especially not analog designers), so they
tend not to be verified in real-world applications.
This is especially true for bandgap references (see chapter 7), which
demand uncommon accuracy from the bipolar transistor models. Even a
small error in VBE (i.e. the basic diode voltage) and its temperature
coefficient causes intolerable errors in the reference voltage. Here it is in
fact preferable to set such parameters as IS (and its modifiers) so that it fits
(several) designs existing in silicon.
You should also check the models for the presence of Monte Carlo
parameters. If there aren't any, you are going to be seriously handicapped
for an analog design.

Camenzind: Designing Analog Chips Chapter 3: Current Mirrors
3 Current Mirrors
Bob Widlar was a truly great designer of analog ICs. He was wild
and totally unmanageable and had an odd sense of humor. The press loved
him and he had a flair for self-promotion. He shunned computer analysis,
preferring to breadboard his circuits, but time and time again he came up
with nuggets of design details and products which were thought to be
impossible. Burned out by the frenzy of Silicon Valley he moved to
Mexico, where he died in 1991 at age 53.
One of Widlar's early contribution is the +V
current mirror, a design detail (or design element)
I2
which you will now find in just about any analog IC. I1
Start with the primary current, I1, which flows 50u
into the diode-connected transistor Q1. This produces
a voltage drop across Q1, namely that of its base-
Q1 Q2
emitter diode; this voltage drop is called a VBE.
Now connect the base and emitter of a second,
SUB
identical transistor, Q2, to the same nodes as those of
Q1. Since the base-emitter voltage of Q2 is the same
Fig. 3-1: The Widlar
as that of Q1, it follows that its collector current current mirror.
should be the same as that of Q1 and, therefore I2=I1.
Well, not so fast. There are errors, two of them. The first one
concerns the base currents. I1 splits into
54
three paths: the collector current of Q1
and the two base currents. Assuming a
52
minimum current gain of 100, each base
current amounts to 1% of the collector
I2 / uA
50
current, for a total of 2%. So the collector
48
currents of Q1 and Q2 are 2% smaller
than I1, worst-case.
46
The two transistors may be
0 1 2
identical, but they are not necessarily
3 4 5
Collector Voltage Q2/V operated identically, which is error

1V/div
number two. The collector voltage of Q1

Fig. 3-2: The current of Q2 depends
on its collector voltage. is always VBE, but the collector voltage
of Q2 may be anything. As

The Current Source
All current mirrors start with a current source, from which one or
more currents are derived. For ICs, a current mirror is a more basic
element than a current source, which is the reason they are discussed
first.
However, be aware that there is a significant difference between a
theoretical current source (as in a simulation) and a practical one. In a
simulation a current source will do anything to keep its programmed
current level, including building up thousands of volts. In an actual
circuit the supply voltage limits the excursion.
Also, little distinction is usually made between a current source
and a current sink (e.g. I1 in figure 3-3) . For convenience all of them
are usually termed current sources.
we have seen in chapter 1, the gain is affected by the collector voltage (the
Early effect), increasing as the collector voltage is increased. Thus I2 is not
exactly steady. For this particular transistor (made in a process capable of
20 Volts) the change amounts to 8% from 0.3V (the saturation voltage of
Q2) to 5 Volts. (I1 is 50uA for all examples in this chapter).
This is the most simple current mirror and, as we shall see in figures
3-7 and 3-9, we can improve its performance considerably with additional
devices. There is also a lateral-PNP equivalent. Using a
+V
split collector (see figure 1-17), this current mirror needs
only a single device. Each collector being smaller, the
Q1
maximum current is more limited (depending on the
process, about 100uA).
I1
I2 The voltage 60
50u dependence of a PNP 58
current mirror is 56
54
SUB generally a bit worse 52
than that of an NPN
I2 / µA
50
Fig. 3-3: Current
mirror with
design (here about 48
lateral PNP. 12% change). The 46
44
voltage of the second 42
PNP collector can move to within 0 1 2 3 4 5
about 0.3 Volts of +V. If you let it go Voltage Collector 2 of Q1/V 1V/div
any higher (or disconnect the collector

Fig. 3-4: Voltage dependence of I2.
completely), you get a substrate current
about equal to I1.

+V The current mirror also works with MOS

I2 devices, but it is not quite correct to call M1 a "diode-
I1 connected transistor" (there is no "junction" diode).
The
52
change in current
M1 M2
is only about 1.5% 51
from 1 to 3 Volts 50
W=5u W=5u
L=2u L=2u (0.35u process), 49
I2 / µA
but only because 48
Fig. 3-5: Simple the channel 47
MOS current mirror. lengths were made 46
quite large. It takes at least 0.5 Volts at

0 0.5 1 1.5 2 2.5 3
the drain of M2 to make the mirror Drain Voltage M2/V 500mV/div
work, a figure which you can improve
Fig. 3-6: The voltage dependence
by making the devices much wider. The of an MOS current mirror can be
mirror can be inverted by using p- made smaller by increasing
channel devices. channel length.
Now let's see how we can
improve the performance of the basic Widlar circuit (not that we are any
smarter than Widlar, but we have had a long time to work on it and have
much better tools now).
+V A first step is to place resistors in the emitters
I2 (or the sources in case of MOS). With 6kOhm in the
I1
50u
example here we drop 300mV across the resistors. If
the current in Q2 wants to be higher than I1, it would
also cause a higher voltage drop across R2. This latter
Q1 Q2 increase forces I2 back to where it is more or less equal
to I1. There
R1
6k
R2 is, however 50
6k
still the base 49.8
SUB
current error, 49.6
Fig. 3-7: Improved which is not 49.4
current mirror with improved. 49.2

I2 / µA
emitter resistors. 49
There 48.8
is a penalty: The voltage at the 48.6
collector of Q2 cannot go any 48.4
lower than the voltage drop 48.2
across R2 plus the saturation 0 1 2 3 4 5
voltage of Q2, about 600mV total Collector Voltage Q2/V 1V/div
for this case. From this point to

Fig. 3-8: Voltage dependence is now
the supply voltage (5 Volts) I2 reduced to 0.7%.

changes only about 0.7%. A measure of quality of a current source is its

output impedance, i.e. the change in voltage divided by the change in
current. This has now increased from 1.1MOhm for the original current
mirror to 12MOhm.
If you want to use emitter resistors in the PNP equivalent, you will
need to use two separate transistors rather than a split collector.
+V An even greater improvement can be made with the
I2 addition of a transistor. This circuit, invented by George
I1 Wilson, is naturally called the Wilson Current Mirror
50u (analog designers don't get Nobel prizes, they get a circuit
named after them). Q3 acts as a cascode stage; its sole job
Q3
is to shield the important matching transistors, Q1 and Q2
from any
Q1 Q2
fluctuation in the 49.6
output voltage. It 49.55
SUB
does this job and 49.5
more: by a happy 49.45
coincidence the
I2 / µA
Fig. 3-9: 49.4

Wilson current three base currents 49.35
mirror.
cancel and I2 is now 49.3
within about 1% of I1 and changes 49.25
only about 0.09% over the useful
0 1 2 3 4 5
voltage range (an output impedance
Collector Voltage Q3/V 1V/div
of 90MOhm).
Note, however, that the useful
Fig. 3-10: Performance of the Wilson
voltage range stops at a little over 1 current mirror.
Volt, given by the
+V
VBE of Q2 plus the saturation voltage of Q3.
Q1 Naturally there is a PNP equivalent for the Wilson
current mirror. We can again use a split-collector device
Q2 for Q1. The output voltage can go to within about 1 Volt of
+V (at room temperature). Here the improvement is not
I1 quite as good (the output current changes by about 0.5%).
There is still a systematic error in the basic Wilson
I2
Fig. 3-11: current mirror: The two transistors intended to match don't
PNPSUB Wilson have the same collector voltages; one is at VBE, the other
current mirror.
at 2 VBE. In the relentless pursuit of perfection, given at
birth to all analog designers, we shall now proceed to eliminate it. Enter a
fourth transistor.

+V The only purpose 51
I2 of Q4 is to lower the 50.8
50.6
I1 collector voltage of Q1 to
50.4
the same level as that of
I(Q3-C) / µA
50.2
Q2. With this I2 is now 50
Q4 Q3 within 0.6% of I1 and 49.8
changes by less than 49.6
Q1 Q2
0.08% with voltage. 49.4
The single sweep 49.2
in this DC analysis is, 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5

SUB
however, deceiving. The V1/V 500mV/div
Fig. 3-12: Four- depicted curve can only

transistor mirror. be observed once in a Fig. 3-13: Performance of the
four-transistor current mirror.
53
great while, when all four devices
52 match perfectly. Only a Monte
51
Carlo analysis can tell you what
really will happen in production.
50
The remarkably small change with
I2 / µA
49 output voltage is a fact, but the

48
output current will vary by ± 3%
because of mismatch.
47
1 1.5 2 2.5 3 3.5 4

Current mirrors need not
4.5
Collector Voltage Q3/V be restricted to 1:1 relationship

500mV/div
Fig. 3-14: Although the output current now between input and output current.
changes little with voltage, there is still If the critical transistor on the
considerable variation due to mismatch, as
a Monte Carlo analysis will show.
output side is increased in size, its
collector current is increased too.
+V +V In a bipolar transistor the current ratio is
I2=3xI1 I2=I1/3 determined by the size of the emitter
I1 I1 (more precisely, the active emitter length;
see chapter 1) but a accurate ratio is in
practice only achieved if you work with a
Q1 Q2 Q1 Q2 number of identical emitters. In figure 3-
15 Q1 has one emitter while Q2 has three
SUB SUB (they can all be in the same base),
Fig. 3-15: 1:3 resulting in a current which is three times
Fig. 3-16: 3:1
current ratio. current ratio.
that of I1. In figure 3-16 Q1 has three
emitters and Q1 one, which causes I2 to have one-third the value of I1. Any
ratio is possible (such as 3:2 or 5:3). In a CMOS design the ratio can be

obtained simply by varying the channel width of one of +V
the transistors, but best matching is achieved by using I2=3xI1

I1
identical, multiple devices.
This scheme can be expanded to creating
multiple currents (i.e. additional transistors with their M1 M2
bases and emitters connected in parallel to those of Q2,

W=10u W=10u
but their collectors separate) in any ratio you desire. L=2u L=2u
M=3
But, in bipolar circuits, there is a limit: the base current
for each additional emitter is supplied by I1. Thus, with
Fig. 3-17: MOS
Q2 having three emitters (or two additional transistors), 1:3 current ratio.
the systematic errors (with a minimum gain of 100) is
4%; with 9 additional emitters this increases to 10%.
+V
There is a solution to this (have you noticed,
I1 I2=10xI1
there is always a solution, it just takes one or a few
Q3
additional transistors). Here, with the help of Q3, the
base current for Q1 and Q2 is supplied not from I1 but
Q1 Q2 from the positive supply, thus the base current error is
10
divided by the gain of Q3. In this way you can not only
R1
6k
R2
create large current ratios but also drive a substantial
600
SUB
number of separate transistors. In Fig. 3-18 emitter
resistors are used to get less of a change in I2 with a
Fig. 3-18: an varying output voltage (0.7% from 0.7V to 5V); if you
additional have 10 separate transistors, they all get 6kOhm in the
transistor supplies
the base current. emitter; if the current is simply multiplied by 10, R2 has
one-tenth the value of R1. Remember that best matching
is achieved if the resistors consist of identical sections, i.e. you create a
basic 600 Ohm device and use one for Q2 and 10 in series for Q1.
If you are thinking of turning I1 on and off rapidly, be aware that
this circuit is very slow to turn off; there is no discharge path for the bases
of Q1 and Q2. A resistor (or another current sink) from these bases to
ground helps to speed up the turn-off +V
time.
The base current problem does I1
not exist with CMOS devices, they

require no input current. Here you are M1 M2 M3 M4
free to add as many dependent current
sinks as you desire - if the change in W=10u W=10u W=10u W=10u
current with output voltage doesn't L=1u L=1u L=1u L=1u
bother you. If this voltage dependence is

too large, you have the choice of Fig. 3-19: Multiple current mirrors
increasing the gate lengths, adding in MOS.

resistors in all sources or - you guessed it - add a few devices.

To reduce the influence of the output voltage we could use the
Wilson current mirror, as discussed above. But
+V
MOS devices cannot take advantage of one of its
features, the cancellation of base currents. For I1
I2 I3
50u
this reason the Wilson current mirror is not the M3 M5
best choice for MOS, a simple cascode stage has
R1
slightly better performance and can be made to 10k W=10u
L=0.35u
W=10u
L=0.35u
have a wider range in the output voltage.
M1 M2 M4
Here M3 and M5 simply shield M2 and
M4 from changes in the output voltage. Their W=20u W=20u W=20u
L=3u L=3u L=3u
gates are held at a voltage slightly higher than the
threshold voltage of M1 by causing a voltage
drop in R1. In our case here this bias voltage Fig. 3-20: Current mirror with
is 500mV, which results in quite a remarkable cascode transistors.
49.9
50.4
49.85 50.2
49.8 50
49.8
49.75
49.6
I2 / µA
I2 / µA
49.7
49.4
49.65 49.2
49.6 49
48.8
49.55
48.6
0.5 1 1.5 2 2.5 0.5 1 1.5 2 2.5
Drain Voltage/V 500mV /div Drain Voltage/V 500mV/div
Fig. 3-21: Performance of cascode Fig. 3-22: Figure 9-21 repeated with Monte
MOS current mirror. Carlo variations.
performance, but requires at least 0.7 Volts at the output. Lowering the
voltage drop across R1 lowers this minimum output voltage, but increases
the voltage dependence, which you can reduce again by using even larger
devices.
Again, don't get carried away by the impressive performance shown
with a single sweep, which assumes perfect matching. A Monte Carlo run
will show you the true behavior.
For CMOS Current mirrors there are three more sophisticated
schemes. Figure 3-23 is the one you frequently see in articles. M1 is a thin
device, producing a bias voltage about 100 to 200mV higher than the gate
voltages of M3 and M5. Since the gates of M2 and M4 are connected to
this point, these two devices act as cascodes, i.e. they shield the lower two
devices from voltage changes.

With the dimensions shown,

+V +V
I1A I1B
the circuit in figure 3-24 has exactly 50u
50u 50u the same performance with fewer I2
devices and less current

M1 M2
consumption; here the lower devices
M4 M1 M3
W=4u W=100u are dimensioned so that the gate

W=100u
L=2u L=2u L=2u W=100u W=100u
M3
voltage (at 50uA) has the required
M5 L=2u L=2u
value for cascode biasing. The upper M2 M4

W=10u W=10u
L=5u devices are then made wide enough
L=5u
to leave a comfortable margin W=10u

L=5u
W=10u
L=5u
between their source potentials and
Fig. 3-23: Widely
used mirror. the "on" voltage of the lower Fig. 3-24: Fewer
devices (i.e. the voltage drop devices, same
performance.
caused by channel resistance). This is a prime example
how much you can do by simply changing the channel
length and width of a CMOS transistor.
+V The circuit in figure 3-25 has the best performance.
50u
I3
The cascode bias voltage is set not only by the device
dimensions, but by the small (250mV) voltage drop across
R1
5k
R1. Since the current itself is almost certainly determined
by a resistor, R1 will track it. The flatter curve represents a
M1 M3
higher output impedance (100MOhm for 3-25, 33MOhm for
W=100u W=100u the others) which is 50.04
L=2u L=2u
M2 M4
important for high 50.03
3-23
gain in active 3-24

50.02
W=20u
L=5u
W=20u
L=5u loads.
50.01
All the
Fig. 3-25: 50
Best figures given here 3-25

uA
49.99
Performance. are for room
temperature only. 49.98
The threshold voltage, the resistor 49.97
and, in bipolar designs, the VBE 49.96
have temperature coefficients. 49.95
Make sure you simulate your 0.8 1 1.2 1.4 1.6 1.8 2 2.2 2.4 2.6 2.8
circuit over the entire temperature Drain Voltage/V 200mV/div
range. Fig. 3-26: Comparison of Performance.

Camenzind: Designing Analog Chips Chapter 4: The Royal Differential Pair
4 The Royal Differential Pair
Open any analog IC and you will find a differential pair. Or, more
likely, a half dozen. It has great advantages, even if amplifying a
"difference" is not even a goal.
The reasoning is simple: Individual integrated components have
large variations, but two (or more) of the same match very well. If you can
take advantage of the matching, you get better performance.
It isn't always true, of course. Noise, for example can be smaller in
a single-transistor stage and some of the most ingenious designs are
remarkably free of the common differential stage. But let's look at this
wondrous tool.
Two transistors - here bipolar - share a
common emitter current. If the voltages at
I2 I3 their bases are equal and the two transistors
Vcc
match perfectly, I1 is split into two equal
Q1 Q2 5 parts at the collectors, I2 and I3.
If we increase V1 (relative to V2), Q1
V1 V2
gets more of the current than Q2. If we
I1
100u 2
SUB decrease V1, the opposite is true.
But there are limitations and errors.
First of all, the current division (or input
Fig. 4-1: In a differential pair voltage to output current relationship) is not
a current is divided by two linear. We are dealing with two base-emitter
transistors.
diodes here, fundamentally exponential
devices. Not counting stray effects the emitter resistance is:
k∗T
re =
q∗ Ie
where k = Boltzman constant (1.38E-23 Joules/Kelvin)

Ie = the operating current through each emitter
This expression amounts to about 26 Ohms, at room temperature

and with a current of 1mA. If Ie drops to 100uA, re becomes 260 Ohms.

Since it is very much a function of current, re is called the dynamic emitter

resistance. The conversion from base voltage to collector current, the
transconductance, is
1
gm =
re + Re
where Re is the ohmic resistance of

the emitter, i.e. the resistance 90
between the emitter contact and the 80
emitter-base junction (usually a 70

I3 I2
60
few Ohms).
µA
50
As the current moves from 40
one transistor to the other, both 30
emitter resistances change and we 20
10
get a rather non-linear behavior.
1.8 1.85 1.9 1.95 2 2.05 2.1 2.15 2.2
Only a small portion of the curve V1/V 50mV/div
in the middle, when the two current
Fig. 4-2: The conversion from input
are equal or nearly equal, could be voltage to current (the transconductance)
called linear, though in truth it too is non-linear.....
is not a straight line.
The other variable in the
equation is temperature. The emitter
90
80
resistance is proportional to absolute
70
-50C 125C
temperature, so at high temperature
60 you get less gain or transconductance.
I2 / µA
50 There are also three sources of

40
error to be considered: 1. A small
30
portion of the emitter current comes
20
10
from the bases, not the collectors.
1.8 1.85 1.9 1.95 2 2.05 2.1 2.15 2.2
With a minimum hFE of 100 this
Input Voltage/V 50mV/div
makes the sum of the collector current
smaller than the emitter current by
Fig. 4-3: ...and also temperature-
dependent. 1%, 2. Transistors only match well if
the are treated identically. In this case
that specifically means the collector
voltages have to be the same. If one is higher than the other, its transistor
will have a higher gain because of the Early effect; 3. Devices never match
perfectly; there will be some differences in both VBE and hFE and thus
some uncertainty in the voltage at which I2 and I3 are equal, showing up as
an offset voltage.

A differential pair using MOS

transistors behaves almost identically, but
I2 I3
Vdd for entirely different reasons. There is no
M1 M2
dynamic emitter resistance; the gain is
W=50u W=50u
determined directly by the trans-
L=0.35u L=0.35u conductance. This transconductance is also
V1 V2
non-linear, increasing drastically with
I1
20u 2
increasing gate voltage. Whereas in the
bipolar transistor size is only of second-
Fig. 4-4: MOS differential pair. order importance, transconductance in an
MOS transistor is directly proportional to
gate width and decreases with increasing temperature.
18 18
-50C
16 16
I3 I2
14 14
125C
I(M1-drain) / µA
12 12
µA
10 10
8 8
6 6
4 4
2 2
1.8 1.85 1.9 1.95 2 2.05 2.1 2.15 2.2

1.8 1.85 1.9 1.95 2 2.05 2.1 2.15 2.2
V1/V 50mV /div

V1/V 50mV/div
Fig. 4-5: A CMOS differential pair is Fig. 4-6: ...and the transconductance
also non-linear ..... also has a temperature coefficient.
Notably absent in the error sources is any kind of input current; I2

plus I3 are indeed equal to I1. There is, however, an offset voltage and, for
equal sizes, MOS transistor have a larger offset voltage (i.e. mismatch) than
bipolar ones (about 2:1, but this depends
R1
40k
R2 greatly on the process). Remember you
40k
Out1 can always improve matching (for any
Out2
2VDC, Vcc
device) by increasing size (i.e. total area),
50mVpAC
Q1 Q2 5 preferably by using multiple small
devices.
Vin Vbias Let's get back to bipolar transistors
I1
100u 2
SUB and complete the differential stage. We
can simply use the two collector currents
to create voltages across two resistors. In
Fig. 4-7: A complete differential this example the voltage at the base of Q2
amplifier. is held constant - it is simply a DC bias

voltage large enough to overcome the base-emitter diode voltage (assuming

that there is a single 5-Volt supply). Vin, going to the other base, carries
the same DC bias level and has a 50mVp AC signal superimposed (i.e. it
moves from 1.95 Volts to 2.05 Volts). The gain of this stage is determined
by the ratio of the resistors to the dynamic emitter resistances. At 50uA (for
each transistor) re is 520 Ohms (26Ohmsx1mA/50uA). The gain from the
inputs (measured differentially, which in this case is simply Vin) to the
outputs (again measured differentially, i.e. Out1 + Out2) is 80k/1.04k or 77.
The gain to only one output is half of that.
It's not a great deal of gain and it cannot be made any larger by
simply increasing the values of R1 and R2. There is a DC voltage drop of 2
Volts across them, if we were to double their values the transistors would
saturate.
In reality the gain is always lower than obtained by this simple
calculation, which does not take into account the ohmic (i.e. access)
resistances in the emitters or the fact that a small percentage of the emitter
current is lost to the base.
Even with only 50mVp R1 R2
input there is already significant 40k
Out1
40k
distortion, about 5%. We can improve Out2

2VDC,
this by connecting resistors in series with 50mVpAC Vcc
Q1 Q2 5
each emitter. This makes the total
emitter resistance more linear, which Vin
R3 R4
Vbias
2k 2k
drops the distortion to less than 0.1% SUB
(with 50mVp input). But the gain has I1
2
suffered badly: less than 16 with a 100u
differential output, less than 8 single-

Fig. 4-8: Linearized differential
ended. amplifier
There is a competing approach:
R1 R2
40k 40k
two separate emitter current sources (or,
Out1
Out2 more precisely, current sinks) of half the
2VDC,
10mVpAC
Vcc value and a single resistor of twice the
Q1 Q2 5
R3
value connected between the emitters. If
Vin
4k
I2 Vbias
you take a poll among analog IC designers
I1
SUB
about half of them will swear that one is
50u 50u 2
better than the other. But in fact the two
circuits are identical in performance.
Fig. 4-9: A connection different To get more gain we need a better
from that of figure 4-8 but identical scheme for the output. In the vast
in performance. majority of applications an amplifier
needs only one output. Thus it is no loss

if we convert the differential signal to a single-ended one in the very first

stage. And, with a current mirror, the benefits are immediate.
If one NPN collector current is
Vcc
mirrored by Q3 (here a split-collector
Q3
Out lateral PNP) it opposes the current of the
R1 5 second collector. With no input signal
250k
Vbias2 (and perfect matching) the two are equal,
Q1 Q2 they cancel each other. But with an input
3
signal one increases, while the other one
Vin I1 Vbias1
100u decreases (hopefully by the same
2 SUB
amount), so that we only see their
difference at the output and we can use a
much larger output resistance. As drawn,
Fig. 4-10: Differential amplifier with
an active load. the gain of this stage is 278. And since
the gain is so large, we get quite a large
output signal with only 1mVp at the 3.5
input, which makes the distortion

reasonably small. Q3 is called an 3.4
active load. 3.3

Out / V
But there are two things wrong 3.2
with the circuit in figure 4-10. First, if

you were to specify a 250kOhm 3.1
resistor in an IC you might be 3

0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2
suspected of lunacy; its size would Time/mSecs 200µSecs/div
take up more space than all the other Fig. 4-11: Output signal with a
components together. Second, if you 1mVp sine-wave input.
look at the output waveform closely, you
notice that there is a DC current flowing through R1. At the right end we
connect it to a 3-Volt bias point, but at the left end the center of the sine-
wave is not 3 but 3.25 Volts, i.e. we have a built-in offset. There are two
reasons for this: 1. the two collectors of Q3 are not at the same potential and
2. the collector current of Q1 has to supply the base current for Q3.
We need something like R1 to fix the DC potential at the output.
The two opposing collectors are current sources/sinks. The smallest
difference between the two would cause the output potential to move up so
much that Q3 would saturate or down so much that Q2 would saturate.
In figure 4-12 all of these problems are fixed at once by adding a
second stage. Q4 is the same size as Q3 and is operated at the same current.
Now the collector voltages of both Q1/Q2 and Q3 are identical. Moreover,
the collector current of Q2 has to supply the same amount of base current

(for Q4) as the collector of Q1 does. In other words, with no input signal
the circuit is perfectly balanced; there is no built-in offset.
But you need to be careful here.
Vcc
Q3 The gain of this circuit is no longer fixed
Q4
5 by a resistor ratio, it is dependent on
transistor parameters. If these two stages
Out
Q1 Q2 are made part of an operational amplifier,
the feedback will take care of this. Or, if
Vin1 I1 Vin2 I2
100u 100u
the circuit is used merely as a comparator,
2 SUB
gain is of lesser importance than offset.
Fig. 4-12: High-gain, balanced 4.5

differential amplifier.
If you simulate the circuit 4
as shown, you will get a different Out / V 3.5
and rather odd output curve. 3
Current sources in a simulator are 2.5

ideal devices, they will do anything
2
to supply the exact amount of
current, which includes supplying 1.999 1.9994 1.9998 2 2.0002 2.0006
their own voltage (if necessary V in1/V 200µV/div
thousands of volts). An actual

Fig. 4-13: Transfer curve for circuit in
current sink such as I2 will figure 4-12.
collapse near ground, but the ideal
one keeps right on working
down to a very large
4.5 negative voltage. For this
reason there was an
4
additional device in the
3.5 simulation diagram, a diode
Out / V
from Vin2 to Out which

3
clamps the output swing at
2.5 the low end.
The last circuit may
2
be perfectly balanced but, as
1.999 1.9992 1.9994 1.9996 1.9998 2 2.0002 2.0004 2.0006 2.0008
in any circuit, the matching
of the devices is still subject
Vin1/V 200µV/div
to variation. If we run a
Fig. 4-14: Even a perfectly balanced differential Monte Carlo analysis we
amplifier (figure 4-12) has an offset voltage due to
mismatch. meet the real world: the
random offset voltage.

M3 M4 Figure 4-15 shows the

M5
Vcc same design in CMOS. Note that
W=20u W=20u
L=2u L=2u M3, M4 and M5 are all the same
5
W=20u
L=2u size, thus balance is achieved with
M1 M2
Out
I2 having a magnitude of one-half
I1. Here, of course, we are not
W=10u
L=2u
W=10u
L=2u
concerned about cancellation of
Vin2
Vin1 I1
100u
I2
50u base currents but identical gate
2 SUB
voltages are still important.
The random offset voltage
is of greater concern in a CMOS
Fig. 4-15: Balanced CMOS differential
amplifier. design. MOS transistors match
less well than bipolar ones. That
has been true since the start of the IC industry. It is not that an MOS
transistor is inherently inferior in this respect, but that matching,
specifically the offset voltage is based on different process parameters. For
the bipolar transistor matching is determined by the depths of diffusions,
particularly the base and emitter. The dimension having the greatest
influence on offset voltage in an MOS transistor is the gate insulator
thickness. While control has steadily increased, the insulator thickness
needed to be steadily decreased to get sufficient gain for the ever smaller
devices. The gate insulator thickness has by far the smallest dimension in
an IC and thus continues to create fluctuations in threshold voltage larger
than a diffusion will cause in VBE.
Two more additions. The base current of a bipolar transistor is a

disadvantage. If its operating current is say 25uA and the minimum hFE
100, the input draws (or supplies in the case of a PNP transistor) as much as
250nA. We can decrease this with a
Darlington configuration.
Q3 and Q4 carry the base current
I2 I3
of the differential pair. At their bases the
Q3 Q4 Vcc
input current is reduced by a factor of
5
another hFE. Thus the input current is Q1 Q2
Iin = I1/2(hFE)2 SUB
or 2.5nA. There is a price, though: V1 I1 V2
1. The input voltages need to be 100u 2
higher by a VBE so that there is enough

headroom for I1;
Fig. 4-16: NPN Darlington input
2. Q3 and Q4 run at very low stage.
current, thus their speed is bound to be

rather slow; and

3. the leakage currents of Q3 and Q4 run into the bases of Q1 and
Q2, showing up multiplied by the hFE of the latter two in I2 and I3. This is
a danger at high temperatures (say above 90oC).
Switching time and leakage current can be reduced with small
currents from the emitters of Q3 and Q4 to ground, in effect running the two
transistors at a higher operating current. But of course you can't go too far
in that direction: the input current
Vcc increases again.
I1
50u If you invert the circuit and use
(lateral) PNP transistors at the input,
Q1 Q2 you gain an advantage which is often
In Q3 Q4
useful: one input can be at ground.
Out
There is enough headroom for the
Q5 Q6 current mirror (Q5 and Q6) even if the
input is 200 or 300mV below ground.
SUB The limit here is one diode drop below
ground, at which point the base of Q3
Fig. 4-17: A PNP Darlington input
will forward-bias against the substrate.
stage allows the input to move below The same limitation in speed and upper
ground. temperature apply.
The Darlington Pair

Sidney Darlington was born in Pittsburgh, Pennsylvania, in1906 and joined
Bell Laboratories in 1929, where he remained until his retirement 42 years later. He
was a theorist who also liked to tinker with circuits.
In 1952 silicon transistors made at Bell Labs had low gain (5 to 15).
Darlington checked out two of them (only a few were available) and experimented at
home over a weekend. He found that by connecting the emitter of one to the base of
the other, the gain would be the product of the two, 25 to 225, a much more useful
range. He then suggested a method fabricating the pair out of a single block of
silicon (with a common collector), thus coming very close to the idea of a monolithic
integrated circuit. Bell Labs was issued a patent (2,663,806) in 1953.
Darlington died in 1997 at age 91.

Camenzind: Designing Analog Chips Chapter 5: Current Sources
5 Current Sources
Ever since the dawn of analog IC design (all the way back in 1962)
a succession of very clever people have been trying to conjure up
something that would produce an accurate current. The results have been
uniformly dismal.
There happens to be a capable voltage source in ICs, the bandgap
reference (which we shall get into next). So, to get a current, one would
think, all one needs is an accurate resistor; after all I = V/R. But, unless you
want to add a costly thin-film layer and laser trimming, there are no
accurate resistors. What we get are resistors made from diffused or
deposited silicon layers which vary in resistance from wafer to wafer and
have a considerable temperature coefficient.
So, don't expect any precision here. At best, an integrated current
source can provide a small current without the use of large-value resistors
and make this current more or less independent of the applied voltages.
Current Sources with Bipolar Transistors

Vcc
The first example uses a diode-connected
transistor (Q3) as a reference voltage. A primary R2
I1
40k
current flow through R2, Q2 and Q3. The base of Q1 is
at two VBE (base-emitter or diode voltage), thus its
Q2 Q1
emitter has a potential of one VBE. The current
through Q1 is thus R1
20
VBE/R1. If we let Q3 40k
18
16
the voltage at the SUB
14 collector of Q1
12
(the destination of Fig. 5-1: Current
I1 / µA
10 source based on
8
the current) drop VBE (Q3)
6 below about 1
4
Volt, Q1 saturates
2
00
and draws from the primary current.
1 2 3 4 5
Collector Voltage Q1/V

But above 1 Volt the current is very
1V/div
Fig. 5-2: I1 vs. output voltage.

constant, changing less than 0.3%. This
quality is best expressed as output

impedance, i.e. the change in voltage (4 Volts) divided by the change in

current (about 53nA). Thus the output impedance of this circuit is about
75MOhm. Not bad for using only 80kOhms in resistance.
A diode has a negative temperature coefficient and a (diffused)
resistor a positive one. The two combine to give the current a strong
negative temperature coefficient, a
18
change of about -29% from 0 to 16
1000C. 14
The VBE is of course no Zener 12
diode, it varies a bit as the current
I1 / µA
10
changes, which makes the current 8
6
dependent on the supply voltage (a 4
+2% increase as the voltage moves 2
from 4.5 to 5.5V). 0 1 2 3 4
And then there is the variation Supply Voltage/V 1V/div
in production: ± 28%, mostly caused

by the variation of R1. Changes with Fig. 5-3: I1 vs. supply voltage.
temperature and supply voltage must
be added to this figure.
Also be aware that we are wasting some current: it takes 90uA
through R2 to produce 20uA in Q1.
A word about the choices in the examples of this chapter:

• For bipolar circuits the use of (base) diffused resistors is assumed
with an absolute variation of ± 25%. This is probably the largest variation
you will encounter; CMOS foundries often guarantee smaller variations,
especially for poly resistors.
• Each current source produces about 20uA, an arbitrary choice
made to allow comparison.
• Strictly speaking these circuits are current sinks, not sources. To
make a circuit in which the current is delivered from the positive supply, the
design is turned upside-down, NPN transistors are made PNP and N-
Channel ones P-Channel.
• Supply voltages are arbitrarily selected from 5, 3 and 1.8 Volts.
• As before, the fourth (bipolar) transistor terminal is hidden; all of
these terminals are connected together to the most negative supply voltage
with the symbol SUB. This avoids cluttering up the schematic. For MOS
transistors the connection is left visible as a choice needs to be made for the
P-Channel device.

On to the second example, a rare case where better

Vcc
performance is achieved with fewer devices. Through
R1
I1 feedback Q2 regulates the current of Q1, holding I1 more
40k
constant. In this way the output impedance increases to
Q1
500MOhm, the Monte Carlo variation decreases to ± 26%
and the change with supply voltage from 4.5 to 5.5V to
Q2 +1.8%. But the voltage at the collector of Q1 still must not
R2
40k
drop below about 1 Volt.
SUB In both of these current sources the emitter of the
output transistor is sitting on top of one VBE, about 0.65V
Fig. 5-4: at room temperature (and higher at low temperature). For
Improved VBE
current source.
low-voltage ICs we need a design in which this emitter is
at or very near ground.
20
18 16
16 14
14 12
12
10
I1 / µA
I1 / µA
10
8
8
6
6
4
4
2
2
00 1 2 3 4 0 1 2 3 4 5
Collector Voltage Q1/V 1V/div Supply Voltage/V 1V/div
Fig. 5-5: I1 vs. output voltage of figure 5-4. Fig. 5-6: I1 vs. supply voltage of figure 5-4
Figure 5-7 looks like a current mirror, but it isn't. Vcc

There is a deliberate mismatch between the two
R2
transistors. They get the same voltage at their bases but, 40k
I1
while Q2 has a straightforward base-emitter diode to
ground, the path for Q1 consists of a lower diode voltage Q2 Q1
(because of the larger area using three emitters) and a
resistor. The difference in voltage between the two R1
diodes is: SUB 3.75k
k∗T  A1∗ I 2  Fig. 5-7: Delta-VBE

deltaVBE = ∗ ln   current source.
q  A2∗ I1
where k = Boltzman constant (1.38E-23 Joules/Kelvin)



A1 = emitter area of Q1
A2 = emitter area of Q2
I2 = current through Q2
k*T/q amounts to about 26mV at room temperature and I2 is about 110uA.

Thus, with a desired I1 of 20uA, the voltage drop across R1 is
26mV*ln(16.5), i.e. I1 = 72.9mV/3.75k = 19.4uA. Note that delta-VBE is
independent of current, only the current ratio is important.
20
20
18
18
16
16
14
14
12 12
I1 / µA
I1 / µA
10 10
8 8
6 6
4 4
2 2
00 1 2 3 4
0 1 2 3 4 5
Collector Voltage Q1/V 1V/div Supply Voltage/V 1V/div
Fig. 5-8: I1 vs. output voltage of figure 5-7. Fig. 5-9: I1 vs. supply voltage of figure 5-7.
The voltage at the collector of Q1 can now go lower, to the

saturation voltage of the device plus the delta-VBE. There is little change
in current as the voltage at the output is moved (amounting to an impedance
of about 12MOhm) but dependence on supply voltage is quite large, a
+6.5% change as Vcc moves from 4.5 to 5.5V.
Since delta-VBE is proportional to absolute temperature (PTAT), I1
has a marked positive temperature coefficient, moderated only slightly by
the positive tempco of the resistors. Production variation (at a fixed voltage
and temperature) is ± 26%, dominated by the variation of R1.
The performance can be improved slightly by using a larger device
ratio. With Q1 having 10 emitters the output impedance increases to
15MOhms and the voltage dependence to 4.5% (4.5 to 5.5V).
The Quality of a Current Source
An ideal current source maintains the current level no matter what happens
at its terminals, which results in an impedance that is infinite.
A practical current source can approach this over a limited voltage range,
with an impedance of up to tens of Meg-Ohms (i.e. there is very little change in
current as the voltage across the current source changes. But its absolute level is
subject to (absolute) parameter variations, which are large in an integrated circuit.

Vcc You can also improve this performance with a

R2 simple measure. Suppose you connect the base of Q1
40k
not to the base of Q2, but to a point which
I1 counteracts a rising Vcc. By inserting a small
R3 amount of resistance in the collector path of Q2 we
413
get a node whose voltage is fairly constant. The
Q1
voltage at the base of Q2 still increases somewhat as
Q2 Vcc is increased, causing its collector current to
R1
1.8k
increase. But this makes the voltage drop across R3
SUB increase and, with just the right value, the base
voltage for Q1 changes little, at least over the critical
Fig. 5-10: R3 reduces
supply-voltage range in supply voltage.
dependence. Note
that, because
18
of the lower base voltage, the value 16
of R1 is lower for the same amount 14
of current. The easiest approach to 12

I1 / µA
circuits like Figure 5-10 is 10
8
simulation. Just try various values
6
for R1 and R3 until you get the right 4
current with minimal change. But , 2
in the layout, make these resistors 0 0.5 1 1.5 2 2.5 3 3.5 4
fairly wide; you are counting on Supply Voltage/V 500mV /div
matching. Fig. 5-11: I1 vs. supply voltage with R3

The change in I1 is now a mere optimized for the range 3 to 3.6 Volts.
±0.5% with Vcc varying between 3
and 3.6V (and even lower with a 4.5 to 5.5V range).
The temperature coefficient for this circuit is somewhat larger: a
+31% change from 0 to 100oC and the output impedance drops to about
7MOhms. Production variation is unchanged.
We are about to take a rather daring step. The primary current in the
previous circuits is a nuisance; it wastes power and takes up considerable
resistance. Why not replace it with a current source derived from the
current the circuit generates?
There is one flaw in this argument: the current must exist first.
There are two possible modes, one in which the current levels are as
intended and one where there are no currents at all. In other words, there
must be a current in Q2, which can be mirrored and fed back to Q1 and the
base of Q2 so Q2 can have a current, etc.

The usual solution is to employ a start-up circuit, designed to bring

Q2 to a level sufficient to sustain the loop. The start-up circuit then shuts
down and has no further influence.
Vcc But there is another way: leakage
Q3
currents. Q2 has two leakage currents, from
collector to substrate and from collector to
I1 base. These currents may be small (pA), but
R1
they are mirrored by Q3 and fed back into the
Q2
1.1k base of Q2, where they are amplified. And so
Q4
Q1 it goes around the loop, eventually reaching

R2 R3 microamperes.
300 300
SUB Two factors must be understood here.
First, we are not talking about a leakage
Fig. 5-12: Self-starting current caused by dirt. The very small reverse-
current source without junction currents measured in today's IC
large-value resistors.
devices are fundamental phenomena and have
nothing to do with cleanliness.
Second, the design and the
process must allow these small 20
currents to grow. If, for 18

16
example, there is a path from
14
the base of Q3 to Vcc or the
I1 / µA
12
bases of either Q1 or Q2 to 10
ground which can shunt 8
leakage (provided say by a very 6

4
large, reverse-biased junction),
2
the scheme won't work. If your 00 1 2 3 4 5
models are accurate, trust the
Supply Voltage/V 1V/div
simulation. Use a Monte Carlo
analysis to see if the circuit Fig. 5-13: I1 vs. supply voltage for figure 5-12.
starts up every time and do this
at temperature extremes where
leakage currents are either at their lowest or highest.
R1 has been added to counteract the remaining dependence on Vcc
(caused by the Early effect in Q2 and Q3). With that we get a change of
+0.4% as Vcc is increased from 4.5 to 5.5V. The circuit can have a supply
voltage as low as 1 Volt and the voltage at the output can be as low as 0.3V.
Lastly, the Erdi current source, a very clever design with an

astonishing performance. We start with an auxiliary current, Iaux. And
before you even have a chance to sneer at the fact that a current source is

Vcc used to make a current source, let me point out that

Q1 Q2 the accuracy of this current source is of no great
I1 importance. A bulk (epi) pinch resistor will do or
any of the lesser current sources discussed above.
Iaux Q5 Iaux is mirrored and split into two equal
10u
parts by Q1 and Q2; thus the operating currents for
Q3 Q4 Q3 and Q4 are equal. Q4, however has 3 emitters,
Q3 only one, thus there is a difference of about
SUB R1 R2
1.5k 1.5k 29mV (at room temperature). Unbalanced, the
collector voltage of Q3 rises until Q5 supplies
Fig. 5-14: Erdi current enough current to make up the difference. This
source.
current amounts to (delta-
VBE)/R2. 18
Vcc can be as low as 1 Volt 16
(or as high as breakdown voltages 14

vs. Supply Voltage
allow). Moving Vcc 20% changes 12

vs. Output Voltage
I1 / µA
I1 by 0.08%. The output 10
impedance is 50MOhm. 8
Temperature is strongly positive, a 6
+25% change from 0 to 100oC. 4
And the Monte Carlo variation is 2
roughly that of R2, here assumed 00 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2
Voltage/V 200mV/div
to be ± 25%.
Fig. 5-15: Performance of the Erdi current
source.
CMOS Current Sources
None of the bipolar schemes work well for CMOS devices. They
are based on VBE or delta-VBE , for which there are no equivalents.
Trying to use circuits such as Figures 5-10 or 5-14 with CMOS width-ratios
I1 leads to inferior circuits. Also, due to the square-law
behavior of the gate voltage, the variations are roughly
M1
double those of bipolar designs.
Fortunately the CMOS transistor is a current
Vref
W=4.5u source. If we simply apply a constant voltage to the
L=20u
1.2 gate (such as a reference voltage) we can tailor the
width and length of the device to give us a certain
current.
Fig. 5-16: MOS Using a rather exaggerated length, we can
transistor as a minimize the channel-shortening effect. In the example
current source.

here the output current varies little 8
with the applied voltage, amounting to 7
an impedance of 38MOhm. But the 6
variation (due to the uncertainty in the 5
I1 / µA
threshold voltage) is large: ± 39%. 4
Add to this the change with 3
temperature (0 to 100oC, -23%) and a

2
1
variation in the reference voltage (± 00 0.5 1 1.5 2 2.5 3 3.5
3% causes a change of 10% in I1). Output Voltage/V 500mV/div
Fig. 5-17: I1 vs. voltage for fig. 5-16.
The Ideal Current Source

Sometimes a compromise is the best solution. If we allow just one
component to be external to the IC and provide a pin for it, the
performance of a current source improves dramatically. All other currents
I1
within the IC can then be derived from it with
current mirrors and are thus inherently
+ M1 accurate.
100mV In the last circuit an op-amp compares
- W=5u
L=0.18u the voltage across an external resistor with a
low internal reference (divided down, for
R1
example, from a bandgap reference) and
5k
drives the gate (or base) of an output device.
Assuming no trimming, a 1% tolerance for the
external resistor, 3% for the reference voltage
Fig. 5-18: Accurate current
source with an op-amp and
and 2mV offset uncertainty for the op-amp, I1
external resistor. will be within 6% at any voltage and any
temperature.

Camenzind: Designing Analog Chips Chapter 6: Analog Measures
6 Time Out: Analog Measures
dB
Analog scales tend to be very large. As an example, the hearing
threshold of a young adult is 20 micro-Pascal; the maximum level without
damaging the ear can be more than 20 Pascal, a ratio of one to 1 million.
Particularly because of the widely varying sound levels a need for a
logarithmic measure appeared early on in electronics. There are two of
them: The Neper is based on the natural logarithm and named after John
Napier, a 16th century Scottish mathematician who came up with the
logarithmic table (and whose name was most likely spelled Neper in his
time).
In the 1920's a measure based on logarithm with base 10 began to be
used at Bell Laboratories. At first it was called the "transmission unit", then
re-christened the Bel, after Alexander Graham Bell. The idea is simple, a
Bel is the logarithm of two power levels:
P1
Bel = log
P2
But the Bel turned out to be a bit coarse; one-tenth of that suited the
Bell Labs people better, hence the decibel, or dB:
P1
dB = 10∗ log
P2
This is the ratio of two power levels. Since power is related to the
square of the voltage (or current), we get:
V1
dB = 20∗ log
V2
Neper has more or less disappeared as a measure, dB proved to be

more convenient. But, when using dB, always keep in mind there is a 2:1

difference between the ratios of power and those of voltages or currents (or
pressure).
Even though a logarithmic ratio is very convenient, it is helpful to
picture the (voltage) actual ratios:
-60dB 1/1000
-40dB 1/100
-20dB 1/10
-6dB 0.5 (exactly: 0.5012)
-3dB 0.707
0dB 1
20dB 10
40dB 100
60dB 1000
Fundamentally dB is relative, expressing only a ratio. But there are

many modifications in which one of the two levels are absolute, among
them:
dB(SPL) Sound pressure level, where the hearing threshold (0dB)

is based on 20uPascal.
dBm Power ratio where 0dB = 1mW. Originally this was based
on an impedance of 600 Ohms (that of a telephone line),
but now is used with any impedance (which is fine as long
as we calculate power ratios, not voltage ratios).
dBuV Voltage ratio relative to 1uV.
RMS
RMS calculation was introduced by Charles Steinmetz more than
100 years ago. Steinmetz grew up in Breslau, Germany (now Poland), but
shortly before he got his Ph.D. in mathematics and physics he had to flee to
Switzerland because of his socialist activities. From there he emigrated to
the U.S. and found a job as an assistant draftsman in Yonkers. The company
fabricated hat-making machinery, but soon expanded into electrical motors.
The year was 1889.
Steinmetz was a small man with a hunchback and one leg shorter
than the other, a deformity he inherited from his father. Though he made the
proverbial bad first impression, the people around him soon were in awe of
his razor-sharp mind. No surprise then that the overqualified draftsman was

at the forefront in AC engineering within four years. Through mergers and

acquisitions he found himself to be working for General Electric as head of
the calculating department in Schenectady and teaching at Union College.
He led a bohemian life; afraid to marry because of his inherited deformity,
he shared his house with an entire family and kept several crows, raccoons,
eagles, owls, squirrels, dogs and alligators. He resumed his socialist
activities, expounding his ideas in a book; he was against competition and
advocated an industrial reorganization by the government. It is remarkable
that he got along very well with his bosses at GE. In all respects he was a
delightful man who seemed to have a very happy life. Almost single-
handedly he moved electrical engineering from a craft to a profession.
Steinmetz found that few "electricians" used mathematics, his
specialty. The first curriculum in electrical engineering had started at MIT
in 1882 and very few people understood AC. George Prescott lamented in
1888: "It is a well-known fact that alternating currents do not follow Ohm's
law, and nobody knows what law they follow."
For example, there were two things wrong with the "average" value
meters of the time displayed: in the first place the true average of an AC
waveform should have been zero; in the second place the product of the
average current and voltage gave the wrong answer for power. Also, a phase
shift between voltage and current left almost everyone perplexed.
In 1893 Steinmetz presented his first paper on the use of complex
numbers in electrical engineering. It was heavy going, delivered in a thick
German accent. But he kept at it in paper after paper and then a massive,
three-volume text book. By 1901 he had it down pat and published a
textbook that was finally easy to understand.
What he said was this: In order to calculate the power correctly, you
need to square the voltage (or current), calculate its mean (average) and
apply the square root. Hence RMS - root-mean-square. Or a bit more
detailed: You divide the waveform into equal segments over one period,
square each segment, add up the squared values, calculate the average and
take the square root of that.
The power, by the way, is the average power. There is no such thing
as RMS power, only RMS voltage and RMS current.
For a pure sine-wave this works out as:
Vpeak
Vrms = = 0.707∗Vpeak
2

Here is a simple illustration of RMS

5
calculation: Four time segments of
100usec each. First a voltage is at 5 4
Volts, then a zero, then at 2 Volts and 3
Voltage / V
finally at zero again.
2
52 + 0 2 + 2 2 + 0 2 1
Vrms = = 2.69V
4 00 50 100 150 200 250 300 350
Time/µSecs 50µSecs/div
But the RMS calculation has Fig. 6-1: Arbitrary waveform for RMS
some limitations: it doesn't work with calculation.
non-linear elements. In Steinmetz's
time there were no transistors, not even vacuum tubes. There were only
linear elements (save perhaps for the occasionally saturating transformer),
so he didn't consider what would happen if the impedance changes while
you are measuring RMS voltage and current.
Take the case of a transistor stage, either linear or switching. You
want to determine its power dissipation, so you measure the current through
it and the voltage across it. But the impedance of the transistor constantly
changes and Ohm's law doesn't hold. The product of RMS voltage and RMS
current gives an absurdly wrong result for power. The only way you can
determine the power is to integrate the instantaneous values of voltage times
current. In a simulation, Spice does this very well.
But measurements aren't nearly so easy: "True RMS" instruments do
indeed have a circuit element which measures RMS rather than average. But
the inputs to almost all of them are capacitively coupled. If the waveform
you are measuring has a DC component, it is ignored and the result reflect
on the AC portion of it.
Noise
Imagine a current flowing through a wire connected between a
negative terminal on the left and a positive terminal on the right. Through
the wire are flowing millions of electrons from left to right.
Each electron carries a charge of 1.6e-19 Coulombs. Let's say we
observe a current of 1uA, thus 7.8e12 electrons pass every second. If the
interval between electron were the same, we would then see a ripple at
7800Ghz, like the teeth of a saw-blade moving at high speed.

But in a diode or a bipolar transistor, we see quite a different effect.

Here the current is initiated by electrons and holes moving across a barrier
and this movement is anything but smooth. Within any given time interval
one electron or hole may cross the barrier, or 5, or 100, or none. The
variation is so great that there is no discernable peak at 7800Ghz, or any
other frequency. In fact, because of the very large number of electrons, this
white noise or shot noise is so well distributed over the frequency range
that it has a constant level over the entire spectrum:
Inoise( rms ) = 2 ⋅ q ⋅ I ⋅ B
where q = electron charge (1.6e-19 Coulombs)

I = dc current
B = bandwidth in Hz
There are two things you should notice here. First: Noise increases
as the square-root of bandwidth. Second: When the current is decreased,
noise becomes a larger fraction of it.
Let's illustrate the second part. With a bandwidth of 10kHz, 1mA dc
produces 1.8nA(rms) of noise. That amounts to 0.00017% or -115dB.
With 1uA of current and the same bandwidth the noise is 56pA(rms), i.e.
0.0056% or -85dB. At 1nA we get 1.8pA of noise, which amounts to
0.18% or -54dB. All of which shows that it is harder to design a low-noise
circuit at low current levels.
There is also noise when no current flows at all. By the energy
imparted by temperature, some electrons will suddenly leave an orbit and
jump to another. The higher the temperature, the larger this irregularity
becomes. Thus a resistor, doing nothing but lying on a bench actually has a
noise voltage at its terminals:
Vnoise( rms ) = 4 ⋅ k ⋅ T ⋅ R ⋅ B
where k = Boltzmann constant (1.38e-23 Joules/T)
Thus a 1MOhm resistor always has a noise voltage of 13uVrms at

room temperature, if measured over a bandwidth of 10kHz. This is called
the Johnson Noise.
Whenever you mention a noise voltage or current, you also have to
state the bandwidth. To avoid this, noise voltage is often expressed in
nV/rtHz (nanovolts per root-Hertz). To get the real noise voltage you
simply multiply this value with the square-root of the bandwidth.

These two noise sources are fundamental, present in any current or

resistor. But there is another one, not fundamental exactly, but always
present. It is called 1/f noise or flicker noise.
Flicker noise is worst in an MOS transistor, which is a major reason
why bipolar transistors are preferred in analog design. The silicon-oxide
interface is capable of holding some electrons for a considerable period
(seconds) and then releasing them in bunches. This increases noise at low
frequencies far above the white-noise level; at 1Hz the noise level (in
nV/rtHz) can be two orders of magnitude higher than at 1MHz.
Flicker noise is also present in bipolar devices, but to a lesser extent.
Fourier Analysis, Distortion

Jean Fourier was a mathematician who was active in the French
revolution. He was arrested twice in the fight between the various factions
but was spared the guillotine. In 1798 he joined Napoleon's army in the
invasion of Egypt and then was appointed prefect in Grenoble; in 1809
Napoleon made him a baron.
In between his political and administrative duties he found time to
not only publish a massive work on ancient Egypt but do mathematical
research. He analyzed the flow of heat in mathematical terms, coming up
with a novel expansion of functions as trigonometrical series. His memoir
"On the Propagation of Heat in Solid Bodies" was read to the Paris Institute
in 1807. His method, now called the Fourier series, was criticized by the
leading French mathematicians and was not published until 1822 (and not
translated into English until 54 years later). It turned out to have
applications in a wide range of areas,
400 including now electronics.
200
When a sine-wave is distorted
other, higher frequencies are created
D1-anode / mV
0
which can be extracted in a Fourier series.
-200 There is an algorithm called "Fast
-400
Fourier Transform", or FFT, which does
this. FFT uses an algorithm which allows
0 20 40
fewer computations compared to the
60 80 100 120 140 160 180
Fig. 6-2: Distorted sine-wave.

original discrete Fourier transform.
In our example here the positive half of a 5kHz sine-wave has been
compressed. Converted into a frequency spectrum with the help of a
Fourier transform we see the fundamental frequency of 5kHz and a series of

harmonics, multiples of the

fundamental at 10kHz (second 1
harmonic), 15kHz (third 100m
harmonic), 20kHz (fourth

harmonic), 25kHz (fifth harmonic) 10m
Amplitude / V
etc., with gradually decreasing 1m
amplitudes. The square-root of the

sum of the squares of all harmonics 100µ
divided by the amplitude of the 10µ
fundamental is the amount of

1µ 0
distortion. You can usually 5 10 15 20 25
Frequency/kHertz 5kHertz/div
disregard harmonics after the
fourth or fifth, since their Fig. 6-3: Fast Fourier transform with low
resolution.
amplitudes become very small:
Harmonics = 36mV 2 + 21mV 2 + 8.2mV 2 + 0.9mV 2 = 42.5mV
Fundamental = 550mV
42.4
Distortion = = 0.077 = 7.7%
550
The peak at zero frequency shows the DC level, i.e. the asymmetry
caused by the clipping.
Before you run a fast Fourier transform in Spice you need to choose
two settings: how many samples should be taken over one period of the
waveform and how many periods should be analyzed. In the example of
Figure 6-3 there are in fact too few samples and periods, resulting in broad
peaks.
As a general rule start with 25 samples and 50 periods. The first is
determined by "maximum time-step" and "maximum print step" (set at
8usec in figure 6-4 for a 5kHz driving frequency) and the second by the
total time in the transient analysis (1msec for 50 periods at 5kHz). You get
the best results if both the number of samples per period and the number of
periods are integers.
The fast Fourier transform has some flaws and limitations. For
example, figure 6-4 shows peaks in between the harmonics, which, in

1 1
100m
100m
10m
10m
1m
Amplitude / V
Amplitude / V
100µ
1m
10µ
100µ
1µ
10µ 100n
10n
1µ0 5 10 15 20 25
1n 0 5 10 15 20 25
Fig. 6-4: Fast Fourier transform showing Fig. 6-5: Continuous Fourier transform
false peaks because of still insufficient with high resolution.
resolution.
reality are not there. A superior method is the Continuous Fourier
Transform, available in some analysis programs and shown in figure 6-5.
When you have a waveform which is symmetrical but not a sine-
1 1
0.8
400m
0.6
200m
0.4
100m
Amplitude / V
Amplitude / V
0.2
40m
-0
20m
-0.2
10m
-0.4
-0.6 4m
-0.8 2m
-10 1m 1 2 3 4 5 6 7 8 9 10
0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2
Time/mSecs 200µSecs/div Frequency/kHertz 1kHertz/div
Fig. 6-6: Triangle wave. Fig. 6-7: Fourier analysis of a triangle.

wave, you get only odd harmonics (i.e. the third, fifth, seventh etc.). Shown
here is the example of a triangular wave. Total distortion (i.e. deviation
from a sine-wave) is 12%.
When you have non-linearity in a circuit and two frequencies are
present, you also get intermodulation distortion, i.e. not only harmonics
are created, but differences as well.

Frequency Compensation
Feedback is a wonderful thing. We take the inverted output signal,
subtract the input signal from it and the amplifier will automatically correct
and difference between them. If we only feed back a fraction of the output
signal, the amplifier will automatically adjust its gain to one over that
fraction.
Using a single frequency (any frequency), inverting a signal
(negative feedback) is the same as a 180 degree phase-shift. And here
comes the problem: Each device in the amplifier has a little bit of delay. At
low frequency this has little effect, but as we go higher and higher in
frequency the delay becomes more and more noticeable. At some high
frequency the delay amounts to half a period of the signal and thus causes a
phase-shift of 180 degrees. What started out as negative feedback now
becomes positive feedback and the whole thing oscillates.
Frequency compensation is a design method which avoids this. The
principle is very simple: deliberately slow down one device so that it is
much slower than all others, i.e. it dominates the frequency response so that
the delay in all other devices is no longer important.
Feedback This is illustrated with a very
E1 simple simulation. E1 is a "voltage-
R1
In
100k
Out controlled voltage source" and acts like
C1
an ideal op-amp with a gain of 1 million
1Meg
Vin
10n (120dB), has no delay and the input and
output terminals are free-floating (but
are referenced here to ground). R1 and
Fig. 6-8: Abstract circuit to illustrate
phase-shift in a feedback amplifier.
Y2 Y1
C1 cause the single delay (i.e.

phase-shift). 160 160
Phase
Due to the RC network 140 140
Gain
120 120
the amplitude at the output starts
Phase / deg
Gain / dB
100 100
decreasing at about 100Hz. At Pole
80 80
this point the phase of the signal 60 60
at the output is considerably less 40 40
than 180 degrees, but as we go 20 20
higher in frequency the phase 0 01 10 100 1k 10k 100k 1M 10M

never goes below 90 degrees. Frequency / Hertz
Thus the signal being fed back to

Fig. 6-9: Single-pole response. The
the input cannot reach a phase-shift phase never goes below 90 degrees.
of zero degrees, the condition for

oscillation.
The point at which the phase has turned by 45 degrees is called a
pole. At frequencies somewhat higher than the pole the amplitude drops by
6dB per octave (doubling of frequency) or 20dB per decade.
Now let's look at the same
simulation with another RC Y2 Y1
network added at the output, with a 180

Phase
180
160 160
pole at a much higher frequency (C 140
Pole 1
140
= 100pF). We now have two 120

Gain
120
Pole 2
poles; you can just barely see the
Phase / deg
100 100
Gain / dB
second pole (at about 10kHz) by 80 80
60 60
the change in the steepness of the 40 40
gain curve. The maximum phase- 20 20
shift now is 180 degrees. The 0 0
point of interest is the frequency at -20 -20 1 10 100 1k 10k 100k 1M 10M
which the gain moves through zero Frequency / Hertz
dB (i.e. a gain of 1). If the gain is Fig. 6-10: Two poles in a feedback path
less than 1 an oscillation cannot approach zero degrees phase-shift.
sustain itself. While the phase at
this point only approaches zero degrees, the margin is far too close for
comfort.
Y2 Y1 With three poles we are
180 180
160 160
Phase clearly out of luck. The phase
140 140 now reaches zero degrees a
120 120
Gain
decade before the gain drops
Phase / deg
100 100
below 0 dB. An amplifier which
Gain / dB
Oscillation
80 80
60 60
has these three poles will
40 40 oscillate, in fact we can tell with
20 20 certainty that it will oscillate at
0 0
200kHz.
-20 -20 1 10 100 1k 10k 100k 1M 10M
There are now three
Frequency / Hertz
remedies: 1. we can lower the
Fig. 6-11: Three poles in a feedback path. gain until it drops below 0dB
Phase-shift goes through zero degrees and before the phase reaches zero
oscillation takes place.
degrees; 2. we can insert a new
pole at a frequency so low that it
dominates the others and 3. you can introduce a zero.
To illustrate the effect of a zero, we use another artificial circuit.
R1/C1, R2/C2 and R3/C3 provide the three poles, delaying the phase of the
signal, each by the same amount as in figure 6-11. R4, together with C2
provides the zero, it advances the phase rather than retarding it. The

frequency (i.e. the value of R4)

Pole E1 Pole E2 Pole
R1
100k
R2
100k
R3
100k
is selected to result in a
C1
10n
1k
C2
100p 1k
C3
frequency where it is most
V1 Zero R4
1p
effective.
20k
At about 30kHz R4/C2
Fig. 6-12: Three poles and a zero. start turning back the phase, so
that at the critical frequency
(5MHz) the gain drops
below 0dB but the phase is Y2 Y1
still positive, about 15 160 160

Phase
degrees, called the phase 140 140

margin. Theoretically a 120 120
feedback circuit with this Gain
Phase / deg
100 100
Gain / dB
behavior will not oscillate, Zero
80 80
though the phase margin is 60 60
rather low. Since gain and 40 40
time constants are subject 20 20
to variation in an IC, it 0 0
should be at least 60 -20 -20 1 10 100 1k 10k 100k 1M 10M
degrees. Frequency / Hertz

Now let's look at a
real design, a simple, bipolar Fig. 6-13: A zero retards the phase-shift.
op-amp; this rather outdated
+V circuit was chosen because it uses
Q3 the slow lateral PNP transistors,
Q4 C1 which aggravate the phase-shift
20p problem beautifully.
Q6
The circuit uses the
In+ Q1 Q2 In- Q5
classical 3-stage design for op-
Out
Vin I1
amps (more of this in chapter 8):
Q7 Q8
50u
an input stage which converts the
I2
Q9 differential input signal to a single-
50u
SUB ended one and has gain, a second
-V
C2
stage (Q4) which provides more
L1
1Meg
gain, and an output stage which
1
has no (voltage) gain but provides
V1
a reasonably high output current.
Since high-current PNP transistors
Fig. 6-14: Measuring gain and phase in a
are often not available in an IC,
feedback loop. the lower portion of the output
stage uses a compound transistor;

from the second stage it looks like a PNP transistor, from the output like an
NPN one (but the combined device is achingly slow).
Q5 and Q7 are diode-connected transistors to bias Q6 and Q8.
The amplifier is investigated as a buffer, i.e. with a gain of one,
produced by connecting the output directly to the inverting input. Here,
though, there is an inductor in the path, which blocks AC but lets DC
through so that the circuit is properly biased. C2, a very large capacitor,
couples an AC signal to the negative input. In this way the feedback loop is
opened up and we can measure loop gain and phase. This can be done at
any convenient point in the loop, but the output to input connection is
clearly the most convenient. Note that L1 and C2 have impractically large
values. This is of no great consequence since these components are not
going to be part on the design; we want to make sure they don't influence
the AC behavior of the circuit.
We feed the AC signal into the loop after the inductor and then
measure the loop response before the inductor (at "Out").
First let's look at the loop without C1. The loop gain is about 92dB
and the phase drops rather sharply, reaching zero degrees long before the
gain reaches 0dB. (Gain
and phase have identical Y2 Y1
scales for easier reading). 160 160

Phase
In fact, when the phase 140 140

reaches zero degrees, the 120 120
gain is still about 42dB.
dbV @ Out / dB
Phase / deg
100 100
Therefore this circuit is 80 80
Gain
unstable, it will oscillate. 60 60
C1, the 40 40
compensation capacitor, 20 20
has been placed at the most 0 0
strategic point in the circuit. -20 100 1k 10k 100k 1M
There is considerable Frequency / Hertz
voltage gain between the

Fig. 6-15: Loop gain and phase of figure 6-14 without
base of Q4 and the C1. The circuit would undoubtedly oscillate, the phase
output, which multiplies reaches zero degrees while there is still gain.
its apparent value (the
Miller effect). Without this multiplication we would need a capacitor of
about 2000pF, too large for an IC. It is also important that the capacitor
feed back the AC signal from a reasonably low impedance (here the output)
to a very high one (the current mirror and the base of Q4) so that we get
nearly the full AC voltage swing at this point.

The result is self-evident. A new pole is created, about 100 times lower in
frequency than the next higher one. This pole now dominates up to at least
10MHz and the phase is still 65 degrees away from zero when the gain
drops below one. A stable circuit with an adequate safety margin.
Of course there is a
Y2 Y1
price to be paid for this
stability: the gain of the op-
160 160
Phase
amp may be more than
140 140 90dB at 10Hz, but it drops
Phase Margin
120 120
65 degrees steadily as the operating
100 100 frequency is increased. If
Phase / deg
Gain / dB
80 80
Gain we use this op-amp at
60 60 10kHz, we only have about
40 40
58dB of gain.
20 20
This analysis has
0 0
assumed that the op-amp is
-20 10 100 1k 10k 100k 1M 10M 100M going to be used with a
Frequency / Hertz gain of one. But if you are
Fig. 6-16: With C1 the circuit of figure 6-14 has a
creating a design with a
phase margin of 65 degrees, i.e. the gain drops fixed gain, say 40dB, there
through 0dB safely before the phase reaches 0. is no reason why it should
have to be stable at a gain
of one. Which makes frequency compensation much less demanding. Just
look at figure 6-15. Subtract 40dB from the gain curve (only the excess
gain counts) and the amplifier is almost stable, i.e. a much smaller
compensation capacitor is required.
The gain/phase analysis, as elegant and informative as it is, has a
serious flaw: it shows performance only at one particular operating point (it
is, after all, an AC analysis which does not disturb DC operating voltage
and currents). A real-life signal will change the DC operating point and the
loop gain and phase can change substantially.
Some simulators let you perform this AC analysis at different DC
operating points, but there is an easier way , one that is a surefire test for
stability. Get rid of the inductor and C2, close the feedback loop as
intended in the application and apply a square-wave at the input. The
square-wave should have fast edges (the default values in the simulator are
adequate).
Then observe the output and watch for overshoot. For this circuit,
with C1 at 20pF, there is a slight overshoot, one peak only. This circuit is
very stable. (You can also see that the large compensation capacitor affects
the slew-rate rather badly).

With the compensation capacitor reduced to 5pF there are three to

four peaks, a damped oscillation. Up to four peaks are acceptable. If there
are more, you are asking for trouble.
To make absolutely
sure, do this with a brief (10 600
run) Monte Carlo Analysis at 400

the temperature extremes and
also for a rapidly varying
Output Voltage / mV
200
load and supply voltage (less C1 = 20pF

-0
likely to cause instability, but
it doesn't take much time to -200
check). If there are never C1 = 5pF
more than four peaks, you are -400
safe.
-600
0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8
A final small hint: in Time/µSecs 200nSecs/div
a gain/phase analysis Fig. 6-17: To make sure a feedback circuit does

simulators often get confused not oscillate observe the pulse response. If there
about the phase. You will is ringing with fewer than 4 peaks, the circuit is
stable.
see a plot which starts not at
180 degrees, but at -180. The
two are in fact the same.

Camenzind: Designing Analog Chips Chapter 7: Bandgap References
7 Bandgap References
In February of 1964 David Hilbiber of Fairchild Semiconductor

presented a paper at the Solid State Circuits conference on "A New
Semiconductor Voltage Standard". Zener diodes were
I1 I2
50u 207.5u still very poor and he was looking for something that
Q1 drifted less over time.
Q2 Q11
It was already known that transistors with base
and collector connected together made almost ideal
Q3 Q12
diodes. Hilbiber took two of Fairchild's discrete
Q4 Q13 transistors with greatly different forward voltages (which
Q5 Q14
he attributed to different diffusion profiles) and made two
strings with different numbers of transistors. He found a
Q6 Q15
current level at which - over a narrow temperature range
Q7 Q16 (± 2.5oC) - the voltage difference between the two strings
Q8 Q17
changed little and amounted to 1.2567V. He attempted to
find a relationship between this voltage and the bandgap
Q9 Q18
potential of silicon at zero Kelvin, but found that it was
Q10 Q19 primarily a function of the semiconductor material used
in the two different transistors. He got what he was after,
a much better long-term stability, and stopped at that.
Fig. 7-1: The
ancestor (1964). Nothing happened for six years, when Bob Widlar
put in the missing pieces.
He recognized that the
difference in diffusion
profiles was only a
secondary effect and the
idea would work better if
the two transistors were
made by identical
processes.
If you plot the diode
voltage (VBE) over
temperature you will notice
that it points at the bandgap
Fig. 7-2: The principle of a bandgap reference.
potential at absolute zero.

This is not strictly a straight line; it is slightly convex below about 150oC
and concave above (it asymptotically approaches zero volts). The bandgap
voltage at zero K, by the way, is strictly a theoretical concept; at that
temperature there are no semiconductors, in fact electrons don't move at all.
Widlar found that an equal but opposite temperature coefficient can
be created by running transistors at different current densities:
k∗T  A1∗ I 2 
deltaVBE = ∗ ln  
q  A2∗ I1
where A is the area (effective emitter area) of each transistor and I the
current running through it. Here you have the choice of either using
different emitter sizes, different current levels or both at the same time.
Delta-VBE is a true straight line, pointing to zero at zero K. But it is
relatively small. kT/q amounts to about 26mV at room temperature, so an
area (or current) ratio of 10 gives you a delta-VBE of about 60mV. As you
can see from the diagram in figure 7-2 you need about 600mV at room
temperature so it counteracts VBE.
But Widlar came up with a simple Vcc
solution: multiply delta-VBE with a resistor ratio. I1
R1 creates a current in Q1. Q2 has ten times the 150u
emitter area of Q1, so there is a delta-VBE Vref

R1 R3
between the two transistors of about 60mV (at 25k 25k
room temperature). This delta-VBE shows up
across R2. Ignoring a small error due to the base Q3
current, emitter and collector currents of Q2 are Q2

equal. Thus the voltage drop across R3 is delta- 10
Q1
VBE multiplied by the ratio of R3/R2. Adding to R2
SUB
2.25k
this voltage the VBE of Q3 we get Vref.
The three transistor form a feedback Fig. 7-3: Widlar's first
loop (with limited gain, thus the internal bandgap reference.
capacitances are sufficient to keep it from
oscillating), holding Vref at a constant level. If we increase the value of R3,
Vref increases and the temperature coefficient becomes more positive. If
we decrease R3, the opposite happens. In this way we can find the right
value for R3 so that the negative temperature coefficient of the VBE is
cancelled by the positive one of delta-VBE.
Widlar's first design was a bit more complicated, using 14 transistors
and producing 5 Volts with four VBEs in series and the delta-VBE
multiplied by a factor of about 40. It is no longer used.

There is no such thing as an absolutely precise bandgap voltage.

You will find that the voltage at which Vref has no temperature coefficient
can be anywhere between about 1.18V and 1.25V due to several effects.
First, the bandgap voltage is slightly dependent on the doping level.
Second, the bandgap potential of a semiconductor changes with pressure (or
stress). And third, we are using (presumably) diffused resistors which have
a temperature coefficient of their own. Fourth, as pointed out before, VBE
vs. temperature is not an exact straight line; thus Vref vs. temperature will
always show a slight upward bow.
Nevertheless, such a bandgap reference voltage can have an
accuracy of better than ± 3%, without trimming any of the components.
Apart from base currents (which can be compensated in more
advanced designs) there are two main sources of error in a bandgap
reference:
1) The VBE. This is an absolute, not a ratio. You have to rely on
the precision with which dopants can be introduced into silicon in the
process. In a well-controlled process this amounts to about ± 10mV
uncertainty, or about 0.8%. Be aware that prototypes from a single wafer
(or even a single run) will not give you any indication how much this varies
in production over many wafers.
2) Ratios. In Widlar's first bandgap reference there are two ratios of
significance: Q1/Q2 and R3/R2 (and also R1/R3). To minimize these errors
you simply make these devices large.
Vcc Four years after Widlar, Paul Brokaw

R3
30k
Q3 published a paper entitled "A simple Three-
Terminal IC Bandgap Reference". The core of
Q4
Q7 the "Brokaw Cell" is formed by Q1, Q2, Q3,
Q2 Q1
Vref Q4, R1 and R2. (His actual circuit contained
Q5
10
14 transistors, so it wasn't so simple after all).
R1
1.5k The Brokaw cell needs a start-up
Q6
circuit, which has been added here (Q7 lifts
R2
6.9k Vref to one VBE, which is sufficient for Q1
SUB and Q2 to start drawing current).
Q2 has 10 times as many emitters as
Fig. 7-4: The Brokaw cell.
Q1 (an arbitrary choice, more would be better),
so there is a delta-VBE of 60mV (at room temperature) across R1. Q3 is a
current mirror, forcing Q1 and Q2 to run at the same current. Q4 completes
the feedback loop from the collector of Q1 back to the input bias of the
differential pair Q1/Q2 and supplies a moderate amount of output current.

When the circuit is in balance a multiplied delta-VBE shows up

across R2. Thus Vref is that voltage plus the VBE of Q1. The value of R2
is selected to achieve a zero temperature coefficient for Vref.
The gain in the feedback loop is limited, which eliminates the need
for extra frequency compensation capacitors but results in a relatively high
output impedance (about 80 Ohms). Because of the emitter-follower output
transistor (Q4), the minimum supply voltage is 2.2V (0 to 100oC), or about
1 Volts above Vref.
Vcc
Figure 7-5 shows a
modification of the Brokaw cell Q3
R4
for operation at low supply 30k Q4
voltage. Output current is now
supplied by Q6, a somewhat Q7
Q6
Vref
Q2 Q1 Q5
larger than normal lateral PNP
transistor, capable of delivering 10
470n
5mA. Q4 forms an additional Q8 R1
3k
C1ext.
Rload
gain stage, lowering the output R3 20
impedance to 9 Ohms. Note that Q9 R2
14.8k
14.8k R1ext.
the operating current for Q4 is SUB

carefully set by Q5 and R3, with
R3 having the same value as R2. Fig. 7-5: Three terminal Brokaw reference
In this way the base currents of with start-up.
Q3 and Q4 cancel (and, in
addition, Q1 and Q2 have identical collector voltages). The minimum
supply voltage is now 1.6 Volts.
The design procedure for such a bandgap reference is very simple.
First you set the emitter ratio of Q2/Q1. The two devices should have
identical emitters for best matching, Q2 just has more of them. Make the
ratio as high as you can; with a ratio of 2:1 you get a delta-VBE of only
about 18mV, which puts a strain on the matching. At 10:1 the delta-VBE is
about 60mV (again: at room temperature) and the matching requirements is
less severe. At 50:1 the delta-VBE amounts to about 100mV at which point
matching becomes easy (you also have a large number of emitters which,
statistically improves matching).
With the emitter ratio chosen, you now know the value of delta-
VBE appearing across R1. You then set R2 so it drops about 600mV; in
this particular case twice the current flows through R2 as flows through R1,
so a 5:1 resistor ratio will give you 10:1 voltage ratio.
Next comes the simulation, and for this you need good models,
including the temperature coefficient of the resistors. Plotting Vref against
temperature, you will almost certainly see a marked temperature coefficient.

Now simply change the value of R2 until this temperature coefficient is

zero, end to end. A higher value for R2 will give you a more positive
tempco.
Ideally, R1 and R2 should have a ratio so that you can divide them
into identical sections in the layout. In this example 3k/15k would be
perfect, breaking the divider into six identical sections of 3kOhms each. In
reality this rarely happens. You may find that, by changing the value of R1
(thus drawing more or less current) you can get to this ideal ratio, but if you
don't there is a compromise: Use a smaller basic section (say 750 Ohms)
and then get the odd value of R2 by making the last section (or perhaps the
last few sections) a combination of parallel and series connections of the
basic resistor element.
Vref shows the
1.2348
1.2346
characteristic bow of a bandgap
1.2344 reference, due to the slight
1.2342
1.234 curvature of VBE. This amounts
Vref / V
1.2338
1.2336
to about 0.18%.
1.2334
1.2332
This curve was obtained
1.233 using models for a simple 5-Volt
1.2328
1.2326
0 20 40
bipolar process. The results are
60 80
Temperature/Centigrade
going to be different for other
20Centigrade/div
processes, you will need to find

Fig. 7-6: Characteristic bow in the the optimum value for R2 using
temperature curve of a bandgap reference. your own models. Also, the
final value for Vref will most
likely be somewhat different too.
When you plot Vref vs. 1.27
temperature from a simulation you
get a false sense of precision. You 1.26
will see the curve of figure 7-6

1.25
only once in a while on a real IC,
Vref / V
one that happens to have the exact 1.24
nominal parameters. What you

1.23
have to live with is more like
figure 7-7, obtained from a Monte 1.22
Carlo run. Over a range from 0 to

100oC the variation is about ± 1.21 0 20 40 60 80
2.5%. This can be reduced by Temperature/Centigrade 20Centigrade/div
trimming and the best component

Fig. 7-7: In production (Monte Carlo
to trim is R2. As you can see there analysis) you will see a larger deviation
is a distinct relationship between than merely the curvature.

voltage and temperature coefficient. R2 controls both.

Even with trimming, there is a limit to accuracy. When a chip is
attached to a lead-frame in a package, there is always some stress. Stress
changes the bandgap potential and, unless some unusual precautions are
taken, Vref can change as much as 0.5% (in either direction) compared to
the value measured (or trimmed to) on
1.244 the wafer. This can of course be
1.242
avoided if the reference can be
1.24
trimmed in the package.
1.238
Vref / V
1.236
-30
1.234
-35
1.232
1.23 -40
dbV @ Vref / dB
1.228
-45
1.226
0 20 40 60 80 100 120 140 160 180
-50
-55
Fig. 7-8: Pulse response, indicating -60

stability.
1k 2k 4k 10k 20k 40k 100k 200k 400k 1M
The use of a PNP transistor Frequency / Hertz
at the output makes frequency Fig. 7-9: Power supply rejection.

compensation of a feedback loop
difficult. This is true especially for
a slow lateral one. About the only practical way to compensate this
reference is to place a large (i.e. external) capacitor at the output. Even so a
small resistor in series with the capacitor is Vcc
required to create a zero (see chapter 6). I1
50u
The loop is stable but the power supply
rejection at 100kHz is a mere -30dB. Vref
Q3
R1 Q4
24k
It's Widlar's turn again. Four years C1
after Brokaw he came up with a whole series 10p

R2
of new bandgap reference designs. Figure 3k
Q1 Q2 Q5
7-10 shows one of them. Q1 and Q2 have a R3
26k 4
4:1 emitter ratio (just to show some variety) Q7
and their emitters are connected together. Q6 Q8

SUB
So the delta-VBE shows up between their
bases, i.e. across R2. This amounts to:
Fig. 7-10: Another Widlar
deltaVBE = ln4*26mV = 36mV bandgap reference.

at room temperature. Since there is only one current flowing through all
three resistors (save the base currents of Q1 and Q2) the voltage drop across
all of them is 36mV(53k/3k) or 636mV.
1.2
Add the 600mV VBE of the diode-
1.1
connected Q6 to this and you get a
0C temperature compensated reference
1
voltage of 1.236V. (Again, this value
Vref / V
0.9
100C and the required values for R1 or R3
0.8
may be somewhat different for other
0.7
processes).
0.6
The multiplying resistor as been
0 10 split into two parts (R1 and R3) to
20 30 40 50
I1/µA
provide enough headroom for the
10µA/div
Fig. 7-11: Minimum operating current. transistors to operate. The operating

current for the differential stage (Q1,
Q2) and the second stage (Q4) is 1.237
reduced by making Q6 three times as 1.2365
large as Q7 and Q8.

1.236
This reference requires a
Vref / V
minimum current of 25uA to operate 1.2355
properly. Above that level the 1.235
impedance at the output is about 10 0.15 Percent

1.2345
Ohms. Frequency compensation is 1.234 0 20 40 60 80 100

easily accomplished by enhancing the Temperature/Centigrade 20Centigrade/div
Miller capacitance of the slowest device,

Q4, with a 10pF capacitor. Fig. 7-12: Deviation over
temperature (the bow.)
Let's look at the variation again.
Once R1 (or R3) is optimized for near-
1.28
zero change at the temperature
1.27
extremes, we get the inevitable bow.
1.26
For this reference it amounts to 0.15%.
1.25
Nominal When we put this bow in
Vref / V
1.24 context, namely add to it the production

1.23 variations due to the absolute value of
1.22 the VBE and the matching variations of
1.21 the resistors and transistors, we get quite
1.2 0 20
a different picture. The 0.15% bow is
40 60 80 100
Temperature/Centigrade overwhelmed by the ± 3% overall

20Centigrade/div
variation. (The variation, however, can

Fig. 7-13: Again the bow is a minor be reduced to perhaps ± 2.3% by
factor in the overall variation. choosing a larger emitter ratio).

At the same time Widlar Vcc
introduced his new designs he also I1

50u
came up with a way to reduce the
bow, a method which is now called R1
Vref
second-order temperature 14.175k Q3

Q4
compensation. Q9
R2
C1
To illustrate it we use the same 8.85k

10p
bandgap reference again, with one R5
R3
3k
transistor added. A portion of the 75k
R4
Q1 Q2 Q5
voltage across the resistor string is 25.875k 4
tapped by the base-emitter diode of Q7

Q6 Q8
Q9 with a large-value resistor. The SUB
tapped voltage has a positive
Fig. 7-14: Bandgap reference with
1.223 curvature correction.
temperature coefficient, the base-
1.2228
emitter diode a negative one. At about
1.2226
40oC Q9 and R5 start feeding a small
Vref / V
current into Q6, which increases as the

1.2224 temperature is increased. This bends
the right-hand side of the
1.2222
characteristic bow upward. R1, R2
1.2220 20 40 60 80 100
and R4 then need to be adjusted to
Temperature/Centigrade 20Centigrade/div
level the curve, a somewhat delicate
Fig. 7-15: The bow reduced by second- 1.25

order temperature compensation.
1.24
process. The net result (after 1.23

Vref / V
several adjustment cycles) is a

1.22
flatter curve, showing a deviation
of just 0.04%. 1.21
But let's put this in context 1.2
again. We may have straightened Nominal

0 20 40 60 80
the nominal curve, but it is still Temperature/Centigrade 20Centigrade/div
subject to the variations caused by

VBE and matching. Adding this
Fig. 7-16: The overall variation now
(Figure 7-16) we see little or no overwhelms the remaining bow, so this
improvement in overall accuracy. approach should only be used with trimming.
For this reason second-order
curvature correction only makes sense if a bandgap reference is trimmed in

a very sophisticated way, reducing production variation to considerably less

than 1%.
Vcc Here is a more modern bandgap reference

R3
25k
which is more accurate (without trimming) than the
previous examples. Just 4 transistors are used, one
Vref
with a dual base/emitter. It is basically a two-
Q2
terminal reference, fed by R3. There are two
C1
R1
VBEs in series, so the output voltage is twice the
10p
40.5k bandgap potential, 2.45V. With R3 = 25kOhm the
optimum Vcc range is 4.5 to 5.5V.
Q4a
R2
3k
The delta-VBE appears across R2, given by
Q4b
Q3 the 24:1 emitter ratio of Q3 to Q1 (about 83mV at
24
room temperature) and is multiplied by R1 to about
Q1
SUB
1.2 Volts. The difference here is the placement of
R2 in the collector circuit of Q1, thus subtracting
rather than adding the delta-VBE. One VBE is that
Fig. 7-17: A different of the lateral (split-collector) PNP transistor Q2, the
design for a bandgap other the NPN transistor Q1. Lateral PNP
reference (2.5V).
transistors generally have a narrower variation in
VBE, but work only over a limited current range.
The error signal is picked up by a Darlington transistor (Q4, one
collector region, two base-emitter patterns).
Variation in production over a temperature range of 0 to 100oC is a
mere ± 1.6%. As always, the values given here are for a specific process,
with fairly large dimensions (the resistors are 4um wide). You may need to
adjust R1 for other processes (and certainly for other emitter ratios).
The circuit is stable with a load capacitance of less than 50pF or
greater than 200nF. With a 330nF capacitor at Vref power supply rejection
is -60dB, increasing further above 10kHz. The output impedance is 25
Ohms. The circuit is intended as a reference only, but it can sink several
milliamperes. If more sourcing current is needed, you simply decrease the
value of R3.
It is possible to modify this circuit for 1.2 Volts but, as a
consequence the performance suffers a bit (which is almost always true
when you move to lower voltages).
In figure 7-18 only a single diode-connected transistor (Q1) is used.
A second one mirrors one-third of the current, which is compared with the
mirrored current of Q4. Here the emitter ratio is 20:3. A second stage (Q5)
increases the loop gain, lowering the output impedance to about 1.7 Ohms.
R3 is optimized for operation from 3 to 3.6 Volts, consuming 90uA.

Production variation from 0 to Vcc
o
100 C is ± 2.2%. R3
22.5k
Frequency compensation is a
bit tricky. With a load capacitance of Vref
R1
500pF or less the circuit is stable and 42.75k Q3
has a power supply rejection of -80dB Q5
below 10kHz, -60db at 100kHz and a R2

5.25k
peak of -40dB at 1MHz. Q4

10p
C2
Figure 7-19 shows the same Q2 20
Q7
circuit, transformed into a 3-terminal Q1 Q6
reference, or a mini voltage regulator. SUB

It uses an NPN transistor to supply the
output current, which delivers a greater
Fig. 7-18: A similar circuit, but with a
current than a (lateral) PNP transistor single VBE (1.25V).
and makes frequency compensation an
easy job, but only works down
Vcc
Q9 to 2.2 Volts supply voltage.

Q6
The base current for the

Q7
output transistor is supplied by

Vref
C1
R1
43.5k
Q3 an independent current source
consisting of Q6, Q8, Q9 and
10p
R3 R2 Q10. This is the self-starting

Q5
1.1k 5.25k
Q10 Q4
current source discussed in
20 chapter 5, figure 5-12. The
Q8
R4
300
Q1 Q2
last transistor of the bandgap
reference, Q5, diverts the
SUB
unneeded current from Q6. Q6
supplies about 100uA. With a
Fig. 7-19: Three-terminal version of figure 7-18. maximum hFE of Q7 (at high
current) of 100, the output
current is limited to about
10mA (depending on the size of Q7), which prevent burn-out.
Production variation (3-sigma) over a temperature range from 0 to
100oC is ± 2.4%. The output impedance is 1.5 Ohms and the circuit is
stable with any load capacitance.
Low-Voltage Bandgap References

The principle followed in the bandgap references so far has been
this: add two circuit elements with equal but opposite temperature
coefficient, so that the sum of the two has a temperature coefficient of zero.

One of the circuit elements is a diode, which has a voltage drop of about
600mV. The second circuit element is a multiplied delta-VBE, which also
amounts to about 600mV. Therefore the minimum reference voltage
possible is about 1.2 Volts.
This is only true if we add these two voltages. There are other
approaches which avoid addition. Let's look at two of them.
Vcc Here is the ferment mind of Bob Widlar
I1 again. As early as 1978 he suggested a circuit
100u which works down to 1 Volt supply, a single
battery.
R1
9.75k
R5
800
First off he uses just about the largest
Q2
emitter ratio practical, 50:1 between Q2 and Q1.
Q1
50
This gives a delta-VBE of about 100mV at room
R2
Vref temperature.
50.25k R4
3.75k
The VBE appears at the base of Q1 to
ground. Thus the voltage at the entrance of the
R3
9.75k
current source is higher by a fraction of a VBE.
SUB Now assume R5 to be zero. Thus the voltage at
Vref is that fraction of a VBE plus the delta-VBE of
the 50:1 ratio in emitters of Q2 and Q1. If R1 is
Fig. 7-20: 200mV Vref
design by Widlar.
dimensioned such that the fraction of the VBE
amounts to about 100mV, then we have a
temperature-stable Vref of 200mV.
R5 provides some compensation for changes in I1 and connecting
R4 to a tap at R2/R3 rather than ground creates a minor amount of second
order temperature compensation.
A Vref of 200mV is just about the maximum value you can get from
this design. Even with a much larger emitter ratio, say 200:1, delta-VBE
only amounts to 138mV, i.e. Vref would be about 272mV.
The second approach is considerably more complex but has greater

flexibility. Two currents are created, one with a positive temperature
coefficient, the other with a negative one. Summed, they produce a voltage
drop in a resistor and this voltage drop has a near-zero temperature
coefficient.
The first current depends on the 3:1 emitter ratio of Q6 and Q4 and
the fact that Q4 runs at twice the current compared to Q6. Thus the
effective emitter ratio is 6:1 and the current is determined by the delta-VBE
(47mV at room temperature) and R1. The feedback loop has a gain of 3,
carefully controlled by the 3:1 emitter ratios of Q1/Q3, in this way the loop
is frequency-compensated by the device capacitances. The loop is self-

starting by leakage currents and the collector currents of Q2 and Q5 have a

positive temperature coefficient. Two identical currents are derived by Q7,
one feeding the Vcc
output resistor R3, Q2 Q5 Q11
the other starting Q7 Q12
the second current

Vref
source. Q3
Q9 Q10
Q1 C2
The
second current Q4 Q6 10p
depends on the R1
Q8
R2
R3
22.5k
VBE of Q8 and 7.65k 56k
SUB
the value of R2.
Again, the loop
has a limited Fig. 7-21: Bandgap reference with a minimum supply voltage of
and well- 0.9 Volts.
controlled gain
(the emitter ratio of Q10/Q9 and the 2:1 collector ratio at Q11/Q12), but a
small frequency compensation capacitor is still required. The collector
currents of Q11 and Q12 have a negative temperature coefficient and one
collector of Q12 feeds the output resistor R3. The sum of the two currents
flowing through R3 cause a voltage drop of 250mV, with a temperature
coefficient near zero.
The two currents can be adjusted independently with the values of
R1 and R2, allowing fine-tuning of the temperature coefficient. The
magnitude of the output voltage can be selected with the value of R3
without affecting the temperature coefficient.
Note that the currents depend on the resistor values. They will vary
in production but R3 tracks these variations and the output voltage depends
only on resistor matching.
The output impedance is that of R3. Unless the load draws only a
very small current you will need an output buffer.
This bandgap reference works down to 0.9 Volts supply and the
change in output voltage from 1 to 1.5V Vcc is 0.25%. Power supply
rejection is -55dB up to 10kHz. To keep this low at higher frequencies you
will need an external capacitor (10nF) at the output.
Production variation is ± 3.6% from 0 to 100oC, which illustrates
that the lower the supply voltage the more difficult it is to get high
performance, even if a more elaborate circuit is used.

CMOS Bandgap References

Let's face it: a bandgap reference is a bipolar concept. It needs a
diode and the difference between two diodes. And the only diodes good
enough are diode-connected bipolar transistors (or, in some designs, the
base-emitter diodes of bipolar transistors).
Fortunately there are some layers in a CMOS integrated circuit
which, although not intended for this purpose, can be used to make a
passable bipolar transistor. The most obvious ones are those used for a p-
channel transistor, the p-type region (source, drain) forming the emitter, the
surrounding n-well the base and the substrate the collector.
Such a device has limitations. First, the collector is permanently
tied to the lowest supply voltage. No flexibility there at all. Second the
gain (hFE) is very low, about 7. In a bipolar process we rely on the high
gain (at least 100) to effectively eliminate the base resistance as a source of
error. So the CMOS substrate PNP transistor only works if we make it
large (which we probably want to do anyway to get reasonable accuracy).
It is also possible to make lateral PNP transistors in CMOS, using
the p-channel drain/source diffusions as both the emitter and the collector.
Such devices have a reasonable gain (100 or so) but, unlike the substrate
devices, they are hardly ever characterized by the foundry, which means
you can't consider them unless you want to spring for a rather expensive
V+
evaluation run.
For this
M5 M8 M11
reason we will
W=1u W=1u W=1u consider only a
L=1u L=1u L=1u
M12 CMOS bandgap
M9
reference using
W=20u
L=0.5u substrate PNP
M6 W=20u
L=1u
transistors here. Q2
R2 24k
Vref has a single (10um
W=5u
L=1u M1 M2 24k R1 x 10um) emitter,
Q1 has 24 of them.
W=20u W=20u
L=1u L=1u 100n
Q2 is usually in the
R4
R3
Cext. center, surrounded
50k M10
M7
M3 M4
3.85k by 2 rows and
24X 1X
W=20u
W=0.4u L=1u
Q1 Q2 columns of
L=100u W=20u W=20u
L=1u L=1u
identical Q1
devices. Get used
to it: this pattern is
Fig. 7-22: CMOS bandgap reference with substrate diodes. very large

compared to a 0.12u, 0.18u or even 0.35u CMOS device.

The delta-VBE appears across R3, with R1 and R2 being equal. The
error voltage is amplified by M1, M2, M3, M4, M10 and M12. These
devices need to be as large as indicated. For M1, M2, M3 and M4 the
prime requirement is matching, which gradually improves as the area
(channel length times width) is increased. (Keep in mind that we are
working down at a level of a delta-VBE, which here amounts to about
82mV). For M10 and M12 the width needs to be substantial to get
sufficient gain (transconductance) and an increased length helps to reduce
the influence of power supply variations. To reduce this even more M9 (a
cascode stage) has been added.
M7, a narrow and very long transistor starts the circuit by feeding a
small current into the loop. Once sufficient voltage appears at Vref, M6 and
R4 take over and supply the operating current, mirrored by M5, M6 and
M11.
M12 is a p-channel transistor, which provides a low minimum
supply voltage (1.5V) but, as we have seen before, make frequency
compensation difficult. The only practical way to do this is with an external
capacitor, though placing it at the output also provides for a good power
supply rejection (-60dB). The output impedance is 0.5Ohms up to about
1mA.
With the transistor sizes as shown and the resistors 4um wide you
can expect a production variation of ± 1.8% over a temperature range from
0 to 100oC.
A word of caution: A bandgap reference is the ultimate test of

accuracy for device models. For example, it is very difficult to measure a
VBE over temperature accurately enough on a wafer so that it will predict
the behavior of a bandgap reference. With most processes you need to
make a bandgap reference to verify the models.

Camenzind: Designing Analog Chips Chapter 8: Operational Amplifiers
8 Operational Amplifiers
Op-amp design is a specialty, peopled by a small group of engineers

forever dedicated to the quest of finding the universal building block. None
has ever been found (hence the large number of different op-amps) but still
they toil. Year after year they come up with small improvements; and each
new design has one imperative requirement; it must work in any application
without creating smoke or - heaven forbid - oscillation.
When designing an op-amp for an ASIC the precise application is
known, so the circuit does not need to be universal and the task is easier.
Not exactly a cinch, but nothing compared to what a designer of
commercial op-amps has to face.
The majority of op-amps have three stages. The first stage converts
the differential signal into a single-ended one; the second one provides the
bulk on the gain and the third one the required output power. There is no
law that says it has to be this way, it just turned out to be an approach that
works well.
Bipolar Op-Amps
In our first circuit Q1 +V
and Q2 form the differential Q3

I1 Q4
pair and Q3, a split-collector 100u
C1
lateral PNP transistor, is In- In+
connected as a current mirror 10p Q5
or active load. At the Q1 Q2 Out
collectors of Q2 and Q3 we
Q7 Q8
have a high impedance, limited Q6 Q9
only by the base current of Q4
and the Early effects in Q2 and -V
Q3. The second stage, Q4, has Fig. 8-1: Simple 3-stage op-amp.
as a load the current sink Q8
and the base current of Q5, thus
its gain is also limited only by those two. The output stage is a simple
emitter follower with a pull-down current sink.

The operating currents for all three stages are derived from I1
through a multiple current mirror. Q9, with two emitters, delivers two times
I1, an arbitrary choice; more emitters could be used if more current is
required at the output for negative-going signals.
Q7 and Q8 are identical, which is no arbitrary choice. By making
the collector currents of Q4 and Q3 (both halves) equal, Q3 takes as much
base current from Q1 as Q4 does from Q2. Thus there is no designed-in
base current error and the offset at the input is zero (for ideal matching).
Common Mode Range: Describes the minimum to maximum DC level at which the
two inputs are functional. Desirable is rail-to-rail, i.e. from the negative supply to
the positive one, but many op-amps only work with the inputs a volt or two above -V
(or ground for a single supply) to some voltage below +V.
Common-Mode Rejection: If you connect both inputs together, bias them at a
functional DC level and superimpose on the bias a small AC voltage, no signal should
ideally appear at the output. In reality a small signal leaks through and the measure
describes how much smaller this signal is (in dB) compared to the input.
The common-mode range in this design has limitations. The two

inputs need a dc level of at least one VBE (Q1, Q2) plus a saturation
voltage (Q7) above -V. If they move below this level the input pair gets no
operating current. Also, the inputs need to be about 200mV below +V,
otherwise Q1 or Q2 saturate and Q3 or Q4 are without current. At the
output Q5 can pull the output only to within a VBE of +V.
There is also another flaw: being bases of bipolar transistors, the
inputs need a current. With a minimum hFE of 100 and 50uA flowing per
transistor, this amounts to base current of 0.5uA worst case. With a
100kOhm input resistance for one input and zero for the other this could
amount to as much as a 50mV error at the output.
Frequency compensation is achieved with a single capacitor from
the output to the high-impedance node at the output of the first stage. It
could have been placed just from collector
+V to the base of Q4, but the simulation shows
In+ +V 5 a small advantage for the shown
Fig. 8-1 Out
-V
configuration.
In- -V
Let's first double-check this
5
frequency compensation. To do this (as
C1 1Meg
explained in more detail in chapter 6) we
1 L1
place a very large inductor in the feedback
Vac
loop and feed an AC signal into the input
through a very large capacitor. The
Fig. 8-2: Simulating loop gain inductor (1MH, i.e. 1 million Henry)
and phase.
provides the DC bias to the input but blocks

the AC signal. You want to choose the inductor and capacitor large enough
so they have no effect at even the lowest frequency of interest for the
circuit. Neither 1 million Henrys nor 1 Farad are practical values; they
don't need to be.
And here is what we
Y2 Y1
get: The open-loop gain is 180
about 85dB. The dominant 160 160

Phase
pole, given by the 140 140
compensation capacitor, is at 120 120

100
about 2kHz, after which the
Phase / deg
100
Gain / dB
80 80
gain decreases steadily and 60
Gain
60
reaches unity (0dB) at about 40 40
12MHz. At that point the 20 20
phase is still at about 50 0 0
degrees, marginal but probably -20

100 1k 10k 100k 1M 10M 50M
adequate. Frequency / Hertz
But, as pointed out in Fig. 8-3: For stable operation the gain of a loop
chapter 6, a phase-margin must reach 0dB before the phase reaches 0
analysis is not the real test of degrees.
stability. AC analysis uses
infinitely small signals (even if it says the signal is 1 Volt) and the operating
currents and voltages are not disturbed. So, to be certain, we would have to
repeat this analysis for the DC conditions over the entire (large-signal)
range of the circuit, a tedious task at best.
We get a more immediate picture by
+V
Vin
In+
+V observing a large-signal pulse.
5
Fig. 8-1
-V
Out
To do this we eliminate the
In-
inductor and capacitor in the feedback
-V
0.8
Fig. 8-4: Buffer connection. 0.6
0.4
path and connect the signal to the 0.2
Output
input. Without resistors in the Input

V
-0
feedback path, this is a buffer -0.2
connection, i.e. a closed loop -0.4
-0.6
gain of one; with the entire open- -0.8
loop gain (85dB) being judged, -1

0 100 200 300 400 500 600 700 800 900
this is the most severe test for Time/nSecs 100nSecs/div
stability.
The output waveform Fig. 8-5: Input and output waveforms for the
buffer connection.
shows the amplifier to be very

stable, there is no ringing, just a small overshoot.

But the curve shows something else: rise and fall-times are
substantial and almost straight lines. This is the slew-rate, the time it takes
to charge and discharge the 10pF capacitor over a 2-Volt span with the
operating current. You can speed it up by increasing the operating current,
at the cost of power consumption.
In doing this test we assume that the op-amp needs to be operated as
a buffer. What if, in a specific application, the closed loop gain is never
lower than 40dB? In such a case we only have an excess open-loop gain of
about 45dB, which makes compensation considerably easier.
Let's examine this. In figure 8-6 we have the same circuit as in the
loop gain analysis before, except that the feedback resistors are in the loop
also.
Y2 Y1
+V
160 160
In+ +V 5
140 140
Fig. 8-1 Out Phase
-V 120 120
In- -V
Phase / deg
100 100
Gain / dB
5 80 80
1Meg 60 60
R2 R1
40 40
1K 99k L1 Gain
1
20 20
C1
0 0
-20 100 1k 10k 100k 1M 10M
Vac
Frequency / Hertz
Fig. 8-6: Simulation of loop gain and Fig. 8-7: With the lower gain the loop shows
phase with closed-loop gain of 100. greater phase margin, even though the
compensation capacitor (C1 in figure 8-1) is
reduced to 2pF.
1.5
The gain now shows a 45dB
maximum instead of 85dB and thus
1
drops to 0dB at a lower frequency. We
can now reduce the value of the
Output Voltage / V
0.5
0 compensation capacitor from 10pF to

-0.5
2pF and still have a phase margin of
-1
over 60 degrees.
When we check the stability
0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8
with a pulse (with only the resistors in
Time/µSecs 200nSecs/div
the feedback loop and the signal
Fig. 8-8: Pulse response with 40dB connected to the positive input) we see
loop gain and a 2pF compensation
capacitor.
that the amplifier is just stable enough
(fewer than 4 peaks in the damped

oscillation). And, because the compensation capacitor is smaller, the slew-

rate is substantially higher.
No consideration has been given so far to noise and noise
performance is in fact not that great in this design. The majority of the
noise is created in the input stage; in subsequent stages the signal is larger
and the influence of noise is
correspondingly reduced. To 200n
lower the noise in Q1 and Q2 the

devices need to be larger and 100n
their operating current higher.
Output Noise / V/rtHz

Figure 8-9 shows the 50n
I1 = 10uA
noise performance of this

amplifier in the buffer I1 = 100uA
configuration (since the gain is 1, 20n
output noise and input noise are

equal). As you can see, lowering 100 200 400 1k 2k 4k 10k 20k 40k 100k
the operating current increases Fig. 8-9: Noise

Frequency of the amplifier in the buffer
/ Hertz
noise, an unpleasant fact of life. connection.
Naturally you can invert

V+
Q7
Q8 Q9 the polarity of the transistors and
design an op-amp whose input
In+
can operate close to the negative
In-
Q1 Q2 Out supply (but loses its ability
C1
Q6 within about 1 Volt of the
I1 5p
positive supply). Figure 8-10 is
50u Q5
the PNP-input equivalent of
Q3 Q4
figure 8-1, still with a rather
SUB
V- primitive output stage (Q6, Q9),
which can pull the output to
Fig. 8-10: PNP-input equivalent of figure 8-1. within about 150mV of the
positive supply (if the load does
not require more than 50uA), but only down to about 1 Volt above the
negative rail.
Let's now consider a design in which the inputs can be operated all
the way down to the level of the negative rail and the output swings
(almost) rail-to-rail. The input stage in figure 8-11 is a configuration known
as the folded cascode stage. With an operating current (I1) of 10uA the
voltage drop across R1 and R2 is a mere 50mV, thus the inputs can go
about 250mV below the negative supply rail without saturating Q1 or Q2.

The collector currents of Q1 and Q2 upset the balance of the Wilson current
mirror Q3, Q4 and Q5 and the difference signal is picked up by Q6.
The output Q15 Q16
+V
stage has two Q17 Q10 Q13
branches to it. The

first one is simply Q11
Q14, a grounded Q6
Q7
C1
emitter amplifier. Q1 Q2
In-
Out
In+ 5p
All other transistors Q4
Q8
in this block serve
its antipode, Q13. I1
Q3 Q5
Q9
10u
Note the Q12
Q14
three diode R1
5k
R2
5k
R3
50k
connected SUB
-V
transistors Q7, Q8
Fig. 8-11: Op-amp with folded-cascode input stage and
and Q9. They set a (almost) rail-to-rail output.
voltage for the base
of Q11. If you follow the emitter-base junctions of Q11, Q12 and Q14, you
notice there are also three diodes in series to the V- rail. Thus, as the input
signal to the output stage moves up and down (by a few millivolts), the
current in Q11 fluctuates. It is this current, amplified by the size ratio of
Q13 to Q10 (here about 6) that becomes the pull-up portion at the output.
Q7 to Q9 are deliberately made larger than Q11, Q12 and Q14 so that the
idle current in the output is small. This creates a small "dead-band" (see
chapter 16) but, because of the large loop gain the distortion is very small
(0.0004% for a ± 4.7Vp signal at 1kHz).
In this circuit we are
Y2
180
Y1
180
fortunate to find a node ideally
160 160 suited for the connection of a
140 140 compensation capacitor to the
120 120
Phase output: at the base of Q6 the signal
Phase / deg
100 100
Gain / dB
80 80 has a phase opposite to that at the

Gain
60 60 output; the base of Q6 and the
40 40
collectors of Q4 and Q16 all
20 20
0 0
represent a high impedance; and
-20 -201 10 100 1k 10k 100k 1M 10M 100M there is substantial voltage gain
Frequency / Hertz between it and the output. Which
Fig. 8-12: Phase margin of figure 8-11. all says that this op-amp can be
compensated (at unity gain) with a
single 5pF capacitor, even though
the loop gain is 110dB. Not all designs behave that well.

Though the inputs can

work at the level of V- (or 4
ground if you have only a
single supply), the output 2
cannot. It is the sad truth for a
Out / V
bipolar transistor that there is a 0
saturation voltage. Unlike an

-2
MOS transistor, which is
simply a voltage-controlled
-4
resistor, the bipolar transistor is
0 0.2 0.4 0.6 0.8 1
the interaction of two junctions
with different doping levels
and sizes. Even when fully Figure 8-13: Output swing is limited by the
saturation voltages of Q13 and Q14.
turned on there is a minimum
voltage drop of about 150mV
between emitter and collector in transistors Q13 and Q14. Thus the output
can never be at the rails, only approach them.
The use of lateral PNP transistors at the input and the low operating
current is not kind to noise: 27nV/rtHz at 10kHz and up (white noise). At
1Hz the flicker noise rises to 80nV/rtHz. If you have vertical PNP
transistors at your disposal and can afford a higher operating current, these
figures drop by a large factor (but you need to carefully re-simulate the
entire circuit; frequency behavior is bound to be entirely different).
Another unsatisfactory parameter is the input current. Each input
transistor runs at 5uA; with a minimum hFE of 100 (in a good process) the
base current can be as high as 50nA. But there is a solution to this: more
transistors.
V+
Q17
Q15 Q16 Q10
Q18 Q13
Q11
Q23 Q7
Q1
In+ In-
Q6 C1
Q2 Out
Q22 Q8 5p
Q4
Q20
I1 Q19 Q21 Q24
10u
Q3 Q5 Q9
Q12 Q14
R1 R2 R3
Q25 Q26 5k 5k 50k
SUB
V-
Fig. 8-14: Op-amp of figure 8-11 with base-current compensation for the input stage.

In figure 8-14 eight transistors are added. Their job is to pull as

much current out of the bases of Q1 and Q2 as they naturally require, so
that he external circuit does not have to do this.
The key is Q22. It is identical in size and design to Q1 and Q2, has
the same operating current and very close to the same collector-base voltage
(created by the base-emitter voltage of Q23 and the diode-connected
transistor Q24). Thus its base current must be the same as those of the input
transistor. This base current is mirrored by Q21, Q20 and Q19 and fed to
the inputs, opposing the two base currents.
The cancellation of the base currents is never perfect of course, the
current levels are too small to get precision matching. But the net input
currents are down to 2nA, a 25:1 improvement.
In the last bipolar op-amp the goal is not an ultra-low input current,
but low-noise performance with a reasonably low input current.
Q18 V+
1 Q3 Q4
Q5
3
Q11 Q12
200u C1 Q6
I1
Q13
10 Q15 5p
In- Q1 Q2 In+ Out

10 10
Q16
Q8 Q14 Q9
Q7 Q10
SUB
V-
Fig. 8-15: Bipolar op-amp optimized for low noise.
This circuit is almost identical to that of figure 8-1. The input

transistors are now again NPN, but with the base-current canceling scheme
added. The key transistor is Q13; since the hFE of an NPN transistor
changes much less with current than that of a PNP device, we can afford to
run it at twice the current and then divide the base current by two in the
current mirrors Q12/Q11. This brings the input current down to 20nA.
The operating current is much higher than that of the previous
circuit and the input transistors are large, which lowers the white noise to
5nV/rtHz.

CMOS Op-Amps
CMOS devices have two advantages for op-amps over bipolar ones:
there is no input current (at least not at DC) and, when the transistor is fully
turned on, there is only a simple resistance between drain and source (not
some complex cancellation of two junctions, resulting in an offset voltage
and a resistance). M1 M3 M11 M13 M17
V+
Let's again
first look at a simple W=30u
L=5u
W=30u
L=5u
W=30u
L=5u
W=30u
L=5u
W=90u
L=5u
design. As in figure
M2 M4
8-11 a "folded M12 M14
cascode" input stage W=100u

L=2u
W=100u
L=2u W=100u W=100u
is used, this time In+

M5 M6
In-
L=2u L=2u
C1
using N-channel Out

1p
transistors (M5, W=40u

L=2u
W=40u
L=2u
20u
M6). The primary I1 M7 M9
current, I1, is W=100u W=100u
mirrored with M1- L=2u L=2u M18
M4 and then again M8 M10 M15 M16 W=50u

L=0.5u
in M7-M10, using
W=10u W=10u W=20u W=20u
the circuit of figure L=5u L=5u L=3u L=3u
3-24, so the V-
operating current Fig. 8-16: Op-amp with folded-cascode input stage and a
for the input pair is simple (and limited) output stage.
a constant 20uA.
The four transistors M1-M4 also steer M11/M12 and M13/14,
producing two more accurate currents of 20uA each. The drains of the
input transistors are connected to the sources of M12 and M14, which have
a potential about 200mV below V+; thus the inputs can operate up to (and
about 100mV above) the positive supply.
At balance (In+ = In-) the input pair diverts half of the 20uA current
produced in M11 and M13, i.e. M12 and M14 are left with only half the
current, about 10uA each. The current out of M12 is mirrored in M15/M16
and opposed to that flowing out of M14. With a large input signal the two
currents become unbalanced and each can vary between zero to 20uA. The
voltage created by this unbalance is amplified by the output stage (M18 and
a simple pull-up current source, M17). The idle current of the output stage
is set by the ratio of the channel widths of M1 to M17, i.e. 60uA.

The circuit is Y2 Y1
compensated with a single

150
1pF capacitor, utilizing the 80
Miller effect of M18. This 100 60

works well as long as the
Phase / deg
load capacitance is small. 40
Gain / dB
50
At 10pF the stability is 20

0 10pF Load
marginal when connected 0
as a buffer; if the closed- -50
loop gain is never lower -20
than 10 however, the op- -100

10 100 1k 10k 100k 1M 10M 100M
amp is very stable, even Frequency / Hertz
with a load capacitance as
Fig. 8-17: Phase margin becomes critical with a
high as 50pF. capacitive load, unless the closed-loop gain is
With a load resistance 40dB or larger.
of greater than 25kOhms
1.5
(60uA) the output can move rail-
to-rail (or, more precisely, to
1
within about 100mV of each rail).
0.5 All CMOS examples in
Output Voltage / V
0
this chapter assume a split power
supply of 3 Volts total, or ±1.5V;
-0.5
they are operational down to
-1 ±0.8V, though with reduced
-1.5 0
performance.
0.2 0.4 0.6 0.8 1
Time/mSecs
You need to be aware of
200µSecs/div
the changing open-loop gain. At

Fig. 8-18: Output swing. ground level it amounts to 100dB.
As the output moves close to
either supply there is a marked drop (66dB at -1.4V, 60dB at +1.4V). This
can be improved by making the output devices larger.
What cannot be improved is a fundamental dependence of loop gain
on the load impedance. The lower the load, the lower the loop gain.
The input stage has a limited common-mode range. It will work up
to about 100mV above the positive rail, but not below about -0.8V, i.e.
about 0.7V above the negative rail.
Let's convert the wimpy output stage into a true rail-to-rail one, with
some current capability:

V+
M1 M3 M11 M13 M21
W=15u W=15u W=15u W=15u W=20u

L=5u L=5u L=5u L=5u L=0.5u
M=2 M=2 M=2 M=2 M=2
M24
M22 W=10u
M2 M4 L=5u
M12 M14
W=20u
W=20u W=20u L=0.5u
L=2u L=2u W=20u W=20u M=2
M=5 M=5 L=2u L=2u M27
M=5 M=5
M9 M10 W=20u
In+ In-
1p L=0.5u
M19 M23 C1 M=15
W=20u W=20u
Out
L=5u L=5u
R1 M=5 M=5 W=100u W=100u 1p
20u 10k L=0.5u L=0.5u C2
I1 M29
M5 M7 M15 M17
W=10u
M25 L=0.5u
W=20u W=20u W=20u W=20u M=5
L=2u L=2u L=2u L=2u
M=5 M=5 M=5 M=5 W=20u
L=0.5u
M6 M8 M16 M18 M20 M26
W=20u W=20u W=10u W=10u W=20u W=20u

L=5u L=5u L=5u L=5u L=5u L=0.5u
M=5 M=5
V-
Fig. 8-18: Op-amp with a more capable rail-to-rail output stage.
The trick in designing a rail-to-rail output is in the biasing of the two output
transistors. You want a small but well-controlled idle current to minimize
any uneven behavior as the output signal is switched from one transistor to
the other. In this circuit there are eight transistors whose only job is to set
this idle current.
Follow M25 and M26, two "diode-connected" n-channel devices,
fed by the current source M24. At the gate of M23 we then have a DC
potential of about 1.2V above the negative rail. There is a second path from
this node to V-, through M23 and M29, also n-channel transistors. Thus the
current in M29, one of the output transistors, depends on the current
supplied by M24 (and derived from I1 through M1 and M2) and the channel
dimensions of M23, M25, M26 and M29. An identical arrangement is
provided for M27 by M19 to M22. With the dimensions shown the idle
current amounts to 70uA.

In this circuit we also have two higher-performance current mirrors:

M15 to M18 (see figure 3-24) to get the maximum open-loop gain and M5
to M8 (see figure 3-25) to get the highest possible common-mode rejection
(now 98dB, up from 94dB in figure 8-16).
The output stage is capable of supplying 1mA peak and can get
within 100mV of the rails with a 5kOhm load. This performance can be
increased by making M27 and M29 wider.
Though capable of a much higher current without wasting idle
power, this rail-to-rail output has the same weaknesses as the previous one:
it is very sensitive to capacitive load and the open-loop gain is
fundamentally related to the load
1.5
impedance. With no load it is
1 105dB; with a 100kOhm load the
0.5
open-loop gain drops to 101dB,
Output Voltage / V
with 10kOhm to 88dB and 1kOhm

0
it reaches a paltry 68dB. This,
-0.5
alas, is an unpleasant fact with
rail-to-rail outputs.
-1
Larger input transistors are
-1.5 0 0.2 0.4 0.6 0.8 1
also used in this circuit, which
reduces the white noise to
23nV/rtHz (28nV/rtHz in the
Fig 8-20: Output limits with 5kOhm load.
previous circuit).
In the next circuit (figure 8-21) the polarity of the input stage is
reversed and the current mirror for the second stage (M11 to M14) is
designed to have the highest possible output impedance, resulting in an
increased loop gain. Also note that the primary current has been
(arbitrarily) reduced to 5uA.
The lower operating current level has only a minor effect on the
sizes of most devices; they still need to be large to obtain satisfactory
matching, much larger than the process (0.35u, or the higher-voltage portion
of a 0.18u process) would allow. The idle current of the output stage is now
reduced to 10uA.
Open-loop gain is 107dB at low frequency and with no load.
Capacitive loading is still a problem (but much reduced if the minimum
closed-loop gain is higher than 1) and, as before, the closed loop gain is a
function of load impedance.
The input operating range now extends from about +0.8V to 150mV
below the negative rail. If a single supply is used the inputs can function at
or below ground level.

Because of the large dimensions used for the input transistors the
white noise level is a relatively low 21nV/rtHz. Note, however, that they
are run at twice the level of I1.
V+
M5 M7 M11 M13 M21 M24
W=15u W=15u W=20u W=20u W=15u W=4u

L=5u L=5u L=5u L=5u L=0.5u L=5u
M=2 M=5 M=5 M=10
M6 M8 M12 M14 M22
I1 W=20u W=20u W=20u W=20u W=15u

5u L=2u L=2u L=2u L=2u L=0.5u
M=2 M=5 M=5 M=10
M27
R1
C1
50k W=15u
1p L=0.5u
M9 M10 M19 M23 M=10
In+ In-
Out
C2
W=20u W=20u W=15u W=10u
L=3u L=3u L=0.5u L=0.5u 1p
M=10 M=10 M=10 M=5 M28
M1 M3 M15 M17 W=10u

M25 L=0.5u
M=5
W=10u W=10u W=20u W=20u
L=2u L=2u L=5u L=5u W=50u
M=5 M=5 L=0.5u
M20
M2 M4 M16 M18 W=1.5u M26

L=5u
W=5u W=5u W=5u W=5u W=50u

L=5u L=5u L=5u L=5u L=0.5u
V-
Fig. 8-21: Op-amp with P-channel input.
Now let's extend the operating range of the input by using both p-
channel and n-channel devices. In the circuit of figure 8-22 we are adding
an n-channel differential pair which takes over when the DC level at the
inputs reach about +0.8Volts and the p-channel devices get cut off. There
are three voltage regions for the input now: within 0.8 Volts of the negative
rail only the p-channel devices are active; from about -0.8 Volts to +0.8V at
the inputs, both pairs amplify and within 0.8V of the positive rail only the
N-channel devices amplify.
When both pairs are active, the open-loop gain is at a maximum,
reaching 120dB. When the common-mode level is either high or low, the

loop gain drops by 10dB. Many schemes have been offered in the literature
which hold this gain more constant (e.g. by allowing only one pair to
operate at a time), adding another dozen devices. For most applications the
benefits of this measure are limited; in fact simultaneous operation of both
pairs increases performance (noise, for example drops to 20nV/rtHz,
compared to 30nV/rtHz when only one pair is amplifying).
V+
M5 M7 M11 M13 M21 M24
W=15u W=15u W=20u W=20u W=15u W=4u

L=5u L=5u L=5u L=5u L=0.5u L=5u
M=2 M=5 M=5 M=10
M6 M8
M12 M14 M22
W=20u W=40u
L=2u L=2u W=20u W=20u W=15u
I1 M29 M30 L=2u L=2u L=0.5u
M=5 M=5 M=10 M27
5u
W=20u W=20u C1
L=3u L=3u W=15u
M=5 M=5 1p L=0.5u
M19 M23 M=10
M9 M10
In+ In- Out
W=15u W=10u C2
W=20u W=20u L=0.5u L=0.5u
L=3u L=3u M=10 M=5 M28
1p
M=10 M=10
M1 M3 M31 M15 M17 W=10u

M25 L=0.5u
M=5
W=10u W=10u W=20u W=20u W=20u
L=2u L=2u L=2u L=2u L=2u W=10u
M=5 M=5 L=0.5u
M=5
M20
M26
M2 M4 M32 M16 M18 W=1.5u
L=5u
W=10u
W=5u W=5u W=10u W=10u W=10u L=0.5u
L=5u L=5u L=5u L=5u L=5u M=5
V-
Fig. 8-22: Op-amp with rail-to-rail inputs and output.
The two input stages work with the second stage (M11 to M18) as
folded cascodes. The lower part of the second stage (M15 to M18) is a
current mirror derived from M1 to M4, set here at about 10uA; the upper
part (M11 to M14) mirrors the current again, so that at M19/M23 the
currents cancel if there is no input signal. M19 and M23 set the bias current
of the output transistors (M27, M28)

With an input signal one or both input stages change the currents in
the second stage, resulting in a net positive or negative current through
M19/M23, which is translated into a larger current at the output.
A common problem in op-amps using two separate input stages is
created by the random nature of the offset voltage. Suppose one pair has an
offset voltage of +5mV the other -5mV. As the signal moves from one
stage to the other, this causes a jump of 10mV, creating distortion.
Auto-Zero Op-Amps
Auto-zero or chopper stabilized amplifiers have been around for
decades but continue to evolve. In a modern embodiment two amplifiers
are used, checking up on each other.
Each amplifier has a "Trim" input, i.e. a single node which changes
its offset voltage in both directions.
A built-in oscillator flips the two switches periodically at a rate of a
few hundred to a few thousand Herz. In position A the inputs of amplifier 2
are shorted together and its own offset voltage is amplified (with the open-
loop gain) and corrected by feeding the output to the trim input. The
required trim voltage is stored in capacitor Ca.
In the second phase of the oscillator the inputs of amplifier 2 are
connected in parallel to those of amplifier 1 and its output now feeds the
Feedback trim input of amplifier 1. With the
charge remaining across Ca, amplifier 2
In+
In+ continues to be nulled and thus corrects
Amp. 1 Out Out
the offset of amplifier 1. As the
In- In- Trim
oscillator switches back to phase A this
correction voltage remains across
capacitor Cb. With the high open-loop
A B
In+ gains of both amplifiers the offset
Amp. 2 Out voltage is now reduced to microvolts.
In- Trim Since the correction is done repeatedly,
A B
temperature drift is also much reduced.
Ca Cb
There is an additional benefit.
Anything sensed by amplifier 2 below
the switching frequency is treated as an
Fig. 8-23: Auto-zero op-amp.
offset. This includes flicker (1/f) noise,
which is completely eliminated. Above the switching frequency the
behavior of the auto-zero amplifier is identical to a regular op-amp.

Apart from the higher current consumption because of the additional

circuitry there is one drawback: switching noise. At the switching
frequency there is a noise peak which also causes (intermodulation)
distortion. This effect can be ameliorated by changing the switching
frequency at random, i.e. creating a spread spectrum.
Distortion in an Op-Amp
An op-amp is basically a non-linear circuit. The input stage, for example, can
accommodate only a small differential voltage before it is limited by the input devices,
both bipolar and CMOS.
Feedback reduces the distortion caused by these limitations. Increasing the
amount of feedback increases the linearity.
If you increase the open-loop gain by a factor of 10 (20dB), distortion drops
by a factor of 10, assuming that, by increasing the gain you have not added more
distortion.
The Miller Capacitance
In 1919 John M. Miller was physicist with the National Bureau of Standards
when he wrote a paper on how the grid capacitance of a vacuum tube was so much
larger in use than measured statically. The voltage gain, he said, multiplies the
capacitance between grid and plate. What he described has been known as the Miller
effect or the Miller capacitance ever since.
Miller went on to doing research at Atwater Kent, RCA and the Naval
Research Laboratory. In 1953 he was awarded the IRE Medal of Honor.
The exact same effect was found in both the bipolar and MOS transistor. In
most applications it is detrimental, limiting the frequency response; in IC op-amps,
however, it has been helpful, greatly decreasing the size of the compensation
capacitance.
John M. Miller: "Dependence of the input impedance of a three-electrode vacuum tube upon the
load in the plate circuit", Scientific Papers of the Bureau of Standards, 1920, pp. 367-385.

Camenzind: Designing Analog Chips Chapter 9: Comparators
9 Comparators
To most people a comparator is merely an op-amp without feedback.

With the very large open-loop gain the output abruptly traverses the entire
available voltage range when one input passes the level of the other.
Vcc
This is true for the majority
Q3
Q4
of comparators, but there are also
Ibias1
50u
Ibais2
25u
some refinements and variations.
Let's examine them.
Q1 Q2
In Ref Out
The first circuit is indeed of
the common variety: an input
Q5 Q6 Q7 Q8 differential pair (Q1, Q2), a current
SUB
mirror active load (Q3) and a second
stage (Q4), giving a voltage gain of
Fig. 9-1: Simple but accurate bipolar
about 95dB.
comparator. The second stage is run at
half the current compared to the
input stage, so that it switches when the differential pair is in balance. It
uses a separate current mirror (Q7, Q8) for a good reason: Q7 saturates. If
we were to run Q7 off Q5 (as Q6 is), it would grossly decrease the collector
current of Q6 as it saturates.
This comparator, using bipolar transistors, requires a small input
current; with an operating current of 50uA (25uA for each input transistor at
balance) and a minimum hFE of 100, that amounts to 0.25uA. We could of
course decrease the operating current, but at the expense of speed and noise.
Also, the reference voltage (i.e. the common-mode voltage) cannot
drop below the VBE of the input transistors (plus the saturation voltage of
Q6), otherwise the input stage is simply cut off. At the upper end the
common-mode range stops at about 0.2V below Vcc, when the input
transistors saturate and cut off Q3 and Q4. On the other hand, Vcc can be
as low as 1 Volt.
A simulation for a high-gain circuit like this one is best set up by
connecting two voltage sources to the inputs. One is steady DC (say 1.5
Volts) while the other one is swept from 1mV below this value to 1mV
above it. You will see the output change drastically very close to the zero
difference at the input. There is very little built-in error because Q1, Q2 and
both sides of Q3 operate at the same collector-base voltage; there is only a

small second-order error due to the fact that the collector-base voltage of Q4
is larger.
But don't let this observed accuracy fool you into believing that this
is what will happen in production. Move on to a Monte Carlo analysis and
you will find that the offset voltage of the differential pair moves the
switching point (by about ± 1mV, depending on the process and the size of
the transistors).
Vcc
The bipolar design can M3 M4
be directly translated into

CMOS, with a logic stage W=20u
L=5u
W=20u
L=5u M5
added at the output. The gain Ibias

M9
W=20u
is now 110dB. 20u
M1 M2
L=5u
W=2u
There is no (DC) input In Ref
L=0.5u
Out
current, but the limitations W=20u

L=1u
W=20u
L=1u
M10
concerning the common-mode W=1u
range still apply. M6 M7 M8 L=0.5u
In a CMOS circuit W=10u W=10u W=5u
saturating current mirrors need L=5u L=5u L=5u
not be feared; the current in M8

can be derived from M6. The Fig. 9-2: CMOS version of figure 9-1.
fact that the drain of M8 can
end up very close to ground has no adverse effect on M7. A word about
the transistor dimensions: the logic stage at the output is designed for a
0.35u process, all other channel lengths and widths need to be this large
even for a process capable of smaller sizes. M1 through M4 require a large
area for adequate matching (in fact, offset can be further reduced by
increasing their sizes) and the 5um channel lengths reduce dependence on
supply.
Quite often hysteresis is required in a comparator, i.e. the threshold
Vcc is higher when the input increases and
Q3 Q4
lower when it decreases. For
example, if you have a "low fuel"
Q5 50uA Out
Ibias warning light you don't want this light
50u
R1
to flicker on and off as the fuel sloshes
Q2
In Q1
400
Ref in the tank, so you set the threshold to
a low level as the fuel is consumed
Q6 Q7 and to a higher level as the tank is
SUB
filled. In figure 9-3 two features have
been added. Replacing the simple
Fig. 9-3: Comparator with hysteresis. current mirror, Q3 and Q4 form a flip-

flop with precisely controlled gain, giving the circuit a snap action. In
addition, the diode connection of Q4 makes Q5 into a current mirror (each
collector sources one-half of the current). This current is fed into a 400
Ohm resistor, causing the reference
voltage appearing at the base of Q2 to 2.014
increase by 10mV (the resistor value 2.012
2.01
can, of course be changed to increase Turn Off

2.008
or decrease this value). The voltage at 2.006
Ref must be capable of sinking the
V
2.004
collector current of Q5. Turn On

2.002
As the input voltage decreases 2
from some value above the reference 1.998
voltage, the current out of the output 1.996
0 0.2 0.4 0.6 0.8 1 1.2
terminal abruptly increases from zero Time/mSecs 200uSecs/div
to about 25uA (the exact level depends Fig. 9-4: Switching levels with
on the output voltage because of the hysteresis.
Early effect). You now have to
increase the input voltage to 10mV above the reference level to turn the
output current off.
Figure 9-5 shows the same circuit in CMOS, with the current output
(M8) opposed by a current sink of half the level (M13), and a logic stage
Vcc
M3 M4 M5 M6 M7
W=20u W=20.3u W=20.3u W=20u W=20u

Ibias M8
L=2u L=2u L=2u L=2u L=2u
M9
20u
W=20u
M1 M2
L=2u W=2u
R1
In Ref L=0.5u Out
1k
M10
W=20u W=20u
L=1u L=1u
W=1u
M11 M12 M13
L=0.5u
W=20u W=20u W=10u

L=2u L=2u L=2u
Fig. 9-5: CMOS comparator with hysteresis.
added. CMOS has an advantage here in that the custom sizing of the
transistors allows the amount of positive feedback to be set in precise
increments (M3-M6). Note that the operating current (Ibias) has been

reduced and the value of R1 increased, resulting again in a hysteresis of

10mV.
Ibias will most likely be derived from a resistor value (and, perhaps,
a bandgap reference voltage). R1 will track this resistor value and thus the
hysteresis is remarkably accurate and stable with temperature.
A comparator with hysteresis requires some thought before
simulating or testing. The two different thresholds have to be approached in
the proper sequence. In a simulation this can be done with a transient
analysis, i.e. letting the input voltage increase until it exceeds the upper
threshold, then decreasing it until a level below the lower threshold is
reached. Similarly, in testing the input is ramped up until switching occurs,
and then ramped down until the output changes states again.
In the examples so far NPN or Vcc

N-channel transistors have been used Q8 Q9 Q10
for the input differential pair. This is a
disadvantage when input signal and
reference are near ground level, unless Q2 Q3 Out
In
you have a split power supply. Q1 Q4
By converting the input to PNP
Q7
or p-channel and a couple of design I1
20u
refinements, a comparator can be made Q5 Q6
SUB
to work at ground level, even if there
is only a single supply.
In figure 9-6 a Darlington input Fig. 9-6: A Darlington input allows the
inputs to be at ground level.
stage is used not to decrease the input
current, but to allow the comparator to
operate even if the input drops slightly below ground. With as much as
400mV below ground at the input Q1 is still in its active region. At that
point the base of Q2 is about 200mV above ground (at room temperature),
which is sufficient to keep Q5 from being cut off. (Strictly speaking the
input stage is not a pure Darlington connection, since the collectors go to
ground).
This circuit has a definite upper temperature limit (about 100oC) and
is rather slow because there is no discharge path at the bases of Q2 and Q3.
Since the primary object is not a low input current, however, there is no
reason why we could not place two additional small current sources (like
Q9) at these points.
Though rarely needed in an ASIC, the ideal comparator has a
rail-to-rail input (it already has a rail-to-rail output).

This is actually quite easy to achieve: two input differential pairs,

one n-channel, the other p-channel; mirror the currents of one and sum the
result with the currents of the other.
Vcc
M17 M20 M5 M6 M7 M8
W=20u W=20u W=20u W=20.3u W=20.3u W=20u

L=2u L=2u L=1u L=1u L=1u L=1u
M=2 M=2 M=2 M=2 M13
M15
W=20u
Ibias In M1 M2 Ref L=1u
M=2 W=2u Out
20u L=0.5u
W=20u W=20u
L=5u L=5u M16
M18 M19 M14

W=1u
L=0.5u
W=20u W=20u W=10u
L=2u L=2u L=2u
M3 M4
W=20u W=20u
L=5u L=5u
M9 M10 M11 M12
W=20u W=20u W=20u W=20u

L=1u L=1u L=1u L=1u
M=2 M=2 M=2 M=2
Fig. 9-7: CMOS comparator with rail-to-rail inputs
In this example the active load of figure 9-5 was chosen, again with
sufficient positive feedback to give a snap-action (M5-M8). Note that M5-
M8 and M9-M12 have a considerably large w/l ratio compared to the
corresponding M1 - M2 and M3 - M4 to allow the input to go slightly
beyond Vcc and ground.

Current Comparators
I1 I2
Vcc
When you use the word comparator you
Q4
automatically assume that voltages are compared.
But this does not always have to be the case,
In1 In2
Out
sometimes it is useful to compare currents.
Q3 With a simple current mirror (Q1, Q2)
Ibias
even a small difference in the magnitudes of I1
Q1 Q2 and I2 will show up quite drastically at the base
SUB
of Q3, turning it on or off.
The base-current error is eliminated if
Fig. 9-8: Bipolar Current Ibias is set at twice the level of I1 and I2. The
comparator. only remaining error is due to the Early effect of
Q3, which is easily reduced by adding another
NPN stage and using a more sophisticated current mirror in place of Q4.
Vcc
The CMOS version is M4 M5
almost identical. There is of I1 I2
course no base-current error, W=20u

L=5u
W=20u
L=5u
M6
but the comments above

about the Early effect (or In1 In2
W=1u
L=0.2u
Out
channel-shortening) apply. M3
M7
Yet even without any M1 M2 W=15u

improvements both circuits L=1u
M=4
Ibias W=0.5u
L=0.2u
switch abruptly within W=15u W=15u
L=1u L=1u
0.0006% over a wide M=4 M=4
temperature range. Matching

variations, however, are Fig. 9-9: CMOS version of current comparator.
another matter and you may
have to make the input current mirrors quite large to get enough accuracy.
Find out with a Monte Carlo analysis.

Camenzind: Designing Analog Chips Chapter 10: Transconductance Amplifiers
10 Transconductance Amplifiers
For a while it looked like there would be a second universal building

block, and the concept was called the Operational Transconductance
Amplifier. But the OTA has rather severe limitations and there is no danger
that it might de-throne the op-amp anytime soon.
Let's examine the concept using a simple bipolar design. Just as in
an op-amp there is a differential input pair (Q1, Q2). Its collector currents
are mirrored separately by Q3-Q5 and Q6-Q8. One of the mirrored currents
+5V goes directly to the output, the second
Igain
Q9 Q11 one is mirrored again (by Q9-Q12) and
then opposes the first one at the output.
Q10 Q12 No matter what value is chosen for the
In+ In-
operating current (Igain), the two
Q1 Q2 Output currents at the output have the same
value (without an input signal) and the
Rload
output voltage is at ground.
30k
Ignore Rload for a minute. As
we have seen in chapter 4 a bipolar
Q4 Q7 transistor has an emitter resistance
Q6 k∗T
re =
Q3 Q5 Q8 q∗ Ie
where k and q are constants, T is the
SUB
-5V
temperature in Kelvin and Ie is the
emitter current. The term for re is
Fig. 10-1: A simple bipolar
transconductance amplifier.
dynamic emitter resistance (often called
"little re") because it changes with
emitter current. At Ie = 1mA it amounts
to roughly 26 Ohms (at room temperature), at 100uA 260 Ohms, at 10uA
2.6kOhm, i.e. it is inversely proportional to Ie. (There is also a constant
resistance in series with re, the physical resistance between the emitter
contact and the base-emitter junction; this becomes significant at higher
currents).
The transconductance of a bipolar transistor is simply:

1
gm =
re
Thus with an emitter current of 100uA the transconductance is
(1/260) Ohms, i.e. a 1mV signal at the base cases a change in collector
current of 3.8uA. In a differential stage the transconductance is half of that
since there is an re in each transistor (and we double the total current so that
each emitter receives 100uA).
In figure 10-1 the currents are mirrored in a ratio of 1:1 so that the
collector currents of Q1 and Q2 appear unchanged at the output. With no
signal at the input they cancel each other but, as one input is moved up or
down, one current becomes larger and the other one smaller by the same
amount. Thus the total transconductance is doubled and we have the same
value as for a single transistor.
Without some DC resistance at the output a transconductance
amplifier is really quite impractical. Even the slightest mismatch in any of
the transistors would slam the output voltage into one of the supply rails; we
need some impedance like Rload to keep this voltage near the center. Rload
converts the current output into a voltage output, which means that we no
longer have a transconductance amplifier but simply a voltage amplifier
(with a high output impedance to boot). Very few of the OTAs are actually
used as transconductance amplifiers.
With Rload back in the circuit the total voltage gain is now simply:
Rload  q 
Av = =  ∗ Ie∗ Rload
re  k∗T 
So we have an amplifier whose gain can be varied (over a wide

range) by varying a current .
And herein lies the problem. The input signal also varies the
current, and thus the gain changes with the amplitude of the signal. The
result: distortion. With a small signal at the input this may be tolerable for
some application, but not with a large signal. Here is the tally:
Input Signal Igain=1uA Igain=10uA Igain=100uA
Gain
-5dB 14dB 32dB
Distortion
10mVp 0.3% 0.2% 0.1%
20mVp 1.2% 0.9% 0.3%
50mVp 6.2% 5.1% 1.6%
100mVp 16% 15% 8%

So, if you have to handle a signal greater than about 20mVp, this
circuit is a poor choice. You cannot use feedback or emitter resistors (for
Q1 and Q2) to linearize it, it would interfere with the variable gain.
There is another problem, not just for this circuit but for all such
schemes: offset. A mismatch in not only the input stage but all three current
mirrors will show up as an offset (and added distortion) at the output,
increasing in magnitude as Igain increases. In this circuit this amounts to
60mV worst-case at 100uA. Also, remember that bipolar transistors have
input currents.
There is help, though, and as usual you need to add a few more
devices. If we +5V
connect diodes to Q3 Q5 Q7 Q9
the inputs and I1

feed the signal in 40u Q4 Q6 Q8 Q10
through a resistor, Output
we have Q15
something very Q16 Rload

Q17 30k
similar to a
In+ In-
current mirror Q1 Q2
(e.g. figure 3-1). R1

22k
R2
22k Q11 Q13
The input Vin
impedance is low I2
Igain
I3 Q12 Q14
because of Q16 20u SUB 20u
(at 20uA re -5V
amounts to Fig. 10-2: An improved version of the bipolar

1.3kOhm at room transconductance amplifier with linearizing diodes.
temperature) and
R22 converts the
input voltage into a current. A 500mVp input signal causes so little change
in voltage at the base of Q1 that the distortion is down to 0.3% at 1uA and
0.01% at 100uA. The offset voltage still persists, amounting to 60mV again
worst case at 100uA.
Both sides of the input pair need to be treated equally, including the
addition of the dummy resistor R2 to avoid worse offset problems. The
current mirrors used here are of the highest precision, sacrificing low
operating voltage for accuracy.
Q15 aids to remove the base currents for Q16 and Q17 from I1, but
even with this measure the ratio between I1 and I2/I3 needs to be precise;
any mismatch will increase the offset voltage and the input current (250nA
max. with perfect matching).

The one great

10
feature of a circuit like
this is the precise control 0
of gain over a wide range.
Figure 10-3 shows the -10
gain (in dB) vs. Igain. A
Gain / dB
linear change in current -20
results in a logarithmic
change of gain. Thus, for -30
audio applications, you

-40
can control the volume (a
logarithmic function)
100n 200n 400n 1µ 2µ 4µ 10µ 20µ 40µ 100µ
with a linear current (or
Igain / A
voltage). The accuracy is
within ±0.2dB. True to Fig. 10-3: Gain is a precise logarithmic function of
Igain.
the exponential nature of the
base-emitter diode, the gain
changes 20dB per decade of current.
Because the diode-connected transistors (Q16, Q17) track the input
transistors, gain is
1.5
virtually unaffected by
temperature. If Igain is
Igain = 100uA
1
derived from a resistor
made from the same
0.5
layer as R1, R2 and
Igain = 10uA
Igain = 1uA Rload, the gain is also
Output / V
0 unaffected by absolute
variations.
-0.5 Figure 10-4
shows the waveform that
-1 appears at the output.
There is a very large
-1.5 change in the level of the
0 0.2 0.4 0.6 0.8 1
Time/mSecs
signal, which is of course
200µSecs/div
the purpose of the circuit.
Fig. 10-4: Output waveforms (1kHz). Because of the offset
voltage a
"transconductance" amplifier is best suited for audio and filter applications
with the output capacitively coupled to the next stage.

The concept works in CMOS too, but the fundamentals are different.
A CMOS transistor naturally takes a voltage at the gate and delivers a
current at the drain, and this transconductance varies as the square of the
operating current.
Figure 10-5 is the
+1.5V
M3 M4 M7 M8
same configuration as figure
W=20u W=20u W=20u 10-1, with NPN transistors
W=20u
L=5u L=5u L=5u L=5u
M=2 M=2 M=2 replaced by N-channel
M=2
devices and PNP transistors

M5 M6 M9 M10
by p-channel ones. The
W=20u W=20u W=20u devices are quite large (M5,
W=20u
L=2u L=2u L=2u L=2u
M=10 M=10 M=10 for example, has a total
M=10
Output
width of 200um with the
In+ multiplier M set at 10) and,
Rload
M1 M2
In-
as we will discover shortly,
40k
M11 M12
W=20u W=20u the sizes chosen are still
L=2u L=2u
W=20u marginal.
W=20u
L=2u L=2u
M=5 M=5 In this and the next
Igain M13
example a dual power
M14
supply of ± 1.5 Volts is
W=20u
L=5u
used. This may be an
W=20u
L=5u
impractical value for you,
-1.5V
the choice was made to
simplify the discussion of
Fig. 10-5: A CMOS equivalent of figure 10-1.
input and output DC levels.
In the real world you may be forced to use a single 3-Volt (or 3.3-Volt)
supply, in which case the inputs and the output have to be biased at half the
supply voltage.
This circuit uses a 0.35um process, necessary because the high-
accuracy current mirrors cannot tolerate an output voltage of less than about
0.6 Volts across them. If you were to use a process with smaller
dimensions you would have to reduce each mirror from four to two devices
and pay the penalty of much reduced accuracy.
A CMOS transconductance amplifier suffers from the same non-
linearity as a bipolar one. Distortion is tolerable only for small input
signals. With a ±40mVp input it amounts to 0.1% at 100uA, 0.7% at 10uA
and 1.4% at 1uA. When the signal is increased to ±75mVp (which results
in the maximum output swing possible, ± 0.9V) the distortion increases to
0.8% at 100uA, 2.3% at 10uA and 4.5% at 1uA.

In the gain vs. operating current plot (figure 10-6) the range is
extended down to 1nA
just to show the wide 20
range achievable. You
10
notice, however, that at
the high-end the circuit 0
deviates from a pure -10
Gain / db
logarithmic behavior; to -20
straighten this line the -30
transistors would have to
-40
be even larger.
Transconductance -50
of an MOS transistor is -60
temperature dependent 1n 2n 4n 10n 20n 40n 100n 400n 1µ 2µ 4µ 10µ 20µ 40µ 100µ
and thus there is a Igain / A
decrease of gain (at any Fig. 10-6: Gain (in dB) vs. Igain.
current) of about 2dB from
0 to 100oC. Also, a CMOS transconductance amplifier has the same offset
problem as a bipolar one; at 100uA this amounts to ± 30mV. Unlike the
bipolar version, however, this circuit has no DC input current.
A rather complex scheme has been developed to linearize the input

stage and still have gain control (see references). To do this 15 more
transistors are needed (M15 to M29, figure 10-7).
M17 is the key device. This "diode-connected" transistor is the
same size as M1 and M2, the input differential pair, and all three devices
share a mirrored Igain current (M23) at their sources. The drain/base node
of M17 receives the same amount of current from M24 through the current
mirror M26 to M29. M25, a cascode transistor, has been added to improve
the matching of the mirrored currents.
The current into the drain/base node of M17 is also shared by M16
and M18, but their current is governed by the fact that they each are part of
another differential pair (M16/M19 and M18/M15) whose operating
currents are set at (3/4)Igain. M15 and M19 are twice as wide as the other
five devices in the input row.
This complicated use of ratios serves to extend the range of input
voltage over which the differential pair is linear. The optimum is reached
with a ratio (between M15/M18 and M19/M16) of 2.155, exceeding ± 1
Volt. For our case here this is of little consequence, 75mV causes an output
swing of ± 0.9 Volts, the maximum the circuit can handle.

At this level the distortion now amounts to 0.1% at 50uA, 0.2% at

5uA and 0.3% at 0.5uA.
+1.5V
M26 M27 M3 M4 M7 M8
W=20u W=20u W=20u W=20u W=20u W=20u

M=2 M=2 M=2 M=2 M=2 M=2
Igain
M28 M29
M5 M6 M9 M10
W=20u W=20u
L=2u L=2u W=20u W=20u W=20u W=20u
M=10 M=10 L=2u L=2u L=2u L=2u
M=10 M=10 M=10 M=10
Output
In- M1 M15 M16 M17 M18 M19 M2 In+
W=20u W=20u W=20u W=20u W=20u W=20u W=20u

L=5u L=5u L=5u L=5u L=5u L=5u L=5u Rload
M=2 M=4 M=2 M=2 M=2 M=4 M=2 80k
M11 M12
W=20u W=20u
M25
L=2u L=2u
M=5 M=5
W=10u
M20 M21 M22 M23 M24 L=5u M13 M14
M=2
W=10u W=10u W=10u W=10u W=10u W=20u W=20u

L=5u L=5u L=5u L=5u L=5u L=5u L=5u
M=4 M=3 M=3 M=4 M=4
-1.5V
Fig. 10-7: Transconductance amplifier with linearized input.
With the device

20 dimensions shown the
circuit cannot handle
10
much more than 50uA
0 (Igain) and starts
deviating slightly from
the ideal logarithmic
Gain / dB
-10
-20
line above 20uA.
Because of the many
-30 additional devices there
is also a slight
-40
deviation below about
-50 10nA. Even so, the
10n 20n 40n 100n 200n 400n 1µ 2µ 4µ 10µ 20µ 40µ
gain control has a range
Igain / A of more than 70dB.
Fig. 10-8: Gain (in dB) vs. operating current (Igain). Note that the
output impedance is

rather high; a buffer may be needed.

The problem with the offset voltage is still present, only slightly
reduced by the lower gain. Figure on a ± 20mV uncertainty at the output.
For this reason transconductance amplifiers are primarily used in audio and
filter applications where the output can be capacitively coupled.

Camenzind: Designing Analog Chips Chapter 11: Timers and Oscillators
11 Timers and Oscillators
Summer of 1970. The economy was at the bottom of the cycle and
Signetics, the promising young company I had joined just two years before,
laid off half of its employees.
Disgusted with the turn of events, I decided it was time to strike out
on my own and rented space between two Chinese restaurants in downtown
Sunnyvale, California. Signetics (now Philips) lent me the equipment I
needed and gave me a one-year contract to develop a new IC.
The idea for the new IC came from the work I did at Signetics on the
phase-locked loop. I had needed an oscillator whose frequency could be set
by an external resistor and a capacitor and was not affected by changes in
either supply voltage or temperature. Several products resulted from the
basic design, among them the NE566 Voltage-Controlled Oscillator.
The oscillator
Vcc
Rext.
contained first of all a
voltage-to-current
R 5k
+
Comp. 1 converter. The reference
V to I Converter
voltage at the positive
- -
5/6 Vcc Q1 input terminal of the op-
+
amp is not regulated, it is
Flip-Flop
S simply a fraction of the
R supply voltage. Feedback
5k
C to the op-amp keeps the
Cext. Comp. 2
voltage across the
+
external resistor at the
-
5k
same level and thus the
Mirror current through the
resistor becomes
(1/6*Vcc)/Rext.
Fig. 11-1: The basic 566 Oscillator. In the actual
circuit the comparators and the flip flop are combined Depending on the
in one Schmitt trigger. state of the switch
controlled by the flip-
flop, the external capacitor is either charged with the current, or discharged
with a current of the same magnitude through a 1:1 current mirror.

There is a divider with three identical resistors, producing 1/3 Vcc

and 2/3 Vcc at the two taps. Two comparators, referenced to these taps,
watch the voltage across the external capacitor. If it moves above 2/3 Vcc,
comparator 1 sets the flip-flop, the switch diverts the current to the mirror
and the capacitor is discharged. When the voltage across the capacitor
reaches 1/3 Vcc, comparator 2 resets the flip flop and the capacitor is
charged again.
This endless cycle
produces a triangle-wave. The
amplitude is dependent on the 4
2/3 Vcc
supply voltage, but so are the
charge and discharge currents 3
and the two effects cancel each

other. Except for small errors V2
inside the IC, such as the offset 1/3 Vcc

voltages of the op-amp and 1
comparators and the matching

0 4 6 8 10 12 14 16 18
in the current mirror, the
frequency is exactly: Time/mSecs 2mSecs/div
Fig. 11-2: Triangle-wave produced by

1 the 566 oscillator.
f =
3∗ R∗ C
What I proposed to Signetics was this circuit, modified so it could

also be triggered and produce a single cycle only, i.e. it would be both an
oscillator and a timer.
The project almost didn't get off the ground; the engineering staff
didn't think much of the idea. Timers at the time were put together from an
op-amp or comparator and a few discrete components, including a Zener
diode or two. They argued that such a design would cut into the sales of
their present ICs. But the marketing manager, Art Fury, over-rode them; a
man with immense practical experience, he simply had the gut feeling that
such a timer would sell.
It was a one-year contract and designing the circuit took half of that.
No computer analysis then, the circuit had to be laboriously breadboarded.
When everything was working I wrote a development report and gave a
design review at Signetics. The design passed without any comments.
But something wasn't quite right. I felt that I had missed something,
that I could do better. It bothered me that the design required nine pins,
which was about the most unfortunate number I could have picked. There
was an 8-pin package; the next higher number was 14.

I started on the layout. In 1971 this meant sitting at a drawing board

for several weeks, fitting devices together into the minimum rectangular
shape and checking each dimension by hand. Then, about two weeks after
the design review, on the way home after work, it suddenly hit me: what
would happen if I got rid of the voltage-to-current converter and charged
(and discharged) the capacitor directly with a resistor? That would bring
the pin-count down to eight.
I made a U-turn, went back to work and tried it. Sure enough, the
timing didn't change as I varied the supply voltage. It was my own
limitation that had made me assume that only a linear relationship between
charge current and end-voltage would cause the cancellation effect. Even
though the charging of a capacitor through a resistor causes an exponential
rise of the voltage, the cancellation was just as effective. In fact, having
eliminated the voltage-to-current converter, I now had not only a smaller
but also a more accurate circuit.
I made the changes in the circuit but didn't bother to request a
second design review. I only told Art Fury, who was pleased; an 8-pin
package was then significantly less expensive than a 14-pin one.
It took another five months to draw the layout, cut the patterns on
Rubylith (by hand), spend endless hours hunched over a light-table to check
dimensions and connections (again: by hand, no computers), make a mask
and a prototype wafer and then evaluate the IC, which Art Fury decided to
call the NE555.
In the meantime, one of my former colleagues left Signetics to join a
start-up. The first circuit this start-up brought to market was the timer I had
described in my design review. Time-wise they beat Signetics by two
months, but when the real 555 came out, they had to withdraw their version
very quickly.
The market reaction to the 555 timer was truly amazing. Art Fury
made history by bringing out the circuit at an unprecedented low price, 75
cents. I had deliberately made the design flexible, but nine out of ten
applications were in areas and ways I had never contemplated. For months
I was inundated by phone calls from engineers who had a new idea for
using the timer. To this day the 555 has been the best-selling IC every year,
copied by numerous companies. Except for a CMOS version, the design
has never been changed.
Looking at the design now, 33 years later, there are many areas
where it can be improved with the design techniques we have learned since
and with the enormous benefit of computer simulation. So, let's look at the
actual 555 timer and then a version which benefits from 33 years of
progress.

Vcc
R1 R2 R3 R4 R12
4.7k 830 4.7k 1K R7 6.8k
5k
Q5 Q6 Q7 Q8 Q9 Q21
Q19
Q22
R13
R10 3.9k
Threshold FM 15k
Q1 Q4 Q23
R11
Q2 Q3
4.7k
Output
Reset Q18 Q20

Q25 R8
Q11 Q12 5k Q17
Trigger
Q10 Q13 Q16
R5
Q15
Discharge 10k
R16 R14
Q24
100 220
R6 R9 R15
Q14 100k 5k 4.7k
(pinched) SUB
Gnd
Fig. 11-3 The original 555 timer.
Both comparators use Darlington input stages. This makes the timer
fairly slow, but allows an extreme range of external resistance. Comparator
1 consists of Q1 to Q8. The four PNP transistors form a current mirror with
gain, provided by the unequal emitter resistors.
The output of this comparator feeds into a 4.7kOhm resistor (R11),
which is part of the cross-connection in the flip-flop (Q16, Q17).
Comparator 2 (Q10 to Q15) resets the flip-flop.
The output stage, which must be able to sink or source some
200mA, is controlled by Q20. In the high state the Darlington pair
Q21/Q22 delivers the current, but at a cost of a voltage drop of about 2
Volts. In the low state Q24 receives sufficient base current to work alone
up to about 50mA; beyond that, as the voltage drop increases, Q23 feeds
extra current into the base circuit.
There are several flaws in this design, indicative of the early period
of IC design (and the inexperience of a rookie designer). Neither
comparator is well balanced, showing offsets of as much as 30mV. The
circuit can get away with that because the voltage swing is quite large.
The operating currents are quite large; the lateral PNP transistors run
at up to 1mA. That was acceptable at the time since the devices had 10um
geometries; today it would be excessive.

The output stage consumes a considerable amount of current in the

low state and, during switching, both output transistors are on for a brief
period of time, producing a current spike in the supply.
10
R1 Output
91k Vcc
8
Threshold FM Vcc RC
555
12 6
Discharge
V
Output
4
Trigger Reset R2
Trigger 100
Gnd Trigger
2
C1
1n 0 20 40 60 80 100 120 140 160 180
Fig. 11-4: Timer connection of the 555. Fig. 11-5: Timer waveforms.
In the timer connection the period starts with a negative-going

trigger pulse, which resets the flip-flop through comparator 2 and moves the
output high. When the voltage across C1 reaches 2/3 Vcc, comparator 1
sets the flip-flop, C1 is rapidly discharged and the output moves low.
Despite the bad offset voltage the accuracy is quite remarkable: the error in
timing is around 1% with a temperature coefficient of 24ppm/ oC. The
timing formula is:
t = 11
. ∗ R1∗ C1
12
10
R1 Vcc
50k R3
Threshold FM 100 V1 8
555
12
V
6
Discharge Output
R2
50k 4
Trigger Reset
Gnd 2
1n
C1 0 120 140 160 180 200 220 240 260 280 300 320 340
Fig. 11-6: Oscillator connection of the 555. Fig. 11-7: Oscillator waveforms.
In the oscillator connection there are two external resistors and the
voltage across C1 moves between 1/3 Vcc and 2/3 Vcc with a frequency
and duty cycle of:
1.46 R2
f = DutyCycle =
( R1 + 2 R2)C1 R1 + 2 R2

It is not quite possible to achieve a 50% duty-cycle; charging and

discharging the timing capacitor through a resistor connected to the output
is not such a good idea; the high and low voltage drops are unequal and
have significant temperature coefficients.
There is a CMOS version of the 555 and a redesign for operation
from a single battery cell (see references), but the circuit is still being sold
today in its original form, despite the fact that much better performance is
possible with more modern design techniques. Here is my candidate:
Q3 R4
20k
R8
3.75k
555
Q6 Q9 Q10
Second Version
Q31
R1 Q4
75k FM Flip-Flop
Q32 Q33 Q34 Q35
Q11 Q14
R2 Q13 Q29 Q30

500 Q12
Q5 R5 Q36
20k Discharge
Q1
Q17
R3 Q28 Q37
34k R6
Q2 Q7 Q8 Q15 Q16 20k Q38
Bias Generator Comparator 1
Vcc
R13
R7
Q41 30k
7.5k
Threshold Q40 Q44 Q48
Q22 Q26
Q19
Q50
Q45
Q47
Output
R10 R11 R12 R14
Q20 7.5k 7.5k 7.5k 7.5k
Q23 Q42
Trigger Q18 Q25 Q51
Reset
R9
Q39
Q27 15k Q49
Q21 Q24 Q43 Q46

SUB
Gnd
Comparator 2 Output Stage
Fig. 11-8: An improved version of the 555 timer, 33 years after the original design.
First off, the new timer gets a proper bias circuit (Q1 to Q5) to hold
the operating currents more constant over the wide supply voltage range.
This (and a few other steps) extends the operating voltage down to 3 Volts.
Comparator 1 (Q6 to Q17) now has a balanced active load (Q15,
Q16) which reduces the error in the timer mode to about 0.5% and the
temperature drift to 3 ppm/ oC without any loss in speed. The change in
timing from 3 to 15 Volts is a mere 0.05%.
There are two changes in comparator 2 (Q18 to Q27): a small
operating current for the outer Darlington transistors, which greatly

improves switching speed, and a balanced active load, which makes the
trigger level considerably more accurate.
The flip-flop (Q28 to Q36) is a new design; it operates in a current-
mode for maximum speed at the lowest possible current. The two 50uA
currents generated by Q31 are split by a pair of lateral PNP transistors; one
quarter of the current is fed into the base of the opposite flip-flop transistor,
another quarter turns the reset transistor on and off and one half of the
current is used to steer the output stage. The voltage swing at the collectors
of the flip-flop transistors (Q30, Q36) is 2VBE.
The most significant change is in the output stage. The base current
for the lower output transistor (Q51) is no longer derived from a resistor. A
small amount of current is injected into the bases of three transistors, forced
to be equal by the three resistors R10, R11 and R12. This (plus an
additional current delivered by Q45) starts a positive feedback loop formed
by Q40, Q41 and Q42. Q40 is about seven times the size of Q41 and Q42
has one emitter while the output transistor has 24. This loop then provides
whatever current is needed to keep Q51 fully turned on.
Positive feedback loops are always dangerous, they can run away or
refuse to turn off. In this case the loop is contained by the collector
resistance of Q43 and can be opened up by turning Q43 off.
Replacing the Darlington configuration in the upper part of the
output stage with a compound (PNP/NPN) transistor reduces the voltage
drop. Base current for this part is provided by Q47. Q44, Q46 and Q49 aid
in turning the power devices off rapidly and eliminate the large transient
current.
With these measures the current consumption is now down to
0.85mA from 3mA (typical) at 5 Volts. At 15 Volts the circuit consumes
1.2mA (down from 10mA). Minimum operating voltage is 2.5 Volts (-40oC
to 100oC).
Shortly after the 555 came out Intersil announced a CMOS version.
It was (and still is) done in a 15-Volt process, which requires large
dimensions and is inherently slow. The circuit is not directly compatible
with the bipolar version, lacking high current outputs.
Except for this weakness, CMOS is ideally suited for a timer: there
is no input current and thus no need for Darlington stages.
Figure 11-9 shows a design using a more modern 5-Volt (0.5um)
process. The comparators are conventional (as discussed in chapter 9), with
the dimensions of the devices chosen so that the threshold and trigger inputs
can move rail to rail and their matching is adequate for precision operation
(3ppm/ oC).

M3 M4 M6 M8 M18 M19
R2
Vcc
40k
W=10u W=10u W=10u W=10u W=10u W=10u
L=0.5u L=0.5u L=5u L=5u L=5u L=5u
M13
Discharge
M15
Reset
Threshold M1 M2 M22 M25
FM W=20u
L=0.5u
W=5u
W=10u W=10u R3 L=0.5u W=4u W=20u
L=0.5u L=0.5u 40k L=0.5u L=0.5u
M9 M10
M=10
R1
100k Output
W=10u W=10u
Trigger L=0.5u L=0.5u
M17
M20 M21 M23 M24 M26
M5 M7 R4 M11 M12 M16

W=10u
40k M14
L=0.5u W=10u W=10u W=2u W=100u W=20u
L=0.5u L=0.5u L=0.5u L=0.5u L=0.5u
W=5u W=5u W=10u W=10u W=10u M=5
L=5u L=5u L=0.5u L=0.5u W=5u L=0.5u
L=5u
Gnd
Fig. 11-9: A 5-Volt CMOS version of the 555 timer.
Ordinarily a flip-flop consists of two cross-coupled gates. In this

case two cross-connected transistors fed by current sources result in smaller
temperature and voltage drifts, because the flip-flop switch levels track the
operating currents of the comparators.
The operating currents are set by R1, which limits the operating
voltage range in which high precision is obtained to 3 to 5 Volts. Replacing
R1 with a current source extends this range down to 1 Volt.
A CMOS output stage
Vcc
swings rail to rail (unlike a bipolar
Vcc output which at the very least has a
Threshold FM
minimum drop of some 150mV, if
Discharge Output not an entire VBE). Thus the timing
R1 CMOS555 resistor can be connected to the
100k Trigger
Reset
1n Gnd
output, resulting in a square-wave
C1 with a precise 50% duty-cycle. On
the other hand, CMOS devices are
inferior to bipolar ones when it
Fig. 11-10: 50% duty cycle oscillator. comes to current handling. Even
with a gate-width of 200um for the P-channel devices and 100um for the N-
channel transistor, the circuit only delivers 10mA and the voltage drop is
.25V (which badly affects the duty-cycle). It would be better to have
separate outputs for the timing resistor and the load.

+12V
R1 R2 R14
5k 5k 13k R5 R6
375 375
Square
Q1 Q2
Q3
R9
7.5k
R3 R4 R7 R8
Q4 Q5 15k 15k 750 750
Q19 Q22
Rext
C Q16
65k A
Q18 Q21
Cext. Q13 Q14 R10
20p 7.5k
R Q23 Q25
R11
B
7.5k
Triangle Q24
Q7 Q20 Q26
Q6 Q8 Q17
Q15
Q12
Q10 R12 R13 Q27

Q9 Q11 1.5k 1.5k
SUB
Fig. 11-11: A high-frequency triangle-wave generator.
Figure 11-11 shows an oscillator which produces a precise triangle

waveform even at relatively high frequencies. All transistors which
determine speed are NPN and do not saturate.
First the low-frequency part, the current sources used to charge and
discharge the external capacitor. The primary current is produced by Rext;
being connected between the positive supply and two VBEs the current
through the resistor is not only dependent on the supply voltage but also has
a temperature coefficient. Both of these effects are eliminated by using an
internal resistor chain (R9, R10 and R11) connected the same way.
The primary current is mirrored by Q6, Q7, Q9 and Q10 and then
mirrored again (Q1 through Q5) to form the charge current. A second
current of twice the magnitude is derived from the first current mirror by Q8
and Q11. This latter current is used to discharge the capacitor and is turned
on and off by the differential pair Q13/Q14.
The internal resistor chain is used to bias the rest of the circuitry and
provide the reference voltages for two comparators; the voltage across the
three identical resistors is (Vcc - 2VBE).

Comparator 1 consists of a single differential pair (Q18,Q21) as

does comparator 2 (Q23, Q25). They provide the operating current for the
flip-flop (Q19, Q22) with two of their collectors while the other collectors
switch the flip-flop's bases. The ratio of the resistors in this arrangement is
key: the operating currents for the comparators is set by R12 and R13,
which have one VBE across them. The two currents end up flowing
together through either R5 or R6, depending on the state of the flip-flop.
R5 and R6 are one quarter the value of R12 and R13, so the voltage drop
across them is one-half VBE. In other words, the collector voltages of the
flip-flop drop 1/2 VBE below the base potential, which is safely above the
saturation voltage.
Now the question is: how do we get this small voltage fluctuation,
located just below Vcc, to work on the bases of the differential pair
Q13/Q14, which must operate in the voltage region below the low point of
the wave-form? We cannot use lateral PNP transistors, they are far too
slow.
We do this by coupling the switching signal to the differential pair
through two resistors (R3, R4) and running a known DC current through
them. Q12 and Q15 are current mirrors, slaved to the bias chain (Q27).
Their current thus increases as the supply is increased, and so do the voltage
drops across R3 and R4. Thus the average potential at the bases of the
differential pair stays at a fairly constant 1/3 Vcc, over an operating range
from 9 to 15 Volts.
The triangle wave-form
9 across the capacitor is buffered
8.5 by the emitter follower Q16 for
8 use by both the comparators
7.5
and an external load. At the
7
unused collector of the
differential switching pair a
V
6.5
square-wave can be obtained.
6
This is not an oscillator
5.5
of ultimate precision, but it
5
delivers a good-quality wave-
4.50 0.5 1 1.5 2 2.5 3 form up to at least 1MHz. The
Time/µSecs 500nSecs/div temperature coefficient is
190ppm/ oC and the change in
Fig. 11-12: Wave-form at 1MHz.
frequency from 9 to 15V
supply is 1.7%. As always, these results are based on one particular
process; it is a good idea to re-simulate the design for the process you are
using.

A triangle-wave can be +12V

A
looked at as a sine-wave with R5

1.4k
distortion. This is not so far- R2

200
Q1
fetched, because the distortion is Q2 R6

300
only about 12%. If we round R10

1.5k
Q3
R7
off the peaks, we end up with a Q4
1.2k
R11
fairly respectable sine-wave 8k
Q6
Q5
with relatively little effort. 20u

I4
20u
I5
20u
I6
Figure 11-13 shows a

companion circuit to figure 11- 20u 20u 20u
R8
3.2k
11. It is inserted between points Triangle
R1
Sine
I1 I2 I3
A and B, replacing R10. The 5k

Q7
R19
triangle wave, entering through 10k
Q8
R15
R1, encounters attenuators at six Q9 1.2k
R20
different voltage levels. Follow 2k
Q10
R16
a positive-going signal: at first R21

Q11 300
Q12
there is no attenuation; at about 200
R17
1.4k
0.6 Volts R11 kicks in, held at
Gnd
that level by Q6; at the next B
higher level R10 appears in Fig. 11-13: Shaping circuit, transforming a

triangle-wave into a sine-wave.
8
7.5
parallel to R11 and at the final
7
level an even smaller resistor, R2,
reduces the signal even further.
6.5
Using only three clipping
V
6
levels in each direction, the
5.5 resulting sine-wave has a
5 distortion of only 1%. Using more
4.5 levels reduces the distortion, but
40
is likely to require trimming.
0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2
Oscillators (and timers) can
Fig. 11-14: Triangle and sine-wave.
often be very simple for non-critical
applications. Suppose you wanted to create a brief pulse once a second, for
example to flash an LED. The frequency or pulse-width need not be
precise, i.e. the design does not require two sophisticated comparators; a
simple Schmitt Trigger will do.

Figure 11-15 shows Vcc

Rext
a bipolar design for such an 750k LED
Q5
LED flasher, intended for Q6 R6

15k
use at either 5V or 3.3V. RC LED
Q3 and Q4 form a simple
Q3 Q4
comparator, with Q5 as an R1
R7
3k
active load. Rext charges 15k
R3 Enable
Cext and when the voltage Cext
Q2
50k R4 R5
Q7 R8
1u 45k
at the base of Q3 exceeds R2
7.5k 7.5k
R9
that at the base of Q4, Q6, Q1
1.5k 30k
Q2 and Q7 turn on. R10 Q8

100k
Through the voltage divider SUB
(pinched)
R6/R7/R8 Q7 now abruptly

lowers the potential at the Fig. 11-15: Circuit generating brief current pulses.
base of Q4, while Q2
discharges Cext through R1. When the voltage across the capacitor drops to
the new level at the base of Q4, Q6 turns off and the cycle starts anew.
The frequency is set by Rext and Cext (here 1 Hz) and the pulse-
width by R1 and Cext (20msec). The frequency is accurate to within 2%
from 3 to 5.5 Volts (not counting the variation of the external components),
but the pulse-width reflects the
Y2 Y1 variation of R1, a diffused
200 4
180
resistor.
3.5
160 LEDs have a rather
3
140 large forward voltage drop
I(LED-anode) / mA
2.5
120
(about 2 Volts), so a supply
RC / V
100 2
80
voltage of at least 2.5 Volts is
1.5
60 required. The current through
1
40 LED Current the LED (40mA) is primarily
0.5
20
determined by the size of Q1;
0 0 1.2 1.4 1.6 1.8 2 2.2 2.4 2.6 2.8
it operates in the high-current
Time/Secs 200mSecs/div
region, where the gain has
Fig. 11-16: Wave-forms of the pulse generator. already decreased but the
spread of hFE becomes
narrow. Average current consumption is 1mA.

Q18
+3.3V
It is interesting to
Enable consider a CMOS design
W=10u
L=0.35u for the same function.
M3 M4 M9
We can avoid using a
Rext
1Meg resistive divider (and
W=10u W=10u W=1u
L=0.35u L=0.35u
M=9
L=0.35u M11
LED thus save current) by
using two comparators
W=10u
M1 M2
L=0.35u and making two of the
RC
W=20u
L=0.35u
W=20u
L=0.35u
M12 M14
LED transistors in each
M=9
R4 W=1u W=1u
M16 comparator nine times
130k L=1u L=1u
W=20u
the size of the others.
M5 M6
L=0.35u
M=5 This results in an offset
W=20u
L=0.35u
W=20u
L=0.35u M17
of some 200mV. The
M=9 M10 M13 M15
reference potentials for
330n
Cext R1
20k
M7 M8
W=10u W=1u W=1u
W=10u
L=0.35u the comparators are the
L=0.35u L=1u L=1u M=4
W=10u W=10u
M=4 supply lines. As the
L=0.35u L=0.35u
M=9 voltage across the
external capacitor rises to
200mV below the
positive supply, the upper
Fig. 11-17: CMOS design for a pulse generator.
comparator (M1 to M4) sets the flip- 3
flop (M12 to M15); as it falls to Vcc - 200mV
200mV above ground the lower 2.5
comparator resets it. Cext is charged 2
by Rext (1 second) and discharged by

RC / V
1.5
R1 (20msec). The two times are
surprisingly accurate, exhibiting a 3% 1
change from 3 to 3.6 Volts and 0 to 0.5

100oC. Ground + 200mV
The output current, on the other 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4
hand, shows the weakness of CMOS: Time/Secs 200mSecs/div
it varies ± 21% with a supply voltage Fig. 11-18: Waveform at RC of

change of ± 10%. For this reason an figure 11-17.
even large output transistor (M16) and a
resistor in series with the LED may have to be used.
With a 20msec pulse of 37mA every second, the entire circuit
consumes just 650uA average.

A second example, a timer this time, shows just how low a power
dissipation can be achieved if a resistor divider is avoided: the circuit in
figure 11-19 draws 1uA at 1.8 Volts.
The entire circuit (save the output inverter) is powered from the
Start pulse, rising from ground to Vdd. The logic input must stay high
longer than the set
Start M3 M4 M5 M6 Vdd
timing. Alternately, if
W=5u W=5.2u W=5.2u W=5u
the Start terminal is
M10
R1
L=0.18u L=0.18u L=0.18u L=0.18u simply connected to Vdd,
M12
10Meg
M8
W=2u
the circuit becomes a
L=0.18u
W=10u
start-up timer.
RC M1 M2
W=2u
L=0.18u
L=0.18u M1 to M6 form a
Output
W=5u W=5u
comparator. By making
M7 M9 M11
L=0.18u
M=10
L=0.18u
M1 ten times as wide as
M13
W=0.18u W=3u W=3u M2, an 80mV offset is
3.3n
C1
L=60u L=0.18u L=0.18u
W=5u created. The gate of M2
L=0.18u
is connected at Vdd, thus
the comparator switches
Fig. 11-19: A 1.8-Volt timer which consumes just 1uA.
at 80mV below Vdd.
The switching action is
enhanced by employing a small
1.8
amount of positive feedback; M4
1.6
and M5 are slightly wider than +V - 80mV
1.4
M3 and M6 and deliver their
1.2
drain currents to the opposite
1
sides (see also figure 9-5)
V
Capacitor
0.8
The operating current for Output
0.6
the comparator is provided by
0.4
M7, a long and thin transistor.
0.2
The advantage of such a device is
00 20 40 60 80 100 120 140 160 180 200 220
size: it produces about 0.6uA
Time/mSecs 20mSecs/div
using a relatively small area; a
resistor doing the same job Fig. 11-20: Switching threshold of the 1.8V
(1.2MOhms) would be painfully timer.
large.
On the other hand an MOS transistor with its gate connected to the
supply is hardly a constant current source. With a 25% change in supply
(1.6 to 2 Volts) the current changes 70% (0.5 to 0.85uA). Here we can
afford to live with this shortcoming.
The two outputs of the comparator are level-shifted by M8 and M10
and the active load M9/M11 to fit the input of an inverter.

A circuit operating at such a low current is of course quite slow; a

significant timing error occurs below about 50usec. At lower speeds you
can expect an accuracy of better than ± 5% from 1.6 to 2 Volts and 0 to
100oC.
Simulation of Oscillators
You have just drawn up a great idea for an oscillator and start the
simulation. Nothing happens, you get nothing but DC levels.
This situation is all too common. The simulator is trained to first
find an operating point, i.e. set the DC voltages and currents so all the
device equations are satisfied (in simulator-speak: find convergence). Then
the transient analysis starts and the computer finds that all the voltages and
currents remain unchanged over time.
In real life the circuit may start at exactly the same point, but no
voltage or current stays unchanged, there is noise. No matter how tiny these
fluctuations are, they move the circuit to a slightly different operating point
and it becomes apparent that movement in one direction is the path to be
followed. Thus, gradually, the oscillation builds momentum.
Without any noise (or some sort of transient disturbance) no circuit
would oscillate; it would just sit there, precariously balanced.
It is of great advantage to have a simulator which allows real-time
noise (i.e. all currents and resistors actually produce the appropriate amount
of noise not only for a (small-signal) ac simulation, but during a transient
analysis as well). With this feature a properly designed oscillator will
always start. If you are using a simulator which has no real-time noise, you
may have to coax the oscillator by jarring it with a pulse, e.g. step the
supply voltage abruptly to a higher level.
But there is a second potential problem: it may take a long time for
the oscillation to build up. For the circuits discussed so far in this chapter
this is no great worry, but for the type of circuits we are about to encounter
this can be very frustrating.
Take a crystal oscillator, for example. A high-quality crystal can
take up to a second to start oscillating. At 10MHz, that amounts to 10
million cycles the simulator has to go through, in very small time steps to
catch any movement. If you are not aware of this nuisance, you may sit
there watching flat lines and come to the conclusion that your oscillator
does not work.

LC Oscillators
Oscillators using inductors are rarely used in integrated circuits,

except at frequencies above GHz. But there are occasions at lower
frequencies when only an inductor can give you the performance required.
One such example is shown in figure 11-21.
The object of this
+10V
R3 design is the creation of a
1.5k * 10MHz sine-wave with a
Q1
Q7 large amplitude. Q8 and
TX1 *
Q11 are the oscillating
50p
transistors, cross-coupled
Q2
Cext. by the collector-base
R2 capacitances of Q9 and
1Meg
Q10 (about 8pF each).
(pinched)
Q9
A small current
Q3 Q10
Q5
Q8 (about 12uA) is injected
Q11
Q4 Q6 into the bases of Q8 and
R1
30k
Q11 to bring them into a
SUB current level at which there
is sufficient gain. TX1 is
Fig. 11-21: Sine-wave oscillator with large in reality a center-tapped
amplitude.
inductor, shown as a
transformer with two windings for
the simulation.
20
The collectors of the 18
oscillating transistors start at the 16
supply voltage, 10 Volts. After a 14
+10V
few hundred cycles of gradually 12
increasing amplitude the waveform

V
10
at each collector is limited by the 8
6
emitters of Q5 and Q6 at the 4
negative end; at this point the peak- 2
to-peak amplitude has reached 21 0
550 600 650 700 750 800
Volts, more than twice the supply
Time/nSecs 50nSecs/div
voltage. The action of the center-
tapped inductor is that of a see-saw: Fig. 11-22: The voltage swing of the
one end dips to ground (or slightly oscillator extends to twice the supply
voltage.
below) while the other peaks at a little
above 20 Volts.

Though the supply voltage is 10 Volts, the four transistors Q8 to

Q11 must have a voltage capability of 21 Volts.
To minimize the output capacitance, each oscillating transistor can
share a collector region with its cross-coupling capacitor.
Crystal Oscillators
Let's start with the circuit commonly used in CMOS: the crystal is
connected between the input and the output of an inverter. Since an inverter
is ill-equipped to remain in a state
between low and high, R1 is M1 M3 M5
+3.3V
employed to force it into the linear

region, at least initially. C1 and C2 W=2u
L=0.35u
W=2u
L=0.35u
W=2u
L=0.35u
are a mystery to most designers;
they are there because the crystal M2 M4 M6
manufacturer specifies them.
The whole arrangement is a W=1u
L=0.35u
W=1u
L=0.35u
W=1u
L=0.35u
bit curious. An oscillator needs to

have positive feedback, yet the R1
1Meg
phase-shift between the input and
the output of an inverter is 180 Crystal
degrees - negative feedback. To

10p 10p
understand this we need to look at C1 C2
the crystal itself.

A crystal is simply a sliver
of quartz that vibrates. Quartz is Fig. 11-23: CMOS crystal
piezoelectric, i.e. a voltage applied oscillator.
between two surfaces makes it flex and flexing it creates a voltage between
its surfaces.
The vibrating mass of the crystal C1 L1
R1
can be represented as a series-resonant LC 25.33f

10m 30
circuit (C1, L1) with a series resistance C2
R1. The Q (originally the quality factor) 4p
of such an LC circuit is given by:

Fig. 11-24: Model for a crystal.
2∗ π ∗ f ∗ L1
Q=
R1
and the resonant frequency by:

1
f =
2∗ π ∗ L1 ∗ C1
The values in figure 11-24 were chosen to give a series-resonant frequency

of exactly 10MHz and a Q of 20,000. The Qs of crystals range from 10,000
to 2 million, i.e. far higher than those of LC circuits. Ceramic resonators,
which are otherwise almost identical to crystals, have considerably lower
Qs.
C2 is the stray capacitance created by the contacts to the crystal and
the wires and pins of the package.
If we open the feedback loop in the circuit of figure 11-23 (as shown
in figure 6-14) we can see what is happening. There are in fact two
resonances, about 0.2% apart. The lower one is the series resonance, the
upper one parallel resonance. At these two frequencies the phase shifts
abruptly between 180 and zero degrees.
The parallel
Y2 Y1
resonance is created by C1,
C2 and the combination of
40
160 external capacitances. In an
140
30 oscillator properly designed
120 20
Gain for series resonance it is of
no concern.
Phase / degrees
Gain / db
100 10
80
0 +3.3V
Phase M1
60
-10
40
W=2u
-20
20
L=0.35u
10 10.005 10.01 10.015 10.02 10.025 10.03 10.035 10.04

M2
Frequency/MHertz 5kHertz/div
R2
W=1u 10k
Figure 11-25: Series and parallel resonance of a L=0.35u
crystal.
R1
But even the series resonance is 1Meg
influenced by the additional capacitances. As Crystal

you notice from the plot it is not exactly 10MHz.
C1 C2
There are two reasons: 1. At resonance the
10p
impedance of a series resonant LC circuit 10p
becomes very low, limited only by R1. Thus it

works best if the input impedance of the inverter Fig. 11-26: Improved
is low. In figure 11-23 all we have for input CMOS crystal
oscillator.

impedance is a 10pF capacitance and the gate capacitances. Thus C1 sees

itself in series with this capacitance
and the effective capacitance is Y2 Y1
slightly smaller. 2. At resonance the 80

0
With R2
phase moves from 180 degrees to 60
-10
zero, but it doesn't actually reach 40
Gain
-20
zero (the condition required for
Phase / degrees
20
dB / db
oscillation) until about 10.015MHz. 0
-30
If we shift the phase in the -20 -40

Phase
feedback loop with an additional -40 -50
resistor (working against C2) a zero -60

-60
degree phase-shift is reached at the -80

10 10.005 10.01 10.015 10.02 10.025 10.03 10.035 10.04
series-resonant frequency. With R2 Frequency/MHertz 5kHertz/div
the frequency is more accurate and
the chances of the crystal operating at Figure 11-27: The insertion of R2 in
some unwanted frequency (including figure 11-26 brings the phase shift to
harmonics) are diminished. But be zero degrees at the series resonance.
aware that R2 decreases the loop gain;
make sure it safely exceeds unity.
Simulating a crystal
3
oscillator can be a frustrating task.
2.5
The higher the Q, the longer it takes
for the oscillation to build up. In the
2
case of figure 11-26 it takes 3msec
M1-drain / V
1.5
for the oscillation to reach full
amplitude. If you want to measure
1
the frequency accurately, you need
0.5
to do this in very fine steps (say
00 +5V
0.5 1 1.5 2 2.5 3 3.5 4
R1 R2 R3 C1 C2
Time/mSecs 500µSecs/div 11k 7k 2.5k 10p
25p
Pulse
Figure 11-28: Start-up of a crystal Crystal Sine
oscillator.
R4
Q1 Q3 Q4
10k
1nsec), i.e. you have to wait for
30,000 cycles before you can see R5
10k
the actual wave-form. Q2 Q5
SUB
Figure 11-29 shows a
different approach, for a bipolar Fig. 11-29: Alternate crystal oscillator with
process. Gain and a 180 degree bipolar devices.

phase-shift is obtained through Q4, which needs to run at a fairly substantial

current (about 1mA for the differential pair). The base of Q4 is biased at
2VBE, which gives sufficient voltage swing without saturating the
transistor.
Q3, on the other hand, saturates. By making its collector resistor
larger than that of Q4, a pulse (square-wave) output is obtained, swinging
between 0.5 and 5 Volts.

Camenzind: Designing Analog Chips Chapter 12: The Phase-Locked Loop
12 The Phase-Locked Loop
The idea of the phase-locked loop surfaced as early as 1932, but

remained an esoteric and expensive concept until the arrival of the
integrated circuit. The PLL has the unique ability to capture a signal
without requiring precision components, a welcome feature in a world of
large variations.
The phase-locked loop is primarily an analog concept and only
when we treat it as such can we fathom its powerful capabilities. And here
is where simulation fails us. Anyone who has ever sat down at a bench and
observed a phase-locked loop grabbing a minute signal seemingly buried in
noise will agree that a simulation cannot give you the same sensation. In a
real circuit, a phase-locked loop almost seems to be alive, capturing and
hanging on to a signal as the frequency is changed; a simulation of the same
circuit is a cold experience, giving you no intuition (and taking up an
enormous amount of time).
To get a feel for the operation of a phase-locked loop you need to
understand the key component, the phase detector. So, let's begin with this.
The circuit in figure 12-1 is known
Vdd
R1
20k
R2
as the four-quadrant multiplier, one of
20k
several schemes used as phase-detectors.

Low-Pass
Filter Output There is a straight-forward
C1
differential pair, M5 and M6, which

M1 M2 M3
amplifies a signal arriving from outside the
M4
IC. But instead of the drains being
W=1u
L=0.35u
W=1u
L=0.35u
W=1u
VCO
L=0.35u connected to load resistors or an active
W=1u
L=0.35u
load, their currents pass through four other

M5 M6
transistors, which are turned on and off by
Signal W=5u
L=0.35u
a local voltage-controlled oscillator
W=5u
L=0.35u
(VCO).
20u
I1 The signal inputs are at a certain
DC bias level, say 1V or 1.5V, high
enough to exceed the threshold voltages.
Fig. 12-1: The phase detector.
Now imagine a square-wave at the

VCO input with a frequency 200
exactly the same as that of the 150

input signal. This could be a rail-
100
to-rail 2-phase square-wave or,
preferably, a wave-form moving ± 50
Diff Probe / mV
Output
200mV differentially, centered at 0
about 2V DC. At first (figure 12- Signal

-50
VCO
2) the VCO wave-form is in-phase
-100
with the input signal, i.e. the two
-150
cross zero at the same time.
During the first phase of the -200
0 0.2 0.4 0.6 0.8 1 1.2 1.4
VCO signal, the drain of M5 is Time/µSecs 200nSecs/div
connected to R1 (through M1) and Fig. 12-2: With the VCO signal in-phase,
the drain of M6 to R2 (through the output is a rectified sine-wave with a
M4). During the second phase this positive average.
connection reverses: The drain
current of M5 flows through M2 and R2 and that of M6 through M3 and
R1. Thus, ignoring C1 for now, the output across the two load resistors is a
rectified sine-wave with a positive
200 average value.
150
Now, let's keep the
Output
100
frequencies the same but shift the
phase of the VCO signal by 90
50
Diff Probe / mV
Input
degrees (figure 12-3). The signal
0
is now chopped at the moment it
-50
reaches its peak amplitude and the
-100
output shows equal positive and
-150 negative excursions. Thus the
VCO
-200
0 0.2 0.4
average differential output voltage
0.6 0.8 1 1.2 1.4
Time/µSecs is zero. 200nSecs/div
If we shift the VCO wave-

Fig. 12-3: With the phase of the VCO
signal shifted by 90 degrees, the average
form a further 90 degrees (still
of the output voltage is zero. keeping its frequency constant),
the VCO wave-form chops the
signal at the zero-crossings again, but now the output is inverted.
Averaging it with C1 results in a negative voltage.
Thus, with C1 back in the circuit, we have a DC (or low-frequency)
signal at the output of the phase detector which is a measure of the relative
phases of the two frequencies. If we use this "error" signal to adjust the
frequency of the voltage-controlled oscillator, we have the phase-locked
loop (figure 12-5).

Here is what will happen 200
in slow-motion: Let's say the 150
VCO is running at 1MHz and the 100

VCO Signal
input signal is some distance 50
Diff Probe / mV
away in frequency, e.g. 800kHz. 0
Since the two frequencies are not -50
synchronized, there is no phase Output
-100
relationship yet. At this point the
-150
phase detector is merely a mixer,
-2000
producing several new 0.2 0.4 0.6 0.8 1 1.2 1.4
Time/µSecs 200nSecs/div
frequencies, such as the
difference between the two Fig. 12-4: At 180 degree phase shift
frequencies and various the average of the output is negative.
combinations of harmonics. The
one of interest is the difference,
200kHz; it is still too high to pass
through the filter.
As we move the input
signal gradually higher in
frequency, there comes a point
where the difference frequency is
low enough so that some of the
signal passes through the filter and
Fig. 12-5: Block diagram of a simple phase-
locked loop. starts influencing the VCO. The
signal is not rectified yet, it is still
AC, but the VCO starts to jitter
around its free-running
frequency. Move the input signal 1.3
Loss of Lock
just a little higher in frequency
and suddenly the jitter disappears 1.2
and the VCO jumps into step

MHz
1.1
with the input signal. Now we VCO
see a DC level at the output of 1
the filter. 0.9

Lock-On
As you continue to move Signal

the input signal higher in 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5
frequency, the VCO will Time/mSecs 500µSecs/div
continue to track it, until the loop Fig. 12-6: Locking behavior of a phase-
finally runs out of control voltage. locked loop.
This is illustrated in figure 12-6
where signal frequency is swept from low to high over a 5msec period.

The exact same behavior is seen as you approach the VCO

frequency from the high end. The capture range (the maximum difference
between the two frequencies to achieve lock-on) is always narrower than
the lock range (how far you can drag the VCO and still keep lock). It makes
no difference which frequency is moved and which is fixed.
Both the capture range and the lock range are influenced by loop
gain and signal level. If you increase the gain of the loop or the input signal
level, both ranges become wider.
(Strictly speaking the name phase-locked loop is a misnomer. As
you move through the lock range, the two frequencies are locked but their
phase relationship has to change to produce the error signal, i.e. the phase is
not locked. Frequency-locked loop would be a better name).
The phase-locked loop has three important features, especially for

integrated circuits:
1. Apart from the loop gain, the capture range is determined by a

single low pass filter. For example, if the signal you are looking for is at
50Mhz and has a narrow band-width (say 5kHz), you dimension the low-
pass filter so it rolls off at about 5kHz. This makes the phase-locked loop
look like a very sharp band-pass filter. A single-pole low-pass filter rolls
off at 20dB per decade, so at 49.9MHz and 50.1MHz the interfering signal
is attenuated at the low-pass filter by 26db. Using an active filter, it would
take many poles and a large number of precision components to achieve the
same selectivity.
The phase-locked loop depicted in figure 12-5 is a second order PLL
(i.e. it has two poles, one by the VCO itself, the other by the low-pass
filter). This configuration is unconditionally stable. Adding another pole
makes stability (i.e. the absence of unwanted oscillation) more difficult to
achieve, but it doubles the sharpness of the filter action.
2. The VCO need not be highly accurate. As long as the free-

running frequency is within the capture range of the signal, the loop will
find the exact frequency.
This advantage, however, is made a bit difficult if your capture
range is very narrow. In the example above the free-running frequency
would have to be within 5kHz of the signal, i.e. 0.1%. Without using
accurate components, such precision can only be achieved by tuning, for
example by sweeping the VCO over a wider range, detect capture (see
below) and then stop the sweep.

3. The error signal (i.e. the output of the low-pass filter) is a measure of
frequency deviation. If the input signal is frequency modulated, this output
is the demodulated signal.
There is even a simple solution if the modulation is AM, not FM

(figure 12-7). In this approach the VCO has a second output (same
frequency but shifted 90 degrees) and a second phase detector and low-pass
filter are added.
In the middle of the lock range,
the phase shift between the signal and
the VCO is automatically 90 degrees,
so that the control voltage for the
VCO is zero. This means that the
signal frequency is chopped at the
amplitude peaks. A second phase
detector operating at zero degrees
phase shift will, therefore, chop the
same signal at the zero crossing and
the result is a voltage proportional to
Fig. 12-7: Phase-locked loop with amplitude. This output then delivers
AM output. not only the demodulated AM but also
indicates that the loop is locked.
How do you design a voltage-controlled oscillator? We have seen

some examples in chapter 11, but for most applications VCOs for phase-
locked loops are specialized for high-frequency operation. We have two
examples here.
+3.3V
M2 M3 M7 M8 M12 M13 M17 M18 M22 M23
Output
W=5u W=5u W=5u W=5u W=5u W=5u W=5u W=5u W=5u W=5u
L=0.35uL=0.35u L=0.35uL=0.35u L=0.35uL=0.35u L=0.35uL=0.35u L=0.35uL=0.35u
I1
2u
M4 M5 M9 M10 M14 M15 M19 M20 M24 M25
W=1u W=1u W=1u W=1u W=1u W=1u W=1u W=1u W=1u W=1u
L=0.35u L=0.35u L=0.35u L=0.35u L=0.35u L=0.35u L=0.35u L=0.35u L=0.35u L=0.35u
M1 M6 M11 M16 M21 M26
W=5u W=5u W=5u W=5u W=5u W=5u

Fig. 12-8: Current-controlled oscillator for operation between 6MHz and 300MHz.

The first example is a current-controlled oscillator, though it is a

simple matter to convert the current into a voltage.
I1 sets the operating currents for five simple differential amplifiers
with active loads. The outputs of each amplifier are connected to the inputs
of the next stage and the outputs of the last stage back to the inputs of the
first. It is a ring oscillator, relying on the delay caused in each stage. This
delay is dependent on the operating current, increasing as the operating
current is decreased. With I1=10uA the delay in each stage amounts to
1.6nsec and the frequency is 300Mhz. With I1=0.1uA the delay increases
to 83nsec and the frequency decreases to 6MHz. A remarkably large range.
But the delay in each stage is caused by a number of effects, each
with its own temperature coefficient. The net result is a variation in
temperature coefficient from +800ppm/ oC at 0.1uA to +200ppm/ oC at
10uA. This temperature coefficient can be partially compensated by
introducing an opposite tempco into the voltage to current converter, most
likely optimized at one operating current only.
Our second example (figure 12-9) uses a different approach. Similar

to the 566 oscillator in figure 11-1, a capacitor (C1) is charged and
M8 M10 M12
10u
I1 W=20u W=20u W=20u M22 M23
L=0.35u L=0.35u L=0.35u M25 M26 M28
M=2 M=2
W=2u W=2u
M9 M11 M13 L=0.35uL=0.35u W=2u W=1u W=1u
L=0.35u L=0.35u L=0.35u
R1 W=20u W=20u W=20u

15k M3 M4
L=10u L=10u L=10u
M=4 M=4 M=2 R4 R5
40k 20k
W=20u
W=20u M5 M20 M21
L=5u L=5u
W=20u W=1u W=1u

L=0.35u L=0.35u L=0.35u
M18 M19
1.5V
W=5u W=5u
R2 L=0.35u L=0.35u
5k
M1 M2 M14 M16
C1 R6
1V 20k M29
W=10u W=10u W=20u W=20u
L=5u L=5u L=10u L=10u 2p
Vin
M=2 M=2 W=0.5u
L=0.35u
R7
10k M6 M7 R3 M15 M17 M24 M27
10k
W=5u W=5u W=20u W=20u W=10u W=10u

L=1u L=1u L=0.35u L=0.35u L=1u L=1u
Fig. 12-9: Voltage-controlled oscillator with a Schmitt Trigger.

discharged by a current. But using two comparators and a flip-flop would

be too slow for high-frequency operation. So we employ a Schmitt
Trigger, which has fewer devices in sequence and thus reduced delay.
There are two thresholds again. The lower one is 1/2*Vdd and is set
by the two equal resistors R5 and R6. When this lower threshold is
reached, M21 and M25 turn on. This connects R4 in parallel to R5, which
makes the upper threshold 2/3*Vdd. Notice that the resulting triangle
waveform at the capacitor has an amplitude of only 1/6*Vdd peak-to-peak;
we are trading accuracy for speed.
This is a somewhat improved version of a Schmitt Trigger; the most
important factor determining accuracy is the "ON" resistance of M25. If it
amounts to a substantial part of the value of R4, the effective resistance will
be higher and will have a different temperature coefficient than R5 and R6.
To make this "on" resistance small, we should increase the gate width of
M25, but we can only do this at the expense of speed. The dimensions
chosen for M25 are a compromise.
There is a separate stage (M26) to create a rail-to-rail swing and an
inverter (M28, M29) to make both phases available to the phase detector.
The rail-to-rail output of the Schmitt Trigger is also used to switch
the capacitor current between charge and discharge (M18, M19). Again, the
dimensions chosen here are a compromise. For accuracy over a wide control
current range we want them to be large; to get a fast response, they need to
be small.
There is a voltage to current converter (M1-M7) and R3 is intended
to be an external resistor. The control voltage is derived from Vdd through
a resistor divider (R1, R2, R7) with a rest value of 1 Volt, so that the current
tracks the two thresholds and the frequency is independent of supply
voltage. With no signal at the input, the voltage to current converter
produces 100uA. A large-value resistor can be inserted between the two
input terminals and the base of M1 modulated with the error signal (thus
changing the current by perhaps ±10uA or ±20uA. To adapt the phase
detector shown in figure 12-1 to this VCO, an active load can be used,
converting the differential error signal to a single-ended one and then
bringing it to near ground potential with a current mirror.
With C1=2pF the frequency of oscillation is 36MHz, with a
temperature coefficient of -370ppm/ oC. At 60MHz (C1=1pF) the
temperature coefficient increases to -680ppm/ oC because of the greater role
played by delay. Below 20MHz the temperature coefficient is close to zero.
There is a ± 0.3% change in frequency for a ± 10% change in supply
voltage.

The Schmitt Trigger

Otto H. Schmitt was not a German electronics engineer as one would expect.
He was born in St. Louis, Missouri in 1913 and studied biophysics and zoology. All
through his life he built the electronic equipment he needed for his research himself and
became an expert in electronics as well. In 1934 (at age 21) he was engaged in the
study of the nervous system and came up with a bistable circuit which mimicked the
behavior of a nerve (using vacuum tubes, of course). He never patented it.
The schematic below is a translation of his circuit into MOS devices. With the
input low, the gate of M2 is biased high through R1, thus M2 is turned on. The ratio of
R2 to R3 sets a bias point at the sources of the two transistors. When the input is moved
above this point (plus the threshold voltage of M1), M1 turns on, M2 turns off and the
bias voltage is set to a lower level by the ratio of R1 to R3.
Otto Schmitt died in 1998, after a long and productive tenure at the University
of Minnesota. Although he is best-known for his "Schmitt Trigger", it represents only a
minute fraction of his contributions to science and engineering.
+3V
3
R1 R2
2.8
20k 10k Output
2.6
2.4
M1 M2 Output
Input 2.2
V
2
Input
W=3u W=3u 1.8
L=0.35u L=0.35u
1.6
1.4
R3
5k 1.2
1
0 2 4 6 8 10

Camenzind: Designing Analog Chips Chapter 13: Filters
13 Filters
We can go back as far as 100 years and find elaborate electronic

filters, using inductors, capacitors and resistors. And the inductor in these
combinations has always been the problem child, the largest, heaviest, most
expensive and least reliable component. With the advent of integrated
circuits its status moved from undesirable to virtually impossible.
There is an intriguing relationship between the inductor and the
capacitor; they are direct opposites. As you charge an inductor, the voltage
appears first, the current follows later; in a capacitor the current must flow
before the voltage can build up. If we build a circuit which shifts the phase
180 degrees, a capacitor has all the appearances of an inductor. It is on this
phenomenon that IC filters are based.
Active Filters: Low-Pass

R1 Consider a simple RC network. It has a
15.9k C1 cutoff frequency (the point at which the amplitude
drops by 3dB) of:
1n
1
f 3 dB =
2πRC
Fig. 13-1: Single-
pole RC low-pass For the
filter.
values 0
shown in -2
figure 13-1 this amounts to -4
-6
10kHz. Below about 1kHz there
Attenuation / dB
-8
is no attenuation. At 10kHz the -10
signal at the output is down by -12
3dB and at 100kHz (10 times fc) -14
the attenuation amounts to 20dB. -16
If you extend the straight portion -18
of the curve (figure 13-2) upward 100 200 400 1k 2k 4k 10k 20k 40k 100k
it points precisely at 10kHz. Frequency / Hertz
Such a single-pole, passive RC Fig. 13-2: Frequency response of a

single-pole filter.

low-pass filter is said to have an attenuation of 20dB per decade or 6dB per
octave (doubling of the frequency).
We don't need to be R1 R2
+ +
satisfied with just one RC 15.9k C1 15.9k C2
network, we can connect 1n 1n
several of them in series (i.e.
cascade them). But we need Fig. 13-3: A poor way to sharpen filter response.
to put a buffer in between the
stages, otherwise the network 0
following will load down the -2

1
previous one too much. -4
But look at what we have -6
done (figure 13-4). A second stage -8
will roll off faster, but it also

dB
-10
lowers the -3dB frequency. The -12

16
more stages there are in series, the -14
2
lower the cutoff frequency. With -16
16 stages it has moved down to a -18
little over 2kHz. 100 200 400 1k 2k 4k 10k 20k 40k 100k
We can do much better than Frequency / Hertz
this on two fronts. First, the

Fig. 13-4: Placing identical low-pass
frequency response can be shaped at stages in series lowers the cutoff
will by choosing different resistor frequency.
and capacitor values for each stage.
There are schemes for this, worked out mathematically a long time ago, in
the era of passive filters. They carry such names as Butterworth, Bessel and
Chebyshev.
Second, we can take advantage of active components (such as op-
amps) and create more compact filter stages. There are many such designs,
with names such as Sallen & Key, Multiple Feedback, Fliege, Bach, KHN,
or Tow-Thomas.
C4 Figure 13-5 shows a second-order
180p
active filter, using a design developed by
R7 R6
+ R.P. Sallen and E.L. Key. Only one op-amp
180k 60k
is required for two poles.
C3 The component values are chosen to
75p give a Butterworth response; with different
values we could change the frequency
Fig. 13-5: Second order Sallen response to a Bessel or Chebyshev function.
& Key Butterworth filter. As you can see from figure 13-6, the
drop-off is now twice as steep as that of a

0
single RC network (i.e. 40dB per
-5
decade or 12dB per octave) and
the -3dB point has remained at -10
Attenuation / db
10kHz. -15
-20
Let's now take a look at -25

three filters. The nominal
-30
designs are identical; they all
have two cascaded second-order 100 200 400 1k 2k 4k 10k 20k 40k 100k
Sallen & Key stages. But each Frequency / Hertz
filter has different R and C

Fig. 13-6: Frequency response of the
values. filter in figure 13-5.
C4 C6
8.2n 1.5n
R7 R6 R11 R10
+ +
3.6k 8.58k 7.82k 21.5k
0
1n Bessel
1n C5 -5
C3 Sallen & Key Chebyshev
Butterworth
-10
C12 C2 -15
Butterworth
1.5n 3.3n
dB
R19 R18 R3 R2
+ + -20
5.1k 16.2k 3.32k 9.03k
1n -25
1n C1
C11 Sallen & Key
Bessel -30
-35
C13 C15
-40 1k 2k 4k 10k 20k 40k

10n 4.7n
R22 R23 R26 R27
+ +
9.76k 34.1k 8.83k 27.5k Frequency / Hertz
1n
82p C16
C14 Sallen & Key
Chebyshev
Fig. 13-8: Frequency responses of
the three low-pass filters.
Fig. 13-7: Three fourth-order low-pass filters.
The different component values result in
different frequency responses.
Judging by the frequency
response alone, the Chebyshev filter has the sharpest response, though it
produces some ripples in the pass-band (i.e. below 10kHz). This ripple can
be reduced, at the expense of steepness above 10kHz. In even-order
Chebyshev filters the ripples are above the line (0dB in this case); in odd-
order ones they are below the line.
The Bessel filter gives a gentle roll-off with no overshoot in the
pass-band, and the performance of the Butterworth filter is in between the
other two.

But there is more to the

performance of a filter than just 0
the frequency response. Take

-50
the phase of the signal, for Bessel
example. It never stays -100
constant in any filter with the -150

delays caused by the Butterworth
deg
capacitors. But there is a -200
difference between the three -250
filter types. The Bessel filter

-300
has the smallest phase-shift, the Chebyshev
Chebyshev the largest. -350
1k 2k 4k 10k 20k 40k
The phase response
Frequency / Hertz
influences two more measures
of filter quality. The first one is Fig. 13-9: Phase response of the three
filters.
called Group Delay, shown in
figure 13-10. Assume that you pass through the filter not just one
frequency, but several. A delay in the filter causes the phase-relationships
of the different frequencies to change and distortion results.
The Bessel filter is by far the
180
best in this respect, having not only
160
the shortest delay but also the most
140
Chebyshev constant. The Chebyshev filter is by
120
far the wildest.
100
Also, we can judge a filter by
µSecs
Butterworth
80
its pulse response. In figure 13-11 a
60
40
1.2
20 Chebyshev
Bessel
0
1
1k 2k 4k 10k 20k 40k Bessel Butterworth
Frequency / Hertz 0.8
Fig. 13-10: Group delay of the three filters. 0.6

V
0.4
100usec pulse was applied to the
input. We expect a rounding of 0.2
Input
the corners at the output but, 0
considering that all three filters 0 20 40 60 80 100 120 140 160 180
have the same cut-off frequency,
the Bessel filter does the best job.
Fig. 13-11: Pulse response of the three
filters.
How do we get the values for
the resistors and capacitors? If you open up a text-book on filters, you will

see elaborate tables giving you coefficients for Butterworth, Bessel and
Chebyshev functions. This is no longer necessary. There are a multitude of
programs available on the web (many of them at no cost), which calculate
these values for you. Search for "active filter software".
Bessel, Chebyshev and Butterworth
Friedrich Wilhelm Bessel (1784 to 1846) was a professor of astronomy

at the University of Königsberg in Germany. By measuring the position of
some 50,000 stars he greatly advanced the state of celestial mechanics and came
up with the Bessel function, which was found to be also useful in filters.
Pafnuty Chebyshev (1821 to 1894) taught mathematics at the

University of St. Petersburg. His major contribution was the theory of prime
numbers but, similar to Bessel he left behind a function which later turned out
to be applicable to filters.
Of Stephen Butterworth we know only that he worked at the British

Admiralty for almost all his life. In 1930 he published a paper "On the Theory
of Filters". He died in 1958.
C2 C4
Let's look at two more 1.08n 1n
low-pass filters, using designs R1
11.76k
R2
11.76k
+
R5
12.24k
R6
12.24k
+
other than Sallen & Key. The C1 C3

R3 R7
two stages in figure 13-12 use 1n R4
1k
1n R8
10k
voltage-controlled voltage- 9.5k 8.1k
sources (VCVS), an approach

differing from Sallen & Key
Fig. 13-12: 4th-order low-pass Butterworth filter
only in that the op-amps have in a voltage-controlled voltage-source design.
gain.
R2 C2 R6 C3 The design
R1
15k
R3
1n 6.2k
R5 R4
1n approach for each stage
15k 7.5k
+
6.2k 3.1k
+
of figure 13-13 is
C1 C4 called Multiple
2.7n 15n
Feedback.
All these
Fig. 13-13: A 4th-order Multiple Feedback approach. different approaches
render the same
frequency and phase response, but they differ in sensitivity, i.e. how much
component and op-amp parameter variations will influence filter
performance. A temperature and Monte Carlo analysis reveals the merits.

High-Pass Filters
R2 R4
There is no mystery
6.1k 14.7k
to converting a low-pass C1 C2
+
C3 C4
+
filter into a high-pass one: 1n 1n 1n 1n
you simply exchange R1 R3

41.6k 17.2k
resistors and capacitors.
The drop-off now
Fig. 13-14: High-pass Sallen & Key filter with
occurs toward the low- Butterworth values.
0
frequency end, but at the same rate as
-10 that of a low-pass filter, 80dB per
-20 decade for a fourth-order filter.
-30
dB / db
-40 Note that in all of these

-50 drawings, abstract op-amps are used
-60 (inside the symbol is an ideal voltage-
-70 controlled voltage-source). In a
1k 2k 4k 10k 20k 40k 100k practical design you have to consider
Frequency / Hertz the power supply. With a single
supply, you may have to bias the input
Fig. 13-15: Frequency response of the
4th-order high-pass filter of figure 13-14. midway between ground and +V. In
figure 13-14 this is accomplished at
the low ends of R1 and R3.
Band-Pass Filters
Take the R2
0
3.3k
second-order low- -2
R1 C2 -4
pass filter of figure + -6
83.1k
13-5 and convert 1n -8
dB / db
-10
C1 R5
one RC network to R3 -12
3.18k 10k
1n
high-pass. You R4
5k
-14
-16
now have a drop-off -18
40 50 60 70
in amplitude at both Frequency/kHertz 10kHertz/div
high and low Fig. 13-16: Sallen & Key band- Fig. 13-17: Second-order
frequencies. pass filter. band-pass filter response.

Although the arrangement is called a second-order band-pass filter, the

drop-off rate is only first-order, 20dB per decade, since only one pole is
active in each frequency segment. We can of course improve this by adding
more stages, each stage contributing another 20dB per decade drop-off.
And here there is a bewildering number of schemes available, with names
such as Wien-Robinson, Deliyannis, Fliege, Twin-T, Mikhael-
Bhattacharyya, Berka-Herpy and Akerberg-Mossberg. Your filter program
will tell you which one to choose.
There is also an additional choice for the frequency response:
compared to the Chebyshev filter the elliptic (or Cauer) has an even steeper
initial drop-off, but the attenuation in the stop-band (i.e. outside the pass-
band) is not flat.
R8 R9
R1 R2
+ 6k 12k +
94.5k 94.5k R6
6.4k
C1 C3 C5 C6
30.9p 33p 270p 270p

R3 R4 R10 R11
47.2k 66p 220 6k 540p 220
C4 C7
+ +
R7
95.6k
2.1p R5 R12
C2 34.9k 34.9k
Fig. 13-18: A fourth-order, twin-T elliptic band-pass filter.
The filter of figure 13-18 has two Twin-T stages. The first stage is
a second-order low-pass notch
configuration, the second stage is 10
called a second-order high-pass

notch filter. The center frequency 0
was chosen to be 50kHz, the

dB / db
-10
bandwidth 2kHz. Just outside the
bandwidth the attenuation reaches -20
a maximum, but then settles down

-30
to a modest 15dB.
42 44 46 48 50 52 54 56 58 60
It must be clear to you by
now that active filters are costly. Fig. 13-19: Response of a fourth-order
elliptic band-pass filter.
Not only do they require precision
components, but the values of most
capacitors and some of the resistors are such that they cannot be integrated.
A fourth-order low-pass or high-pass filter requires at least eight external

components and five pins. For a band-pass filter with only modest
performance 14 external components and pins are needed.
Switched Capacitor Filters
If we charge a capacitor (CR) by Clock

closing switch S1 for a brief period of time,
then open S1 and close S2 for the same
amount of time, the potential across the
V1 V2
capacitor is first that of V1, then V2. S1 S2
One of the handiest formulae to carry CR
in your mind is:
Q = C ∗V = I ∗ t
Fig. 13-20: Making a resistor
out of a capacitor by switching
i.e. the charge in a capacitor (in Coulombs) at a rapid rate.
is given by either the capacitance times the
voltage or the current flowing into the capacitor for a certain period of time.
In the case of figure 13-20, the current flowing between the two terminals
over one period is
C R ∗ (V 1 − V 2)
I= = C R ∗ (V 1 − V 2)∗ f clock
t clock
If we had a resistor between V1 and V2 instead of the switches and

the capacitor, the current flowing through it would be:
(V 1 − V 2)
I=
R
Thus the equivalent resistance of the switched capacitor is:
1
R=
C R ∗ f clock
Let's look at some numbers. Suppose the switching frequency is

100kHz and CR = 5pF:
1
R= = 2∗10 6 = 2 MegOhms
10 ∗5∗10 −12
5

Thus, with a relatively small capacitor we can create the equivalent

of a large-value resistor. If we were to implement such a device directly,
the cost in area would be prohibitive.
But the area reduction is just the first benefit of switching; there is
more: if we use this resistor in a filter, the absolute capacitance value
disappears.
Shown here is a simple, one- Clock
pole low-pass filter. The cutoff

frequency is given by:
1
f 3dB = S1 S2
2∗ π ∗ R∗ C CR C
Substituting the equivalent

resistance of the switched capacitor we
get:
R
f clock ∗ C R C
f 3dB =
2∗ π ∗ C
If we make the two capacitors Fig.13-21: By using the equivalent

equal (any value) and switch at a rate resistance of a switched capacitor
in a filter, only the capacitor ratio
of 100kHz we get a filter with a cutoff and the clock frequency are
frequency of 15.9kHz. If C is ten important.
times the size of CR and the clock
frequency remains at 100kHz, the cutoff frequency decreases to 1.59kHz.
Thus, the switched-capacitor filter has two significant advantages
over the active (linear) one:
1. A low cutoff frequency can be achieved with capacitor values small

enough to allow integration.
2. The cutoff frequency is not influenced by absolute variations. Given an

accurate clock frequency and capacitor ratios of 1%, the cutoff frequency
will be within 1%.
The simple low-pass filter can be expanded into any of the

configuration discussed under active filters. Take for example the Sallen &
Key filters in figure 13-7. In a switched-capacitor design you would first

greatly reduce the values of the capacitors and then replace the resistors
with a capacitor and switches.
The switched-capacitor filter requires lateral switches, which are
easily implemented in CMOS, but cumbersome (and slow) in a bipolar
process. For this reason, this approach has become exclusively CMOS
territory.
To minimize the influence of stray Ph1
CR
Ph2
capacitances four (CMOS) switches are

often used instead of two, resulting in an
inverting configuration. Ph2 Ph1
For either switch design it is

important that the two lateral switches
never be closed at the same time, i.e. there Fig. 13-22: Switch
configuration to minimize
must be some "dead-time" between the the effect of stray
two phases of the clock. capacitances in CMOS.
There are four disadvantages with
switched-capacitor filters:
1. No matter how carefully you design the switches, there is always some
switching noise.
2. A switched-capacitor filter samples the signal. To get an adequate

sample, the highest signal frequency cannot exceed about 10% of the clock
frequency. If there are signals present above that point, the switched-
capacitor filter will produce a mixture of new frequencies, some of which
may appear in the 0 to 10% frequency range. To avoid such false signals, a
linear (active) filter must be used at the input (an anti-aliasing filter).
3. With an ordinary simulator, switched-capacitor filter can only be

analyzed in real time; you cannot take advantage of the many features of an
AC analysis, such as measuring frequency and phase response. And with
the clock frequency necessarily being high, simulation takes far more time
compared to an active filter. Only if the simulator has additional features,
such as time delay in the AC model, can it give close to the same picture as
that offered by linear AC analysis. There are some programs that have been
designed exclusively for the analysis of switched capacitor filter.
4. The output has sampled noise, which is present even if the input is zero.

Camenzind: Designing Analog Chips Chapter 14: Power
14 Power
Linear Regulators
Let's say you have 12 Volts available but need 3.3. Your 3.3-Volt
load consumes up to 500mA. The 12-Volt source (e.g. a car battery)
fluctuates between 10 and 14 Volts; the lower voltage needs to be within
5%.
The immediate choice to effect this change in voltage is a linear
regulator. Look at it as a variable resistor, dropping whatever voltage is not
needed.
Q1
Vcc The unwanted
Q9
voltage is dropped in
Q12 an NPN transistor. In
Q2
Repi Q7
C1
Q13 figure 14-1 this is a
50
10p
Vreg
Darlington
Q15
Q14
Q10
R3 configuration to
26.25k
R1
Q5 Q6
minimize the drive
3k
Q3
R4 current; it requires at
Q16 15k
Q4 Q8 least 2.2 Volts
R2
Vref
difference between
6k Q11
1.2 SUB
Vcc and Vreg, but it
is an easy and simple
design.
Fig. 14-1: Linear regulator with NPN power stage. The regulator
uses a 1.2-Volt
bandgap reference
(see chapter 7), whose voltage is compared with a fraction of the regulated
output by the differential amplifier Q5, Q6, Q7 and Q10. Once the circuit is
in balance the voltages at the bases of Q5 and Q6 are equal, so the regulated
voltage is:
Vref ∗ ( R3 + R4)
Vreg =
R4

An operating current is set up by Q1 to Q4 (a circuit derived from

figure 5-4) and mirrored by Q9. At this point we have about 150uA and the
current has a deliberate negative temperature coefficient (R2, which creates
this current, is connected across a VBE, which itself has a negative tempco).
This counteracts the positive tempco of hFE.
Q10 shunts to ground whatever operating current is not needed by
the output stage.
Using a Darlington
3.5
configuration for the output
greatly reduces the required 3
operating current, but there must 2.5
always be a substantial voltage
Output Voltage / V
2
drop between supply and output.
For this reason such a circuit is 1.5
anything but a low-dropout 1
regulator. For our application, a

0.5
conversion from 10 Volts min. to
3.3 Volts this is of little concern. 0
0 2 4 6 8 10 12
The current that flows Supply Voltage/V 2V/div
through the load also flows Fig. 14-2: Drop-out voltage of NPN
through the output transistor. So, at regulator.
500mA, the load consumes 1.65
Watts, the regulator 4.36 Watts
4.5
(with 12-Volts in), which is
4
simply converted into heat.
3.5
Output Transistor This the main disadvantage of
Power Dissipation / W
3
a linear regulator. The heat is
2.5
produced mainly by one
2
device: Q13. Thus there will
1.5
Load be a hot-spot on the chip and
1
0.5
resulting temperature
00
gradients, even with an
2 4 6 8 10 12
adequate heat-sink. These
Supply Voltage/V 2V/div
temperature gradients are
Fig. 14-3: In a linear regulator the energy not bound to influence other
required by the load is converted into heat. circuitry on the chip, including
the regulator's own reference.
A linear regulator with an NPN output transistor is relatively easy to
compensate. Despite the fact that the loop gain is high (which results in an
output impedance of a mere 4mOhm) the circuit is rendered stable with a

single 10pF compensation capacitor. This stability holds even if a filter

capacitor (of any size) is added at the output.
-30
3.34 -40
No Output Capacitance
-50
Power Supply Rejection / db

3.32
Output Voltage / V
-60
3.3 -70
-80
3.28
-90
100uF
3.26
-100
0 1 2 3 4 5 6 7 8 9
1k 2k 4k 10k 20k 40k 100k 400k 1M 2M 4M 10M
Frequency / Hertz
Fig. 14-4: The regulator is stable, even Fig. 14-5: Power supply rejection
with a filter capacitor at the output. with and without a filter capacitor.
Because of the low output

impedance it takes a massive
capacitor at the output to have an
effect of power supply rejection 3.5
(figure 14-5).
3
There are three transistors
and a resistor in this design which 2.5
Output Voltage / V
we have not discussed yet. The 2
differential pair Q14/Q15 1.5

compares the reference voltage
1
(which is assumed to have a very
small temperature coefficient) with 0.5
a voltage slightly higher than 2 20 40 60 80 100 120 140
VBE (which has a strong negative Temperature/Centigrade 20Centigrade/div
tempco). At temperatures below

about 120oC the voltage at the base Fig. 14-6: Temperature shut-down.
of Q14 is higher than Vref and Q15
is cut off. But at about 140oC these two voltages become equal and Q15
diverts the operating current for the output stage. Thus when the chip gets
too hot, the output collapses and the source of the heat disappears. This
makes the regulator virtually indestructible. As the Monte Carlo analysis
indicates (figure 14-6) the accuracy of the shut-down point is ± 10oC.

Low Drop-Out Regulators
To get a lower Vcc

R3
minimum voltage drop Q3
Q6
15k Q10
40x
we need to replace the
I1
NPN Darlington Q8
Vreg
20u Q9
transistor at the output C1
10x
with a PNP (or P- 50p C2 R4
26.25k
20p Cext
Channel) device. And Q2 Q5
4.7u
here is where the problem R1 R2
R5
15k
7.5k 7.5k
starts. Vref I2 Rext
47
Output transistors 1.2
Q1
Q4
Q7 300u
need to be large to carry SUB
the current and thus have

substantial capacitance, Fig. 14-7: Low drop-out regulator with internal (lateral)
multiplied by the Miller PNP transistor at the output.
effect. This forms an
additional pole, which gives the regulator a stubborn tendency to oscillate.
It takes three capacitors to
Y2 Y1
quiet down this regulator. C1
160 160 Phase provides the main pole at about
140 140 30Hz. C2 corrects the phase at
120 120
very high frequency and Cext,
Phase / degrees
100 100
together with Rext form a zero at
dB / db
80 80
60 60 1kHz. In addition the loop gain is

40 40 Gain reduced with R1 and R2. Even so,
20 20
the phase margin is barely 50
0 0
-20 -201
degrees.
10 100 1k 10k 100k 1M
The external capacitor
Frequency / Hertz
Fig. 14-8: Phase/gain diagram using three

compensation capacitors. -50
Power Supply Rejection / dB
offers the benefit of increased power -60
supply rejection, but its effectiveness -70
is limited by the series resistor

(which is essential to form the zero -80
and turn the phase back up). At -90
frequencies above about 5kHz the 1m 10m 100m 1 10 100 1k 10k 100k 1M 10M
power supply noise appearing at the Frequency / Hertz
output is simply determined by the Fig. 14-9: Power supply rejection.

collector capacitance of Q10 and Rext.

Q10 is a large lateral
3.2
PNP transistor with an effective
emitter length 40 times that of a
3
small device, which makes it
2.8
Drop-Out Voltage capable of carrying about 20mA.
Vreg / V
2.6 At this current the drop-out

2.4 voltage is 300mV and the output
2.2 impedance is 4mOhms.
2
Current capability can be
increased at will, simply by
2 2.5 3 3.5 4 4.5
making the output transistor
VP/V 500mV/div
larger. Low drop-out regulators
Fig. 14-10: Drop-out voltage at 20mA. using lateral PNP transistors
have been built for up to 5
Amperes, but at such high
current levels it helps having a special process which provides a higher
doping level for the emitter. Even so, the output devices take up some 80%
of the chip area. Be aware that, as the lateral PNP transistor saturates at the
drop-out voltage, its substrate current becomes very large.
High Currents in an IC
There are two factors which limit how much current an IC can carry. The
first is electro-migration. The force of huge numbers of electrons rushing through a
conductor can become so large that the electrons begin to move atoms, physically
push them along. For pure aluminum this happens at about 500'000 Amperes/cm2.
The effect is slow, it may take months, but eventually there will be an area where
there is no aluminum left. Electro-migration is aggravated by high temperature and
depends on the composition and grain structure of the metal.
Half a million Amperes may seem large and safe, but when you consider that
you are dealing with very thin layers, the limitation becomes real. For example, for a
thickness of 10'000 Angstroms (10'000Å = 1um) and a width of 1um a current density
of 500'000A/cm2 is reached with just 5mA.
The second limitation is resistance. Pure aluminum has a resistivity of
2.8uΩcm. Thus a layer 1um thick has a sheet resistance of 28mOhms/square. Make
this run 100um long and you have a resistance of 2.8Ohms.
Let's say you want to carry 1 Ampere over a distance of 1000um on a chip.
With a thickness of 1um, the aluminum stripe would have to be at least 200um wide
to avoid electro-migration. It then would have a resistance of 140mOhms, i.e. drop
0.14 Volts.
And don't forget to check how much current contacts and vias can take in
your process, as well as the thickness required for bonding wires.

Vdd
Figure 14-11 shows
M5 M6
M7 a CMOS version of figure
M9
W=20u W=20u 14-7. Also dimensioned
L=1u L=1u W=20u
I1 L=1u W=20u for 20mA, the P-channel
L=0.5u Vreg
20u
C1 M=20 output device is smaller
0.1p R1
than the previous lateral
M2 M4
10k PNP transistor. A low
Cext dropout voltage is,
1.2
W=1u
L=1u
W=1u
L=1u
10u however only present at
M8
R2
low current; to get the
M1
Vref
M3 W=10u
20k Rext
1
same value at 20mA, M9
L=1u would need to be 20 times
W=10u
L=1u
W=10u
L=1u
the indicated size, or a total
width of 8000um.
Fig. 14-11: Low-drop out CMOS regulator. 1.8
1.7
1mA
The circuit was designed for a 1.6
supply voltage of 3 to 3.6V and a 1.5

M9-drain / V
10mA
regulated output of 1.8V. 1.4
Frequency compensation is nearly 1.3

20mA
as difficult as in the previous example. 1.2
1.1
Again an external capacitor with a resistor
11
in series is necessary at the output to 1.2 1.4 1.6 1.8 2 2.2 2.4 2.6 2.8 3
Vdd/V 200mV/div
create a zero and turn the phase up.
Fig. 14-12: Drop-out voltage.
Y2 Y1
180 180
-40
160 160
-45
140 140
Phase -50
120 120
-55
Phase / degrees
100 100
dB / db
-60
80 80
-65
60 60
40 40
Gain -70
20 20 -75
0 0 -80
-20 1k 10k 100k 1M 10M 100M
10 100 1k 10k 100k 1M 10M 100M
Frequency / Hertz Frequency / Hertz
Fig. 14-13: An adequate phase margin is Fig. 14-14: ...but Rext limits power
achieved with Rext .... supply rejection at high frequency.

The last linear Vcc

R3
regulator makes the most Q3
1.5k
FMMT549
sense for higher-current Q4
C1 Q6
applications. Using an Vreg

10p
external PNP power Q5
transistor, it requires an extra 15X R4
pin, but it greatly reduces the 25.6k Cext
Q1 Q2
area and power dissipation of 47u
the IC. Also, depending on R1

7.5k
R2
7.5k
R5
15k
the external transistor used, Vref Rext
50u 300u 100m
the drop-out voltage can 1.2
I1 I2
remain low even at high SUB
current.
With the chosen
device for Q6, the maximum Fig. 14-15: Low drop-out regulator with external
current is around 500mA. At PNP transistor.
3.3
this level the supply voltage can drop to
3.25 10mA within 200mV of the output (3.3V).
3.2 500mA
100mA
There is, however, a compromise
3.15
in the loop gain, which effects the output
Vreg / V
3.1
3.05
impedance (33mOhm); in order to achieve
3 stability, the gain has to be reduced (R1,
2.95
R2). Also, the same scheme as used in the
2.9
2.85
two previous circuits is required: an
3 3.2 3.4 3.6 3.8 4
output capacitor with a resistor in series to
Fig. 14-16: Drop-out voltage.
VP/V 200mV/div
keep the phase from reaching zero before
the gain does.
Y2 Y1
180 180 -20
160 160
-30
140 140
120 120 -40

Phase
Phase / degrees
100 100
Gain / db
-50
80 80
-60
60 60
40 40 -70
Gain
20 20
-80
0 0
-20 -20 1 -90

10 100 1k 10k 100k 1M 10M 1 10 100 1k 10k 100k 1M 10M
Frequency / Hertz Frequency / Hertz
Fig. 14-17: Phase margin can only be Fig. 14-18: ... which again impairs
kept high by a resistor in series with power supply rejection at high
the output capacitor .... frequency.

Switching Regulators
Assume again that you have a supply voltage of 12 Volts, but you
need 3.3 Volts. Your load consumes 1 Ampere.
A linear regulator acts as a resistor which drops the unneeded 8.7
Volts. In the process it converts 8.7 Watts into heat. 3.3 Watts are used by
the load; a rather dismal efficiency.
Enter the switching regulator: instead of creating a resistance
between input and output, it connects an inductor between the two for short
periods of time.
Vcc The switch, S1, is driven
S1
PWM by a pulse generator (PWM, or
pulse-width modulator). The
L1
Out pulses are rapid, so that the
27u C1
RLoad inductor value can be small.
D1
4.7u
10 The inductor, together
with C1, smoothes out the
switching pulses.
Fig. 14-19: Reducing a supply voltage with a
series switch and inductor. When the switch is
closed, the left node of the
inductor is at Vcc (assuming the
switch has no resistance), but when the switch opens, this voltage jumps
abruptly to a large negative value, created by the energy stored in the
inductor. It is the purpose of D1 to catch this negative spike so it does no
harm to the switch and provides a path for the current during the off period.
Figure 14-20 shows the 8
resulting waveform at the output, for

7
duty cycles of 10%, 20% and 40%.

The average output voltage is simply 6
40
proportional to the duty-cycle, but 5
there is a noticeable ripple, the

Output / V
4
remains of the switching frequency
20
(100kHz). 3
There is also an overshoot, 2

10
which becomes more pronounced as
the duty-cycle increases. This 1
undesirable behavior is due to the LC 0

0 100 200 300 400 500
filter (L1, C1). Time/uSecs 100uSecs/div
With ideal components the Fig. 14-20: The resulting waveform at

voltage conversion is 100% efficient. the output.

But when you add some resistance to the switch and inductor and a forward
voltage drop for the diode, the efficiency drops. For example, with a total
resistance of just 50mΩ
Vcc
and a diode drop of
S1
0.3Volts (a Schottky
L1 diode) the efficiency is
Vreg
D1 27u
R1
94%.
Error Amp.
32k The circuit of
RLoad figure 14-19 is not a
R3 R2 4.7u 10
100kHz 100k 27k C1 regulator; we have to add
47n feedback to make the
C2 Vref
Triangle
1.2
output voltage immune to
supply fluctuations. This
is accomplished by
Fig. 14-21: "Buck" regulator.
amplifying the difference
between a fraction of the
output voltage (R1, R2)
and a reference voltage in an error amplifier. S1, an abstract simulation
symbol, is now used as both a switch and a comparator (with the on/off
thresholds set just a few millivolts apart). The output of the low-pass filter
(R3, C2) following the error amplifier is thus compared with a triangle
wave (100kHz, 2Vpp). In this way the regulator finds the duty cycle which
gives the desired output voltage. Such a circuit is generally called a Buck
Regulator.
There are a few items to 3
consider, which are peculiar to a
switching regulator: 2.5
First, an actual switch is not 2

Probe1-NODE / V
a perfect device; you will have to

make a painful compromise, 1.5
weighing voltage drop and speed: 1
the lower the voltage drop the

0.5
more current it takes to drive the
device. For example, a discrete 0
0 0.2 0.4 0.6 0.8 1
MOS transistor with an "on" Time/mSecs 200µSecs/div
resistance of 100mΩ at 1 Ampere

Fig. 14-22: Output voltage vs time.
has a total input capacitance of about
1nF. At a switching frequency of
100kHz you will need to turn the device on and off in less than 50nsec,
otherwise the dissipation during switching becomes significant. This means
the output of the comparator (the driver stage) has to provide 100mA to

charge and discharge 1nF. If you push the switching frequency to 500kHz,
this current increases to 0.5 Amperes.
Second, the current level that the switching transistor needs to
handle is always larger than the average output current. If you use a small
inductor, the peak current can exceed the average by a factor of three or
more; with a large inductance this factor is between 1.1 and 1.4.
Third, the voltage drop (and switching speed) of the diode is just as
important as that of the switching transistor, their peak currents are roughly
equal.
Fourth, the output LC filter (L1, C1) form a pole, which makes
frequency compensation (R3, C2) more challenging.
We can step up the voltage Supply

by using the induced voltage in an L1
10u
inductor. Switch S1 connects the
inductor L1 across the power supply D1
Output
(here assumed to be 1 Volt). The
current flowing through the inductor S1 C1
is given by: RLoad
25
PWM 47u
V ∗t
I=
L
Fig. 14-23: By using inductive charge the
As soon as the switch is output voltage can be made higher than
turned off, a positive voltage appears the supply voltage.
at the anode of the diode, created by
the stored current. This voltage is averaged by C1.
4 300
3.5 250
70 Percent Switch Current
3
200
D1-cathode / V
2.5
50 Percent
mA
150
2 Output Current
100
30 Percent
1.5
50
1
0
0 1 2 3 4 5
1.435 1.44 1.445 1.45 1.455 1.46
Fig. 14-24: Output voltage for three Fig. 14-25: Currents through switch and
different duty cycles. load.

The magnitude of the output voltage depends on how long the

inductor is charged (i.e. what peak current is reached). Thus, by changing
the duty cycle, the output voltage is altered. Note that in this configuration,
too, the current the switching device must handle is considerably larger than
the output current.
L1
Vcc (1 Volt)
Add feedback and we
10u
Output (2.5V)
have a Boost Regulator. As
D1 before, the switch symbol
Error Amplifier
R1 represents both the switch
32k
C1 RLoad
25
and a comparator (i.e. the
R3
S1
50k
47u switch turns on and off
R2
Triangle
C2
Vref
27k within a few millivolts of the
100n 1.2 differential input signal).
But be aware that, in this
Fig. 14-26: Boost switching regulator.
configuration, the feedback
circuitry must have some
specific characteristics: the
output of the error amplifier must be constrained so that it stays within the
amplitude of the triangle wave-form, otherwise the regulator can hang up at
either zero or full output.
The frequency compensation 2.5
network (R3, C2) also provides a

"soft start", i.e. the output voltage 2
builds up gradually, without much of

Output Voltage / V
1.5
an overshoot.
1
The same principle of using

0.5
the inductive "kickback" voltage is
also used to regulate larger voltages 00 2 4 6 8 10 12 14
(such as a 110V or 220V line input). Time/mSecs 2mSecs/div
The inductor becomes a transformer, Fig. 14-27: Soft-start of the boost

with a secondary winding delivering a regulator.
lower voltage (isolated from the line).
Feedback to the switching device is effected through an optical link (an
LED and a phototransistor) to also provide isolation.
Some of the devices in such a line regulator, including the switching
transistor, need to operate at high voltage; you need to be aware that this
increases device size considerably (see panel).

The Voltage Penalty

As we have seen in chapter 1 (figure 1-15), depletion layers take up space.
The higher the operating voltage, the wider the depletion layer. Thus the diffusions
not only need to be deeper, but also more widely spaced.
Just how serious is the penalty of using large voltages in an IC? Take a look
at the drawing below. It compares the required areas for minimum-geometry bipolar
transistors operating at 5, 20, 40 and 100 Volts:
Max. Voltage Dimensions, um Area Ratio
5 22x29 1
20 30x37 1.7
40 52x70 5.7
100 152x220 52.4
If only a small portion of the circuitry is required to withstand a high

voltage, you wouldn't want all of the devices to pay the price of large dimensions.
This then calls for a more complex process, one capable of producing both shallow
and narrow devices and deep and wide ones.
Linear Power Amplifiers
An ordinary amplification stage (e.g. figure 8-1) is categorized as

Class A. There is a steady DC current through the transistor and, in the
extreme, this current can be varied between zero and twice the idle value.
The power efficiency of such a stage is dismal: it can only reach 50% at
maximum output; with smaller signals it is much lower. In ordinary
amplification we usually don't care about efficiency, but when it comes to a
power output stage, class A is ill-suited.
In a Class B amplifier two output devices are used, one for the
positive-going signal and one for the negative half. There is no idle current,
each device starts to conduct as soon as the signal crosses the zero
threshold.

This is an idealized concept which does not really work in practice.

It is very difficult to switch from one device to the other without either
leaving a gap or having both devices conduct at the same time. The result is
distortion, which becomes very noticeable at low signal levels.
The solution is a compromise: allow a small idle current so that the
amplifier works in a class A mode with small signals and gradually moves
to class B as the signal increases. This operation is called Class AB.
Such an amplifier is
+12V
Q3 Q4 shown in figure 14-29.

Q5
The two output devices are
C1 Q10 and Q14. They are
Q8
50p
large, having an effective
10 Q10
R5
2.7k emitter length some 200
200
Q6
times that of a minimum
Q9
R6
5k
10
geometry transistor. Speaker
Input
Q1 Q2
R1 Ideally we would
Speaker
R2
1K
want one of the two output
29k 8
Q7
devices to be a PNP
Q11
transistor, to exploit the
Q12
10
I1 I2
R3
10k
complementary nature of
200
Q14
500u 1m
the "push-pull" output. But
Q13
SUBNPN transistors carry a
much higher current than
-12V
Fig. 14-29: 5-Watt bipolar class AB amplifier. PNP ones (unless a

complementary process is
available); with a 5.8 Watt output capability (requiring peak currents of
1.2A) this is no minor consideration.
To deliver the high output current, the upper stage (Q8, Q10) uses a
Darlington configuration. Q9 serves to by-pass leakage current at high
temperature.
The lower output stage has the identical Darlington connection plus
a PNP transistor. The entire four-transistor block behaves like a PNP
transistor. (All PNP transistors in this circuit are fairly large, capable of
carrying 3mA).
There are three base-emitter junctions between the base of Q8 and
the base of Q11. Between these two nodes a voltage is provided which
causes a few hundred microamperes of idle current to flow through the two
output transistors. This is done with the current I2 and transistors Q6 and
Q7. The VBE of Q6 is increased with the resistor divider R5/R6 to the
point where the desired current is reached. Notice that Q6 tracks the VBEs
of Q8 and Q10 and Q7 tracks that of Q11.

The feedback resistors R1/R2 30

set the gain at 30dB and C1 provides
20
frequency compensation. The slowest
device in the amplifier is the 10
Gain / dB
compound PNP transistor Q11 to Q14, 0
but it is fast enough to allow a more

-10
than sufficient frequency response for
an audio amplifier without creating -20
stability problems. 1k 10k 100k 1M 10M

One significant drawback of Frequency / Hertz
using only NPN power devices is

Fig. 14-30: Frequency response of
voltage drop. Only ±10 Volts are the class AB amplifier.
available at the output from the ±12 Volt
10
power supply without creating
distortion. At 10Vp, however, the
1 distortion amounts to only 0.15%.
The maximum efficiency of
Spectrum(Q12-C) / V
100m
an ideal Class B amplifier is 76%.
10m
For this circuit, with its 2-Volt drop
in each output device, the maximum
1m efficiency amounts to 62%. Thus
the output transistors produce 1.7
0.5 1 1.5 2 2.5 3 3.5 4 4.5
Watts of heat each (for a 5.6 Watt
Frequency/kHertz 500Hertz/div
output).
Fig. 14-31: Spectrum of the output signal
at full power. 70
60
It is often argued that, in 50
audio applications, peak power is 40

rarely required and so the heat sink
30
for the amplifier can be reduced in
20
size. Unfortunately, in a class B (or
AB) amplifier, peak dissipation 10
occurs not at peak output, but at 0

0 20 40 60 80 100
about 50% of maximum power.

Figure 14-32: Power dissipation vs.
The design of figure 14-29 power output in a class B amplifier.
requires a split power supply. There
are two ways to avoid this. We could convert the -12V connection to
ground, make Vcc 24 Volts, bias the input at 1/2 Vcc and couple the
speaker through a capacitor. The only problem with this approach is the
size of the new capacitor: 2000uF to get a 3dB drop-off at 10Hz.

+24V
A better solution is the Bridge
Output. In essence there are two
Output
amplifiers, 180 degrees out of phase. With
R1
no input signal, both output rest at 1/2 Vcc.
R2
As the signal appears, one output moves up,
Speaker
8
the other one down.
Input
In this configuration we have in fact
doubled the output swing. With the same
R4 Output
total supply voltage, 25 Watts of output are
generated (which requires four output
R3
transistors with a capability of 2.5A each).
Efficiency is unchanged at 62%, which
Fig. 14-33: Class AB amplifier with produces a power dissipation of 15.3 Watts.
bridge output.
Switching Power Amplifiers
+10V The goal is almost the same as that of

the series switching regulator: lower a
S1 voltage across a load without creating much
heat. There are two differences though: the
L1
output starts at zero and it can move in either
30u
Speaker the positive or negative direction.
SquareWave
RLoad
8
S2
10
8
-10V 4
2
Fig. 14-34: Bidirectional
V
0
switching arrangement. Output Voltage
-2
-4
To start with, let's use
-6
two power supplies. The two -8
switches connect the inductor -10
to either the positive or 0 5 10 15 20 25 30
negative rail. For now we Time/µSecs 5µSecs/div
assume that there is no dead Fig. 14-35: Switching and output wave-
time or overlap and that this forms.
switching action is instantaneous.

The value of the inductor is fairly large for the chosen switching
frequency (200kHz); it is never fully charged or fully discharged. Despite
this, there is still a substantial ripple at the output.
The average output voltage
900 is a function of the duty cycle. At
800 50% the output is zero; 75%
700
produces +5 Volts and 100% +10
Inductor Current / mA
600
Volts. Duty cycles of less than
500
50% cause the output to be
400
negative.
300
200
Notice that the current
100
gradually builds up (figure 14-36);
00 5 10 15 20 25 30
the time constant of this effect is
given by L1 and the 8-Ohm load (a
speaker), a factor which will
Fig. 14-36: Current through S1. become important when we close
the loop with feedback.
Let's now take the next step
+10V and modulate the duty cycle with a
S1 sine-wave signal, making a Class
D amplifier. As in the switching
Input
30u
Speake r regulators, the switch symbols also
act as comparators (i.e. the
L1
270n RLoad thresholds of the control terminals
S2
Triangle C1 8
are set so that the switches turn
from off to on (and from on to off)
within a few millivolts. Also (for
-10V
Fig. 14-37: Class D amplifier. 10
now) the switches are ideal, they have no 6
4
delay and insignificant resistance.
Output Voltage / V
Also, a filter capacitor (C1) has been 0
added; this reduces the 200kHz ripple -2
-4
but increases the build-up delay -6
mentioned above. -8
The output is now a sine-wave -10 1.2 1.4 1.6 1.8 2
with a small amount of 200kHz ripple. Time/mSecs

Fig. 14-38: Output wave-form.
200µSecs/div
Since we use near-perfect components,

the distortion is very small.

10 1
1 100m
Output Spectrum / V
Output Spectrum / V
100m 10m
10m 1m
1m 100µ
0.5 1 1.5 2 2.5 3 3.5 4 4.5 150 200 250 300 350 400 450
Frequency/kHertz 500Hertz/div Frequency/kHertz 50kHertz/div
Fig. 14-39: Frequency spectrum in the Fig. 14-40: Frequency spectrum in the
signal range. switching range.
Alas, if we only had

+10V
ideal components. In reality
D1
S1
the switches have resistance
and significant switching
Input Speaker
times. In addition, as pointed
30u
out on page 14-9, they require
L1
270n RLoad
painfully large drive power.
Triangle
S2 C1 8 In figure 14-41 the
D2
models are changed to
represent more practical
-10V
components. The switch
Fig. 14-41: Pulse-width modulated circuit with resistances, for example, result
more practical component models. The in larger and unequal voltage
diodes are now required to absorb the voltage
spikes.
drops (200mV for an N-
channel transistor, 300mV for
a P-channel one). In addition there is 10
a small dead-time to avoid both

1
devices being "on" at the same time.
Spectrum(Probe1-NODE) / V
This dead-time creates a voltage 100m
spike from the inductor, which 10m
makes D1 and D2 necessary.

1m
These small imperfections
have a significant impact on the 100µ
fidelity of the output signal: 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5
distortion increases to 1%. Frequency/kHertz 500Hertz/div
Unless we use faster

Fig. 14-42: Signal spectrum with
switching transistors with lower realistic components.
voltage drops and better matching, the

level of distortion can only be brought down with feedback. And that is
somewhat of a problem.
In order to reduce the
Y2 Y1
0
high-frequency components at
0 the output we used an LC filter.
-20
Phase It is dimensioned to be effective
-2
-40 at 200kHz, but it causes a phase
Phase / degrees
Amplitude / db
-60
-4 shift already in the audio range.
Amplitude Because of this, the amount of
-6
-80
feedback possible, using a single
-100 -8 feedback loop, is limited to
about 20dB. With two or even
-120 1k 2k 4k 10k 20k 40k 100k
three nested feedback loops this
Frequency / Hertz
figure increases to about 35dB.
Fig. 14-43: Amplitude and phase response of
Also, a loud-speaker is
the output filter. not really a simple resistor, there
is some inductance as well,
making the phase relationship in the feedback path even more complicated.
We could, of course, increase the switching frequency, which would
allow us to push the cutoff frequency of L1 and C1 higher, but the penalty
would be lower efficiency and an increase in drive requirements for the
switching transistors.
We have been assuming that we want a faithful (albeit larger)
reproduction of the input signal at the load. Strictly speaking, this is not
really true. In the case of an audio amplifier, the human ear cannot hear
200kHz, so filtering out high frequencies makes little difference. If the
application is a servo amplifier, the load is unlikely to respond to such rapid
fluctuations.
But there is radiation. Do we want to connect a square-wave of
200kHz (and its harmonics) across a long speaker cable and let it radiate
into AM receivers and other electronic equipment? The answer is a clear
no, and rules and regulations limiting such radiation have been written.
There are ways to reduce radiation. First, we can keep the speaker
wires short, moving the amplifier next to the speaker. Second we can vary
the switching frequency in a random fashion, creating a spread spectrum.
Although this does not reduce the total radiation, it at least makes it less
noticeable and allows meeting radiation limits.
For a given supply voltage and speaker impedance, the delivered

power can be increased by using a bridge output. In figure 14-44 there are
four switches. S1 and S4 are always "on" and "off" together, as are S2 and

S3. Thus the load is +10V
either connected to +V on S1
D1 D4
S3
the left side and -V on the
right, or vice versa. This Input Output
L1 L2
output
RLoad
effectively doubles the 15u 8 15u
supply voltage and the S2

C1 C2
S4
270n 270n
amplifier can deliver 25 D2 D3
Watts into an 8-Ohm -10V
load. There are four large

output transistors, Triangle
however, each of which
must carry up to 2.5
Amperes.
If we apply 40 Fig. 14-44: Class D amplifier with bridge output.
Volts total and use a 4-
Ohm speaker, the output
power grows to 196 Watts (and the peak current in the four output devices
to 10 Amperes).
+10V
But now
let's change the
S1 S3
D1 D4 circuit a little.
Input Output Output Instead of having
L1
RLoad
L2
the two outputs
8
15u
C1 C2
15u
move in opposite
S2
270n 270n
S4 direction, invert one
D2 D3 of the drives so that
-10V they move up an
down together. If
Imverter the input signal is
Triangle
zero, the two
outputs will move
at exactly the same
Fig. 14-45: Class D amplifier which suppresses the
time. Each output
fundamental of the switching frequency. then carries a
200kHz square-
wave, but between them there is no signal. As the input signal goes
positive, the duty-cycle of one output increases while the duty-cycle of the
other output decreases by the same amount. Thus, between the two outputs,
there is now a square-wave with a duty cycle amounting to the difference.

10
The effect on the
frequency spectrum is quite
1 drastic: the fundamental of the
switching frequency has
Output Spectrum / V
100m disappeared; we only need to

worry about the second
10m harmonic, which has a lower
amplitude and is easier to filter
1m out.
But let's not get too
100µ 100 150 200 250 300 350 400 450 500 enthusiastic here: the
fundamental of the switching
frequency is no longer present
when measured across the
Fig. 14-46: Radiation spectrum across the load in load, but the wires leading to
figure 14-45.
the load move up and down
together, at the rate of the
switching frequency. While this movement causes no current to flow
through the load, there is still capacitive radiation from the wires. Hence
C1 and C2 are needed.
A last word about class D amplifiers: simulation is very difficult

and time-consuming. Unless you have a highly specialized program, only
transient analysis can be used, which means you cannot obtain such
parameters as phase margin directly. You may be forced to simulate (and
integrate) the various blocks in pieces and then resort to old-fashioned
breadboarding.

Camenzind: Designing Analog Chips Chapter 15: A to D and D to A
15 A to D and D to A
The field of data converters is vast and still expanding. It would be

presumptuous to cover all of it in one chapter. For this reason only some of
the most often used approaches are discussed here.
Digital to Analog Converters
There is nothing very mysterious about most digital to analog

converters. Just take a look at the first figure. A string of identical resistors
divides a reference voltage into eight equal parts. Of eight MOS transistors
only one is on at a time, connecting the selected tap to the output.
Of course this is a very simple
Vref
R1
example, a grand-total of three bits. It
7/8 M1
gets a bit more complicated as you
R2 increase the number of bits; 256
3/4 M2 resistors and transistors are required for
R3
8 bits, 1024 for 10 and 4096 for 12.
5/8 M3
R4 Also, this DAC creates analog
1/2 M4 Analog Out
voltages of only one polarity; analog
R5
signals have the nasty habit of being
3/8
R6
M5 bipolar. To include negative-going
1/4
values we need to double the number of
M6
R7 resistors and add an identical negative
1/8
M7
reference voltage. Thus an 8-bit Divider
R8
DAC requires 512 resistor segments.
0
M8 For higher number of bits (and the
expected higher accuracy) the matching
Decoder of the resistors becomes the limiting
factor; not only does the number of
resistors increase but each resistor needs
Fig. 15-1: 3-bit Divider DAC. to be larger to obtain better matching.
And forget trimming: at 12 bits you
would have to trim each of the 8192

resistors.
Note that the full reference voltage does not get to the output. This
quirk is caused by the fact that a string of eight resistors has nine nodes.
We need to include zero, so three bits only reaches 7/8 of the total voltage.
To represent bipolar values some special codes are used. In the
"sign + magnitude" code a bit is added which represents just the polarity.
This is not the most efficient way and it is somewhat awkward (there are
two values for zero, 0000 and 1000).
The offset binary code Sign + Offset Twos
simply starts at the most Number Magnitude Binary Complement
negative number and counts up. +7 0111 1111 0111
Note that there is only one +6 0110 1110 0110
+5 0101 1101 0101
value for zero, but the full +4 0100 1100 0100
reference voltage is still not +3 0011 1011 0011
+2 0010 1010 0010
present. +1 0001 1001 0001
In the twos complement 0 0000 1000 0000
-1 1001 0111 1111
code, positive numbers are the -2 1010 0110 1110
same as in a binary code, with -3 1011 0101 1101
-4 1100 0100 1100
the additional sign bit. -5 1101 0011 1011
-6 1110 0010 1010
Negative numbers are the -7 1111 0001 1001
inverse or complement of the -8 0000 1000
positive ones, with a 1 added Fig. 15-2: Codes representing bipolar
and the sign-bit changed. values.
Other codes are also
used for DACs. In the BCD (binary coded decimal) code each decimal
digit is represented by four binary digits. BCD is primarily used for digital
voltmeters. The Gray Code changes only one bit at a time, a feature useful
in shaft encoders.
In any DAC, the output is strictly proportional to the reference
voltage; double it and the output will double. Thus if you treat the reference
terminal as an input, you have what is known as a multiplying DAC.
To increase the number of bits without exploding the number of

resistors we can move to a Segmented DAC. Figure 15-3 shows a simple
example for six bits, divided into three 2-bit segments. In this way we can
reduce the number of resistors from 64 to 12; for a full-fledged design
which delivers positive and negative values you would again need to double
these numbers.
The first segment selects a resistor rather than a tap and the
corresponding voltage drop is buffered and delivered to the second segment,
where the same process is repeated. In the last segment taps are again

delivered to the output. Notice that in this approach, too, the top of R9 is
not connected; a seventh bit would be required to allow that.
In such a segmented DAC the resistors in the first string (the most
significant bits) are the most critical. They should be largest in size to
obtain the best matching (or be trimmed).
It is crucial that a DAC be monotonic, i.e. as you step through the
code from low to high, the output always increases (it may not increase by
precisely the same amount, but at least it will never decrease). A divider
DAC is always monotonic. The same holds true for the segmented DAC,
provided each segment is monotonic (which is the case if we use dividers).
Vref +
+
R1 -
R5 -
R9
+ Analog Out
R2
R6 R10 -
R3
R7 R11
R4
R8
+ R12
+
-
-
Vref
Analog Out
MSB LSB
1 0 0 1 1 0
Fig. 15-3: 6-bit segmented DAC.
It is not necessary to use only identical resistors. Figure 15-4 shows

a 6-bit example of a DAC using binary-weighted resistors. Moving from
the most significant to the least significant bit, the resistors double in value
each time, thus no decoding circuitry is required.
Only one resistor (and transistor) is required per bit but the saving is
largely an illusion. To get good matching, you would need to design all

resistors with 1R
-Vref
identical segments M1
(1R), which amounts M2

2R
1/2 R
to 63 resistors, one 4R Analog Output
less than a simple M3
resistor string. In M4
8R
-
addition, the resistor +
16R
for the most M5
significant bit 32R

M6
influences accuracy
the most, so it should
MSB LSB
be larger than the
others. Also, the
Fig. 15-4: DAC with binary weighted resistors.
transistors carry
current, so their
resistances appear in series with the binary weighted resistors. This means
that M1 should not only be very large, but it should be 32 times the size of
M6.
A somewhat better idea is the R-2R (Ladder) DAC. Just two

resistor values are used and the bit lines need not be decoded.
With the most-significant bit high, the first 2R resistor is connected
between Vref and the input of the op-amp; all other 2R resistors are
connected to ground. Each subsequent bit has half the influence on the
output as the previous one.
Vref
R R R
This is an
2R 2R 2R inverting
2R
2R
amplifier, so the
output goes R
negative with a
positive reference -
voltage. +
Analog Out
Using
MSB LSB only two resistor
Fig. 15-5: DAC with R-2R ladder.
values improves
matching and
trimming is
easier. Note, however, that the MOS transistors carry current and their
resistance is critical. Moving from left to right, the current drops by 50% in
each stage. Thus, to get the smallest error, the transistor size should be
doubled for each stage moving from right to left.

In many DACs the analog voltage is created not by voltage taps but
by currents. An example of a much simplified current DAC is shown in
figure 15-6. A primary current is generated by R10 from a reference
voltage; with Vref at 1 Volts, this current amounts to 200uA. Q1 through
Q6, being biased from Q1, each produce a fraction of this current, Q2
+V 100uA, Q3 50uA, Q4
R11
10k 25uA and Q5 12.5uA.
Vref Analog Out
Q6 is used to terminate
R10
5k the ladder.
S w i t c h e s These binary-
weighted currents are
+
Q1 Q2 Q3 Q4 Q5 Q6 then switched to either
-
16 8 4
R11 or +V (by, for
example, a differential
R1
1k
R2
2k
R4
2k
R6
2k
R8
2k
R9
2k pair, acting as logic
-V
R3 R5 R7 inputs). Note that the
1k 1k 1k
currents are flowing all
Fig. 15-6: Bipolar current DAC with R-2R ladder. the time, which makes
this a fairly power-
hungry approach.
You can, of course use the current directly as the output. But note
that, if R10 and R11 are both inside the IC, their temperature coefficients
and absolute variations will cancel.
Don't let this simplified example mislead you; there are many
sources of error which require fine attention to detail. In a bipolar circuit
there are base currents which must be compensated lest they subtract as
much as 1% from the ideal values of the binary (collector) currents. And
each collector must be at exactly the same potential as Q1 (here ground).
Lastly, if bipolar
+V
switches are used, they, R11
10k
too, will have base Analog Out
Vref
currents which also R10
must be rendered 5k
S w i t c h e s
harmless. MSB LSB
Although it +
M1
16
M2
8
M3
4
M4
2
M5
1
M6
1
started out that way, a -
R1 R2 R4 R6 R8 R9
current DAC is no 1k 2k 2k 2k 2k 2k
longer primarily a -V
R3
1k
R5
1k
R7
1k
bipolar affair; in fact

Fig. 15-7: CMOS current DAC with R-2R ladder.

CMOS has some significant advantages here. There are no base currents,
therefore no base current errors. However, the drain voltages still need to
be at identical levels, otherwise the Early effect will cause substantial
deviation.
The number of bits is limited by the matching of the resistors and

the sizes of the transistors. At eight bits M1 would consist of 512
transistors the size of M5 and M6. The latter two are already going to be far
larger than minimum size to ameliorate the Early effect (making the channel
long) and get acceptable matching (making the channel wide and long).
512 of these (twice as many for both polarities) make the area painfully
large.
There is a way out of this limitation: segmentation. In our example
+V
R11
10k
Analog Out
S w i t ch e s
Vref MSB LSB

Bias
R10
5k
M7 M8 M9 M10 M11
8 4 2 1 1
M1 M2 M3 M4 M5 M6
+
16 8 4 2 1 1
-
R1 R2 R4 R6 R8 R9
1k 2k 2k 2k 2k 2k
R3 R5 R7
-V
1k 1k 1k
Fig. 15-8: Segmented current DAC.
the last transistor is only used for terminating the resistor ladder. It carries
the same current as the least significant bit, 12.5uA. Use it and split it into
16 equal parts, 8 used for 5th bit, 4 for the 6th, 2 for the 7th and 1 each for
the 8th bit and a dummy transistor.
Simple transistor ratios are used for this extension. We could have
also employed another R-2R resistor ladder but, since these are the least
significant bits, the accuracy is most likely sufficient.

Analog to Digital Converters
Analog In As in DACs, the divider analog to

Vref
R1
digital converter is the fastest and most
+ simple approach. Shown here for just three
- bits, there are eight comparators with one
R2
+
input connected to a resistor tap and the
- other to the analog input. Wherever the
R3
+
analog signal exceeds the potential at the
-
tap, the output of the comparator goes high;
R4 the comparator outputs are decoded into
+
three bits. If the input can be both positive
-
R5 and negative, twice as many resistors and

+
comparators are needed, as well as a second
-
R6
reference voltage with an equal but
+ negative value.
- All comparators operate
R7
+
simultaneously, so the speed of the
- converter is given by the speed of the
R8
+
comparators alone.
-
The disadvantage of this approach is
again complexity with large number of bits,
Fig. 15-9: Divider ADC.
with an accompanying high power
consumption. At eight bits 512 resistors
and comparators are required (assuming a bipolar input); at 12 bits the
number increases to 8192. Also note that all comparator inputs are in
parallel, which makes for a rather large input capacitance.
The Successive
Approximation ADC DAC
Vref
reduces the number of

Comparator
comparators to one, though Analog
Digital Output
In
the number of resistors
+
Sample
-
and Hold
remains unchanged (Figure
15-10). Here a sample of Encoder
the analog signal is taken Register, Control Logic
and held steady while the

conversion takes place. Fig. 15-10: Successive approximation ADC.
The heart of the ADC is a

DAC. The control logic sets the DAC through a register to a likely value
initially. If the value is too high, the register is moved down; if the initial
guess is too low, the register is moved up. After a few steps the correct
setting is found and the conversion stops.
All this guessing and stepping takes time, thus a successive
approximation ADC is considerably slower than the divider approach,
though it consumes less current and takes up a smaller area.
In both approaches the accuracy is limited by the resistor (or
capacitor) divider, as was pointed out in the DAC section.
The Delta-Sigma Converter
Most engineers find explanations of the sigma-delta converter

almost incomprehensible. There is a reason for this: terms are used which
are quite non-descriptive and often misleading.
Take a look at a
conventional diagram for a first-
order delta-sigma ADC (Figure 15-
11). This circuits has a "one-bit"
output, which is more a riddle than
a description Figure 15-12 shows
the same function with more
familiar blocks, which makes the
circuit far easier to understand. Fig. 15-11: Conventional diagram for a
delta-sigma converter.
C1
R1
50k 10p
Analog In
R2 - Comp.
Pulse
50k
Train
+
Timer
Integrator
S1
Bias
1usec
0
Vref
2
Fig. 15-2: First-order delta-sigma ADC with more familiar blocks.
The object is to produce a train of logic pulses at the output whose

frequency is proportional to the (analog) input voltage. Counting the

number of pulses for a given time interval then gives the equivalent digital
value, i.e. this is a voltage to frequency converter.
Let's start on the left. There are two resistors leading to the input of
an integrator. R2 is connected through a switch to a negative reference
voltage (of 2 Volts), while R1 responds to the input signal (with a range of
0 to 1 Volt). If switch S1 is open, the positive input voltage causes the
output of the integrator to move negative at a rate given by R1 and C1 (this
is an inverting integrator).
The following comparator then triggers a timer when this falling
voltage reaches the bias level (which is set here at zero volts but can be any
convenient level). The timer produces a short pulse (e.g. 1usec) which is
delivered to the output.
This pulse also closes the switch. Since the two resistors are equal
in value (an arbitrary choice) and Vref is at least twice the value of the input
voltage, the integrator reverses during this time and its output moves up.
If the input voltage is 1 Volt, the output of the integrator moves
positive during the pulse by exactly the same amount as it has moved
negative while the switch was off. Thus the duty cycle is 50% and the
frequency 500kHz (remember that R1 is connected all the time, while R2 is
connected only half the time, hence Vref needs to be at twice the level of
the maximum input signal).
If we lower the input signal to 100mV, the falling portion of the
integrator output becomes longer (while the rising portion remains constant)
and the frequency drops to 50kHz. At 10mV input the frequency is 5kHz
and at 1mV 500Hz. At zero input the oscillation stops entirely.
As in the examples above, this circuit can only handle positive input
voltages. For a bipolar input (say ± 1 Volt), R2 is switched between two
reference voltages, +2V and -2V.
So, the mysterious "1 Bit DAC" turns out to be nothing more than a
switch and one or two reference voltages, the "Latched Comparator" a timer
triggered by a comparator and the "Summer" two resistors (it actually is a
subtractor). The "delta-sigma modulator" (which purists insist should not
be called a sigma-delta modulator) is simply a voltage to frequency
converter. And the "1 Bit Output" translates into serial output.
For accuracy two factors are of overwhelming importance: the
reference voltage and the pulse-width. Reference voltages can be trimmed
and the pulse-width can be derived from a crystal-controlled clock. All
other elements are of secondary importance. R1 and R2 need to match well,
but their absolute values (and that of C1) only affect the height of the
triangle wave at the output of the integrator, not the timing (the rising and

falling flanks of the triangle wave are equally affected and thus cancel out).
A high loop gain in the integrator op-amp assures that the voltage
fluctuation at its input is down to a few microvolts (but its offset voltage
still matters).
The performance of a delta-sigma ADC can be improved by adding
one (or more) feedback
loops (Figure 15-13,
shown again in the
conventional way). Be
aware, however, that
the higher the order, the
less stable the design
becomes. A third-order
delta-sigma ADC can
oscillate in some Fig. 15-13: Second-order Delta-Sigma ADC.
unexpected ways.
The significant advantage of the delta-sigma ADC is its capacity for
resolution. These circuits are often called "oversampling ADCs", because
they must sample the incoming waveform above the Nyquist rate (twice the
maximum input frequency). For example, if you want to capture a 1kHz
signal with an 8-bit resolution, the maximum frequency must be at least
2kHz times 256, or 512kHz. At 12 bits this frequency increases to 8.2MHz.
However, this presumes that we do nothing else than counting
pulses at the output, which ignores much of the concept's capability. The
delta-sigma ADC was made for CMOS and with today's small geometries a
great deal of digital signal processing can be done once the pulses exist.
Apart from increasing the resolution, the sampling noise (which is already
centered around a rather high clock frequency) can be brought down to
stunningly low levels with a sophisticated digital low-pass filter (called a
"decimation" filter).
With these additional measures, a second-order delta-sigma ADC
with a signal bandwidth of 4kHz can achieve a 14-bit resolution with 85dB
signal to noise ratio, using a clock frequency of 1MHz.

Camenzind: Designing Analog Chips Chapter 16: Odds and Ends
16 Odds and Ends
In this, the last circuit design chapter, we look at six functions which
did not fit well into the previous subjects.
As pointed out before, be aware that you will need to re-simulate
these circuits with models specific to the process to be used.
The Gilbert Cell

Vcc
An unusual and brilliant idea:
Take two current mirrors and connect
them in a differential way. Run the inner I2 I3
pair at a higher current than the diode- 50u 50u
connected transistors and you get gain, Q2 Q3

roughly in the ratio of the currents. I2 and Q1 Q4
I3 are modulated, the collector currents of
I1
Q2 and Q3 are the outputs. 1m
Since this is a current in/current
out scheme, the cell is fast (no Miller
effect). Fig. 16-1: The first form of a
Gilbert cell.
In the second form of the Gilbert
Vcc cell all three currents
Vcc
flow to the negative
rail, which allows
stacking: use the
collector currents as
Q1 Q4 Q1 Q4
Q3
the inputs for the next
Q2 Q2 Q3
cell. Each subsequent
cell is biased at a
I2 I1 I3
50u 1m 50u
I2 I1 I3 higher DC potential to
50u
50u 1m
avoid saturating any of
the transistors.
In both forms
Fig. 16-2: Second form of Fig. 16-3: And the third there is a small error
the Gilbert cell. form of the Gilbert cell. due to the base

currents, which is largely eliminated in the third form.

Alas, all this is true only in an isolated, theoretical analysis. It is
very rare that you start out with a differential current input. In most
applications there is an input voltage, and single-ended at that. So, to use
the Gilbert cell, you need to convert this voltage into a differential current,
for example with a differential pair, as is
5V
R1 R2
shown in figure 16-4.
4k 4k And here is where the Gilbert cell
falls down. As shown in figure 16-5, a
2.5V
differential pair actually has a higher gain
and wider frequency response (if operated
Q1 Q4
at I1) without the Gilbert cell. Which is
Q2 Q3
why it is rarely used. This is not due to
I1 the fact that the current is converted into a
1m
1.2V
voltage at the output (and thus the Miller
Vin Q5 Q6 effect is right back in the picture), but
simply because Q1 and Q4 need to run at
I2
a lower current.
100u
34
Fig. 16-4: A practical application of
the Gilbert cell. 32
With Gilbert Cell
Differential Gain / dB
30
This problem is made
Differential Pair Only
worse by stacking several cells, 28
requiring a wide range of 26

current levels. In today's
24
power-conscious and low-
voltage environment the 22
Gilbert cell has become 1k 10k 100k 1M 10M 100M

outdated. Frequency / Hertz
Fig. 16-5: In most applications the Gilbert cell

does not actually enhance performance.

Multipliers
+V
We have seen a similar circuit
R3 R4
60k 60k before, used as a phase detector for a
Out PLL. While accuracy in that application
Out was of minor importance, in a multiplier
it is the main feature,
V2 Q3 Q4 Q5 Q6
The circuit requires a split power
R5
10k
R6
10k
R7
10k
R8
10k
supply (e.g. ± 5 Volts), so that at least
one input (V1) can be at ground level.
The second input (V2) is biased safely
V1 Q1 2.5V
Q2
higher (2.5V) to avoid saturating Q1
and Q2.
R1 R2 It is the insertion of resistors in
10k 10k
the emitters of all six transistors that
I1
100u SUB gives this multiplier its accuracy. Their
-V
values need to be large compared to the
dynamic emitter resistance (re, see page
Fig. 16-6: Simple four-quadrant
multiplier. 4-1).
Such a circuit is 10
called a four-quadrant 8
V2 = 100mV
multiplier because it 6
produces an output for all 4

Differential Output / mV
four quadrants of a plot: 1. 2

V2 = 50mV
both inputs positive; 2. V1 0
positive, V2 negative; 3. both -2
V2 = 0 V2 = -50mV
inputs negative and 4. V1 -4

negative, V2 positive (where
-6
the value of V2 is applied V2 = -100mV
-8
with respect to 2.5V),
The range of the two -100 -80 -60 -40 -20 0 20 40 60 80 100
input voltages is ± 100mV, V1/mV 20mV/div
resulting in a maximum Fig. 16-7: Behavior of the four-quadrant multiplier.

output of ± 10mV. This limits
the achievable accuracy since
matching of VBEs becomes as important a factor as matching of the
resistors. A higher positive supply voltage is needed to allow input and
output ranges of ± 1 Volt.

As shown, the error can be as high as ± 5% untrimmed and ± 1%

trimmed. With a higher supply and trimmed thin-film resistors ± 0.3% is
possible.
+5V
By adding two
R7 R8 R9
10k 20k 20k transistors and biasing the
Out upper quad (Q7 to Q10) with
Out diode-connected transistors
Q5 Q6 Q7 Q8 Q9 Q10 (Q5, Q6, sitting at a DC
potential set by R7), both
input can be at ground level.
Also, the ranges of the two
V1 Q1 Q2 V2 Q3 Q4
inputs and the output are
R1 R2 R3 R4 now extended to ± 1 Volt.
5k 5k 5k 5k
R5 R6
Accuracy is unchanged for
9k 9k untrimmed operation; with
100u
I1
100u
I2
100u
I3
100u
I4
trimmed thin-film resistors
SUB
-5V
and additional temperature
Fig. 16-8: Four-quadrant multiplier with both input
compensation (see reference)
voltages at ground level. such a circuit can be brought
to within 0.1%.
Figure 16-9 +1.5V
shows the equivalent R7

20k
R8
20k
R9
20k
circuit in CMOS,
Out
designed for a 0.35u
Out
process. Because of the M5 M6 M7 M8 M9 M10
lower supply voltages

the range of the input W=20u W=20u
L=0.5u L=0.5u
W=20u
L=0.5u
W=20u
L=0.5u
W=20u
L=0.5u
W=20u
L=0.5u
voltages is again limited M=4 M=4 M=4 M=4 M=4 M=4
to ± 100mV.
This circuit M1 M2 M3 M4
illustrates the V1 V2
performance limitations W=20u W=20u W=20u W=20u

L=0.5u L=0.5u L=0.5u L=0.5u
imposed by low supply M=4 M=4 M=4 M=4
voltages. With offset R1

10k
R2
10k
R3
10k
R4
10k
voltages generally R5 R6
being higher in CMOS 19.1k 19.1k
and the maximum I1 I2 I3 I4

10u 10u
output range a mere ± 10u 10u
-1.5V
10mV, untrimmed
accuracy is no better
Fig. 16-9: Four-quadrant CMOS multiplier.
than about ± 10%. You

can, of course, change the resistor ratios so that the relationship between
inputs and output is multiplied by a constant.
Peak Detectors
Peak detectors tend to be a bit tricky. A surprising number of the

schemes using an op-amp and a diode tend toward oscillation or other
misbehavior.
When you analyze the feedback loop, you find that the diode and the
capacitor at the output place an unusual burden on the op-amp. When the
signal moves up (for a positive peak detector) the output is connected to a
large capacitance. When the signal moves down, there is no load at all.
The circuit in
+5V figure 16-10 uses a bipolar
I1 I2
Q5 Darlington pair to provide
10u 10u Q6
a high-impedance input at
the (external) capacitor.
Q7
For operation over a wide
R3
10k
temperature range the
In
R2
outer transistors (Q1, Q4)
Q1 Q4
20k
Peak
are biased at about 0.8uA
Q2 Q3
D1 by Q9 and Q11.
C1
The output
Q13
Q12
100n impedance of the op amp
is artificially enlarged by
Q9 Q10 R3 to provide frequency
Q8 Q11 compensation (together
with C1).
R1
SUB 50k -5V
There is a
fundamental question to
every peak detector: How
Fig. 16-10: Peak detector with Differential NPN long should the voltage
Darlington pair.
stay on the capacitor? If
the answer is "forever"
then the detector displays the highest peak for an infinite history of input
signals, which is probably not what you want. For any other answer you
have two choices: either discharge C1 slowly, so the voltage stays within
the desired accuracy over the time of interest, or reset C1 before each
measurement.

In our circuit the capacitor is discharged by the base current of Q4.

This current amounts to about 5nA. If the peak voltage is 1 Volt, you lose
about 1% in 200msec with 100nF of capacitance. The discharge current
varies from chip to chip and with temperature.
Figure 16-11 shows a peak detector which operates from a single
supply voltage. The Darlington input pair of the op-amp is more elaborate
and the operating
+5V
currents of the
outer transistors I3 I1 I4 I2
10u 10u 10u 10u

(Q1, Q6) are
merely the base Q3 Q4
Q10
currents of the Q2 Q5 R3
inner ones. This In
10k
R2
limits the Q1 Q6
Peak
20k
temperature range D1
Q9
(to about 100oC)
C1
but lowers the Q7 Q8 R1
10Meg
100n
input current. SUB
Notice the
discharge resistor
R1. Without it, Fig. 16-11: Single-supply peak detector with a lower input
current.
the base current of
Q6 would charge C1 (it flows out of the base). Thus, in this circuit, a
controlled rate of discharge through R1 is essential.
+1.8V
In both examples the supply
I2 voltage must be lower than the
10u M6 emitter-base breakdown voltage of
I1
the output transistor. If it is to be
10u
W=10u
L=0.35u
higher, use an additional diode in
R1 series with the emitter.
1k
In M1 M2 CMOS devices are much
Peak better suited for peak detector
W=10u
L=2u
W=10u
L=2u M5 design than bipolar ones for two
C1 reasons: 1) there is no (DC) input
M3 M4
W=5u
L=5u
100n current and 2) you can reset a
M=2
capacitor to zero volts (the
W=5u
L=5u
W=5u
L=5u
collector-emitter voltage of bipolar
transistors does not go to zero, there
is always a remaining voltage of
Fig. 16-12: CMOS peak detector. about 100 or 150mV).
As in the bipolar examples,

the feedback loop is compensated with a resistor in the output path, working
together with Cext.
Since there is no input current, C1 can be made quite small, to the
point where it can be internal. But be aware that the smaller C1 the more
difficult it becomes to compensate the feedback loop.
Rectifiers and Averaging Circuits
R2 Figure 16-13 shows the standard

D1
20k
configuration for a half-wave rectifier,
appearing without much comment in
AC
R1
dozens of text-books, usually without
- D2
20k mentioning that it does not work well with
+
Out many op-amps.
Putting a diode in the feedback
Fig. 16-13: Standard op-amp half- path is awfully hard on the op-amp. The
wave rectifier. +5V
Q11 Q12
abrupt impedance change Q13
around zero signal level can

easily cause spikes and damped 10u
I1
oscillation, affecting the Q3 Q4 Q10
accuracy. Specifically Q2 Q5
Out
designed circuits avoid this -
AC Q1 Q6
and require only a single C1
supply voltage. 10p
Q9
R1
1 2k
0.6 Q7 Q8
0.2
In / V
SUB
-0.2
-0.6
-1
Fig. 16-14: Bipolar half-wave rectifier.
1.8
1.4
In the circuit of figure 16-14
Out / V
1
0.8 the output is at ground (without an
0.4
input signal), held there by R1. If the
00 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2
input moves above ground, the output
follows. But if the input goes
Fig. 16-15: Input and output waveforms. negative, there is nothing in the output
stage that can pull it below ground, so
it just stays there.

The value of R1 must be low enough to keep the voltage drop due to
the base current of Q6 low. This resistor cannot be replaced with a current
sink; the minimum collector-emitter voltage of an NPN transistor is too
high.
You can capacitively couple the input signal, with a resistor
connected from the input terminal to ground to provide a dc path.
Minimum required supply voltage for a 1-Volt input range is 3.5V.
In figure 16-16
an inverting op-amp R1
10k
Vcc
configuration with a Q9 Q10

gain of 1 is used, but it Q11
Q8
only works for
negative-going input I1
signals. As the signal 10u Q2 Q3
Out
moves above ground, Q1 Q4
R3
25k
the op-amp is R2 10p
effectively disabled. 25k C1
Thus the output simply Q7
follows the input. To SUB

Q5 Q6
avoid loading down the AC
output, a buffer needs to

be used. As it happens,
the circuit in figure 16- Fig. 16-16: A full-wave rectifier.
14 is an excellent
candidate for this job.
Q10 gives a small
0.8
0.6 operating current to Q1 and Q4
0.4
(about 1.7uA). Without this,
In / V
-0
-0.2 frequency compensation of the
-0.4
-0.6 op-amp becomes very difficult.
-1 Minimum supply voltage
1.8
1.6
for a 1Vp input is 2 Volts.
1.4
Out / V
1.2
0.8
Both of these circuits can
0.6
0.4
be readily translated into
00
CMOS. The half-wave rectifier
0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2
in figure 16-18 uses two
Time/mSecs
Fig. 16-17: Input and output waveforms200µSecs/div
for the advantages of CMOS: first,
full-wave rectifier.
there is no base current, so the
output pull-down impedance can be quite high; second, a current sink can
be used at the output instead of a resistor.

With a 1-Volt input range this circuit works down to 1.8V supply at
-40 C, 1.6V at 0oC.
o
The full-wave rectifier of figure 16-19 only needs a 1-Volt supply

for the same input range.
+3.3V
I1 I2 I3 I4
10u 10u 10u 10u
M8
M2 M3
1p W=10u
W=10u W=10u C1 L=0.35u
AC M1 L=0.35u L=0.35u M6 Out
W=10u W=10u
L=0.35u L=0.35u
M7 M9
M4 M5
W=5u W=10u
W=5u W=5u L=2u L=0.35u
L=2u L=2u M=2
Fig. 16-18: CMOS half-wave rectifier with a single supply.
+3.3V
I2 I4
10u
10u
M6
C1
W=10u
L=0.35u
M1 M2 1p
R1
20k
W=10u W=10u
L=0.35u L=0.35u M5 Out
M3 M4 R2 W=5u
20k L=0.35u
M=2
W=5u W=5u
L=0.35u L=0.35u
AC
Fig. 16-19: Single-supply CMOS full-wave rectifier.

Averaging the obtained rectified fundamentally takes time; the longer the
time constant, the smaller
the ripple (but there will
700
always be a ripple).
600
Full-Wave
Take the most
Rectifier simple approach, a single
500
low-pass filter (RC)
400 connected to the output. A
mV
full-wave output has the

300
Half-Wave advantage, producing less
Rectifier ripple. The time constant
200
used here is 10msec and
100
the signal is 1kHz.
00 20 40 60 80 100
To reduce the ripple
you can increase the time
constant (which takes
longer to reach the final
Fig. 16-20: Time constant and ripple for a level), or use a higher-
one-pole low-pass filter used for averaging.
order filter.
Thermometers
The PTAT (proportional to absolute temperature) current source has

come up before (see page 5-4) . It is unusual 2.5V
and remarkable that we are able to produce a R3

15k
R4
15k
R5
15k
voltage whose value is directly tied to the
Q6
absolute temperature scale and whose accuracy Q5 Q7
depends only on ratios, not affected by any
D1
process parameter. 1mV/K
Figure 16-21 shows such a circuit. Q1

through Q6 form a loop, started up by leakage Q3 Q4
alone (see page 5-6). For safety (in case the

models are not quite correct) a substantial Q1 Q2
R2
24
junction (D1) can be added, which has more R1
13.8k
leakage current than any of the other devices. SUB

3.75k
The current in the loop is determined by

the emitter ratios of Q2 to Q1 and R1. Recall the
formula on page 5-3: Fig. 16-21: Thermometer
with Kelvin scale.

k∗ T  A1∗ I 2 
deltaVBE = ∗ ln  
q  A2∗ I1
I1 and I2 are identical (as produced by Q5, Q6, R3 and R4) and the
area ratio is 24. Thus deltaVBE amounts to roughly 83mV at 300K. Since
T is in Kelvin, the current increases linearly from zero at absolute zero to
22uA at 300K. This current is then mirrored by Q7 and causes a voltage
drop across R2. With the values chosen (and perfect matching), the output
voltage amounts to 1mV per Kelvin. Note that any temperature coefficient
or absolute variation in R1 is eliminated by a matching R2.
Although the design is relatively insensitive to power supply
variation, accuracy is maximized by powering the thermometer from a
reference voltage.
Matching is the all-important factor here. A ±1% resistor matching
variation will result in an error of ±3oC at room temperature. Adding
mismatching of VBE and hFE, you must expect a variation of up to ±5oC
untrimmed. With trimming an accuracy of ±0.5oC is possible.
2.5V The centigrade (or Celsius) scale is

R3 R4 R5
15k 15k 15k the same as the Kelvin one, except
Q6
for the zero set to 273.16K. So, all
Q5 Q7
R6
36.675k
we need to do is to create an offset
D1
voltage of 273.16mV and read the
1mV/K
temperature differentially.
(Similarly we can create a
Q3 273.16mV
Q4
Fahrenheit scale by increasing R2 by
a factor of 1.8 and setting the offset
Q1 Q2
R2 R7 to 459.67mV).
24 13.8k 4.5k
R1 Trimming is straightforward:
SUB
3.75k
R2 sets the slope; trim it to read
293.16mV at 20oC at the upper
Fig 16-22: A thermometer with a
terminal; R6 sets 0oC; trim it to read
Celsius scale. 273.16mV at the lower terminal, also
at 20oC.
As we have seen in chapter 7, substrate PNP transistors can be used

in CMOS to create a delta-VBE. Figure 16-23 uses this approach to
produce a Kelvin output. The current mirror is that of figure 3-25.
The untrimmed accuracy is somewhat worse in CMOS because of
the poorer matching of the transistors (for the same area), about ± 7oC at

2.5V
room temperature. You can improve this
M3 M5 M7
by using a larger emitter ratio for Q2/Q1
W=20u W=20u W=20u and generally larger devices.
L=5u L=5u L=5u
M4 M6 M8 But let's not forget the lowly diode. Its

forward voltage has a predictable
temperature dependence (about -2mV/oC).
W=20u W=20u W=20u
L=2u L=2u L=2u
M=5 M=5 M=5
The slope is subject to absolute variation
R3
10k
and not quite as linear as that of a delta-
1 m V/K
VBE, but the device is nevertheless useful
in some applications. For example, if you
M1 M2
want to evaluate the temperature at a
W=20u W=20u
particular spot on an IC (say next to a
D1
L=10u L=10u
power device), use a
R1 R2
5k 25k diode-connected
transistor and connect
Q1 Q2
1 10
it to a small probing
pad. You can then
calibrate it first Fig. 16-24:
without powering up Diode
Fig. 16-23: CMOS Thermometer. thermometers
the chip.
.
Zero-Crossing Detectors
Suppose you need to start a timer or counter at the exact moment

when the line voltage crosses the zero line. How do you determine this
point without bringing the line voltage into the IC? A simple external
resistor will do the trick.
Vcc In a bipolar
Q2 Q8
Q7 design you can use the
(usually unpleasant)
Pulse
In fact that a transistor
Q5 Q6
AC
Rext pair used in the first
470k
V1 Q10 stage can cut off the
10u
Q1 I1 200m
Q9
transistor following in
Q3 Q4
the second stage. In
figure 16-25 one input
SUB
of a differential pair is
biased slightly above
Fig. 16-25: Bipolar zero-crossing detector. ground, at about

200mV (derived with a voltage divider from either a reference voltage or

from the supply). When the other input is above 200mV, Q9 is turned off
and the output is low. As you lower the input voltage, the output goes high
at 200mV, when Q5 and Q9 turn on; but as the input drops below ground,
Q5 cuts off Q9 and the output drops again. In other words: there is a small
window at ground level where the output goes high, otherwise it is always
low.
Q1 clamps the positive-going AC voltage so it can do no damage to
the IC. The negative-going waveform is automatically clamped by base-
substrate diode of Q5. The power dissipation in the external resistor is
25mW.
Be prepared for a surprise
when you simulate such a circuit: 3.5
at first you can't see the output 3
pulse, because it is very small 2.5
and short compared to the AC 2
waveform.
V
1.5
With 110V and Rext = 1
470kΩ, the pulse is about 5usec 0.5
wide. You get the same width at 0

220V if you double the value of
8.24 8.26 8.28 8.3 8.32 8.34 8.36 8.38 8.4 8.42
Rext.
The circuit works with a
supply as low as 1.2 Volts.
Fig. 16-26: AC slope and output pulse.
The effect used to create the window does not work well in CMOS.
Instead we can employ two comparators, one biased at about +200mV (M9,
M10) and the other at ground (figure 16-27). Their outputs are then
supplied to an "and" gate (M17, M18), which drives the output.
The AC waveform is clamped in the positive direction by two
"diode-connected" transistors (M1, M2) and in the negative direction by a
substrate diode.
Since there is no base current, you could theoretically make Rext.
very large. But also consider that the devices connected to the input
(including the pad and the ESD protection device) have a small amount of
capacitance. The time constant formed by the external resistor and this
capacitance must be smaller than the desired pulse-width.

1.8V
M3 M4 M8 M12 M14 M16
W=1u W=1u W=1u W=1u W=1u W=1u

L=0.18u L=0.18u L=0.18u L=0.18u L=0.18u L=0.18u M19
W=2u
M9 M10 L=0.5u
W=10u W=10u M20 Pulse

In V1 M17
L=0.18u L=0.18u
M5 M6
AC Rext
200m W=1u
1Meg W=2u L=0.5u
W=10u W=10u L=0.18u
M1 L=0.18u L=0.18u M11 M13 M=2
D1
W=10u 10u W=2u W=2u M18

L=5u I1 L=0.18u L=0.18u
M=2
M7 M15 W=2u
M2 L=0.18u
M=2
W=2u W=2u
W=10u L=0.18u L=0.18u
L=0.5u M=2
SUB
Fig. 16-27: CMOS version of zero-crossing detector.

Camenzind: Designing Analog Chips Chapter 17: Layout
17 Layout
The layout of analog ICs has so far remained an art, there are no
computer programs which could design, place and route the components in
an intelligent, competent way. And, more often than not, the person who
created the circuit diagram needs to (or should) get involved.
This chapter is by no means a complete guide; it would take an
entire book to do the subject justice. Look at it as some hints stemming
from practical experience.
Bipolar Transistors
The minimum sequence of masks in

a bipolar process is:
Buried Layer
Isolation
Sinker
Base
Emitter (N+)
Contact
Pad
The last mask opens up windows
over the bonding pads in a thick glass layer
which is spread over the entire circuit to
protect the delicate metal.
Fig. 17-1: Mask layers for an
NPN transistor.
Note that the emitter (N+) mask is
also used to make a low-resistance contact
to the collector (the epitaxial layer).
To these seven basic masks several other may be added:
A second (often identical) isolation mask, applied after the buried
layer (but before epitaxial growth), to implant p-type regions which diffuse
upward (up-down isolation).
A separate mask for high-value (implanted) resistors.

A mask for Schottky diodes, which can consist either of Aluminum

or barrier metals directly in contact with the epi layer.
An additional mask for P+ regions, sometimes used to improve the
performance of lateral PNP transistors.
A mask for thin-film resistors.
Occasionally a washed emitter is used. Here the emitter diffusion
(or more likely, implant) takes place through the N+ contact openings
(while the windows to the P-regions are masked off). After creating the N+
regions, the thin oxide layer over them is simply etched (or washed) off
without a mask. In this way the emitter area can be made smaller, because
it is self-aligned with the contact window.
The dimensions of the mask patterns are determined by the process;
some of the factors are:
Minimum size of contacts; determined by how small a window can
be etched into the oxide. Most of the small-geometry processes require all
contacts to be of identical size.
Distance between emitter and base contacts; usually given by the
minimum required spacing of the metal covering them.
Overlap of metal over contacts; determined by how well the metal
can be aligned to the contact.
Spacing between sinker and base; set by the sideways diffusion of
the sinker (and base) and the depletion layer width for the maximum
voltage.
Spacing between base and isolation; determined by the sideways
diffusion of the isolation (and base) and two depletion regions.
Spacing between sinker and isolation; must accommodate two
sideways diffusions and one depletion region.
Spacing between buried layer and isolation; must allow for the
sideways diffusions of both the isolation and the
buried layer. After epitaxial growth the image of
the buried layer at the surface is blurred and shifted
along the crystal axis (see page 1-17) and thus
results in the least accurate alignment.
The isolation mask is a special case. The
diffusion takes place between the devices, but it
would be awkward to draw such a complex web.
Thus a convention has been established to draw the
isolation region where it is not, and then invert the
pattern on the mask.
There are several choices for the design of Fig. 17-2: Isolation
an NPN transistor; figure 17-3 shows some of them. pattern.

In the top pattern the emitter is in the center, the base

contact on the right and the collector contact on the
left. In the pattern below, emitter and base contact
are reversed. There is a slight advantage to having
the emitter closer to the collector contact, in that the
distance the current has to travel in the buried layer
to a point underneath the emitter is reduced. (For
clarity, the buried layer and sinker patterns have
been omitted).
You will also see NPN transistor patterns
with more space between emitter and base or base
and collector to accommodate metal lines.
In the third pattern the collector contact has
been moved, resulting in a somewhat lower
saturation voltage.
The bottom pattern contains two base
contacts, effectively doubling
the current capability of the
devices (remember that the
maximum current is given by
the effective emitter length,
i.e. the periphery of the emitter
facing the base contact; the
rest of the emitter area is
Fig. 17-3: Small NPN
transistor patterns. ineffective at high currents).
Figure 17-4 shows NPN
transistors with two emitters in
a single island (or tub). In the top pattern collector
and base are common, i.e. connected together, which
limits the usefulness of the device.
In the center pattern there are separate bases,
only the collector is common. The bottom pattern is
identical, with the contacts redrawn for uniform size.
There is a danger with multiple emitters in the
same island. As mentioned before, the image of the
buried layer is shifted (in all but low-pressure
epitaxial processes). The actual buried layer region is
where it is supposed to be, a rectangle covering the
Fig. 17-4: Two-
area from the collector contact (and sinker) to the far emitter NPN
edges of the base regions. But the image appearing transistors.
on the surface is shifted (along the crystal axis). In

<111> silicon starting material, with the wafer-

flat at the bottom, the epi-shift is to the right
(figure 17-5). The amount of shift is roughly
equal to the thickness of the epi-layer. What we
see on the surface is a depression, caused by a
slight consumption of silicon during the
diffusion of the buried layer. Thus it is likely
that this step in surface height will hit the left
emitter, but not the right one, which influences
their matching.
This effect can be avoided if the entire Fig. 17-5: Epi-shift
influencing one emitter
but not the other.
transistor is rotated so the

edge of the shifted
pattern falls between the
collector contact and the
bases. Figure 17-6
shows this with a two-
transistor layout. The
center transistor has a
single emitter, the outer
one 16 (used, for
Fig. 17-6: 16:1 emitter ratio with epi-shift mismatch example, in a bandgap
avoided.
reference).
The transistor patterns

shown so far are all intended
for smallest possible size,
which naturally limits how
much current they can carry.
To increase the current
capability, the effective
emitter length needs to be
increased. For the NPN
transistor in figure 17-7 not
only have the emitters been
tripled and stretched, but base
contacts have been placed on
both long sides. Note that the
increase in current capability Fig. 17-7: NPN transistor for higher current.

almost always requires wider metal runs for both the emitter and collector
(see box on page 14-5).
An alternate design is
shown in figure 17-8, with
the uniform contact openings
required by dense processes.
There are two collector
contacts (on the outside),
three emitters and four base
contact columns.
If you increase the
size of such a transistor
further, there comes a point
where it is of advantage to
taper both the emitter and
collector metal, gradually
increasing the width as the
Fig. 17-8: Alternate high-current design. currents from more and more
contacts are added.
Lateral PNP Transistors
The emitter of a lateral PNP

transistor (figure 17-9) is in the center, the
dark contact in a p-type (NPN base)
diffusion. It is surrounded by the collector,
another p-type region. The distance
between the outer edge of the emitter and
the inner edge of the collector is the base-
width. Since both of these regions are on
the same mask, emitter and collector are
self-aligning and the base-width tends to be
very accurate. It needs to be large enough
to accommodate the two sideways
diffusions and the depletion region
spreading from the collector toward the
emitter.
By extending the emitter metal so Fig. 17-9: Lateral PNP transistors.
that it covers the entire base, a field plate
is created (always connected to the emitter, which has the highest positive

voltage). This field plate improves the gain of the transistor at low current
by keeping p-type charges away from the surface. (In a CMOS process, the
poly layer is used as a field plate, also connected to the emitter).
Although a circular emitter results in a uniform base-width and thus
(theoretically) produces the highest possible gain, there is actually very little
enhancement over the more simple square one.
The third terminal (at the bottom) is the base contact, identical to a
collector contact for an NPN transistor.
For a lateral PNP transistor (in a bipolar process) the presence of a
buried layer is essential. Without it, the substrate (connected to the most
negative supply) would be just as attractive a collector as the intended one;
i.e. about half the emitter current would flow to the collector, the other half
to the substrate.
The dual pattern at the bottom of figure 17-9 should be avoided. It
looks attractive, especially since lateral PNP transistors often have common
bases (e.g. in current mirrors), but the two devices influence each other,
especially in saturation.
Resistors
In the case of a diffused resistor there

is always a surrounding semiconductor
region (the epitaxial layer for a bipolar
process, a well or the substrate in CMOS).
The surrounding region needs to be at a
potential so that the junction is reverse-
biased. This bias voltage causes a depletion
layer to extend into the resistor, decreasing
its cross-section and thus increasing its
resistance. For a base diffusion this effect is
small but occasionally not negligible (about
1%); for an implanted resistor it can be very
large (20%).
Thus, if two diffused resistors form a
Fig. 17-10: Diffused resistors voltage divider, the difference between the
in a common (top) and in bias voltage and the resistor voltage is larger
separate (bottom) islands.
for the lower resistor than the upper one,
resulting in a shift of the divider ratio. It may

be small enough to ignore for resistors with 200 Ohms/square (about 0.2%),
but for implanted resistors this error is almost always significant. Note that
this is an initial error only; it is not subject to change during production.
To avoid this effect, you can place each resistor in its own tub and
connect the tub to the positive end of the resistor.
Routing the metal also needs

some thought. The Seebeck coefficient
(see page 1-31) creates a small voltage
between junctions of the same material,
located at different temperatures. For
this reason it is of advantage to keep
connections close together, so that a
thermal gradient will have the smallest
effect. Figure 17-11 shows a pair of
resistors with three sections each,
connected on the same side to obtain the Fig. 17-11: Intermingling and
connection of matching resistors.
shortest distance. For optimum
matching in the presence of a thermal
gradient the sections also alternate.
CMOS Transistors
With the basic layers only, the layout of

an n-channel transistor is quite simple: there
are only three patterns. The first pattern is the
poly gate (sitting on top of thin oxide). The
second pattern delineates an N+ implant; it is
simply a rectangle, protruding on either side of
the poly shape. The n-type dopants enter the p-
type silicon underneath (the substrate) only
outside the gate area; they are stopped by the
poly-silicon layer. The third mask places
contact opening in the poly and implanted
regions.
For a p-channel device two additional
masks are required: one for an n-well
(surrounding the device or several devices) and
Fig. 17-12: Layout of n- one for the P+ implant. The n-well must be
channel (top) and p-
channel transistors.
contacted and biased.

The patterns in figure 17-12 show long channels, as often required

in analog design; the channel length is from left to right, the channel width
from top to bottom.
Alas, if things only were that simple. In reality the layout of CMOS
IC always involves a large number of masks. There are such layers as field
implant, threshold implant, poly 2, poly 3, metal 2, metal 3, metal 4 (an on),
interconnections between the metal layers (vias), the pad mask.
Also, some layers are not drawn directly, but are coded. Additional
layers are used which form mask patterns only in combination with others.
Most CMOS processes
have an n-well (i.e. n-channel
devices sit in the common
substrate, while p-channel
transistors are in common or
separate n-wells); sometimes
both n and p-wells are present.
Drain and source are
interchangeable, which leads to
a peculiar but efficient way to
connect devices in parallel (i.e.
to increase the channel width):
Fig. 17-13: Parallel connection of n-channel
you connect them in series and transistors.
merge the terminals between
the gates (figure 17-13). Thus the source of one transistor also acts as the
drain of the next one, saving space.
The smallest set of matching

devices consists of four transistors,
arranged to be point-symmetrical.
The terminals of the two devices
labeled A (figure 17-14) are
connected together, as are those for
the B transistors. You will find that
this is almost impossible without
employing the second metal layer.
If there is a gradient
(thermal or otherwise) it will affect
both devices equally, no matter
which direction it takes.
Fig. 17-14: A matching pair of n-channel
transistors, using four devices.

Matching: Myths and Misconceptions
Over the years a number of rules have accumulated around

analog design, especially concerning matching devices. For example,
most designers believe that matching devices should be intermingled
and as close together as possible, because the diffusions or implants
have gradients, i.e. vary gradually in depth or concentration over the
area of the chip.
A few years ago I had an opportunity to examine this. I
measured the matching of adjacent devices and compared that with
devices which were farther apart. To my surprise I found no
statistically valid difference in matching for a distance of up to 2mm.
It seems that, perhaps, diffusion gradients were present in the
early days but, with better furnaces and especially ion implantation,
have disappeared to the point where they simply no longer play a role.
To be sure, there are thermal gradients, created by devices
which heat one area of a chip more than another. For this reason alone
it is wise to intermingle devices and place them close together (and as
far from the heat source as possible.
A second belief divides matching devices into as many small

pieces as possible, so that they benefit from the statistical effect (large
groups of devices match better than two single ones). This has proved
to be only marginally true. As you decrease the size of features, the
percentage variation becomes greater. Thus, as you approach
minimum geometry, matching actually becomes worse for the same
overall area.
The third belief holds that you should add dummy devices at
the periphery. There appear to be two different explanations to justify
this practice: 1. shadows or reflections during exposure act differently
on the remote edges than on devices in close proximity, or: 2. the etch-
rate for wide spaces is different from narrow ones.
I found no difference between groups of resistors with and
without dummy devices at the periphery. It appears that you might be
better off using the extra space to make the devices larger.

Cross-Unders
Bipolar analog ICs can often be interconnected using a single metal

layer, which lowers the cost. But you will inevitably find spots where two
metal lines need to cross.
Using the diffused layer with the lowest resistance (emitter, or N+),
one interconnection stops at a contact, dives
under the second metal line, and continues at
the second contact. This introduces a small
amount of resistance (about 20 Ohms), which
is tolerable in such places as a base of a
transistor.
In figure 17-15 the N+ rectangle is Fig. 17-15: N+ cross-under.
placed inside a base diffusion (which sits
inside an epi-island). One side of the cross-
under is connected to the base region (it does not matter which side, since
the voltage drop across the cross-under is bound to be much smaller than
that of a diode). If the epi-island is biased at the highest positive supply
voltage, you can have several such cross-unders in the same island.
The epitaxial region can serve as
a cross-under as well, though it takes up
more space.
A special case in the latter
approach is the NPN transistor with two
collector contacts (figure 7-16). Here a
line connected to the collector stops at
the right-hand contact and continues on
Fig. 17-16: Two collector contacts in
an NPN transistors can act as a
at the left-hand one.
cross-under. But be careful with this scheme.
Let's assume the resistance between the
contacts is 100 Ohms. The resistance between one contact and the center
(i.e. a point underneath the emitter) is then about 50 Ohms. If one contact
carries all or most of the collector current, the second contact will display
the voltage at the center and not that of the first contact.

Kelvin Connections
Any contact on the surface of an IC

has some resistance, which often makes
precision measurements difficult. This
can be avoided by providing two sets of R
contacts, one to carry the current, the other
to measure the voltage.
In a Kelvin connection contact
resistance is of no consequence. The two
resistances in the current path add a bit to Fig. 17-17: A Kelvin connection
for a resistor and its equivalent
the headroom required, the two in circuit.
measurement path simply need to be
negligible compared to the measuring impedance.
Metal Runs and Ground Connections
The concept of an "analog ground" is often misunderstood. It is

meant to be a noise-free point (or hub), a spot either on the circuit board or
on the IC which can be used as a 0-Volt reference.
The usual practice designates a pin which carries little or no current
as the analog ground; other pins, intended to be at the same potential but
carrying current are then connected to this point on the circuit board.
There is another way to achieve this, one which saves a pin and has
better performance. A package pin has low resistance, lower than a trace on
a circuit board or a metal run on the IC. Designate a pin as the analog
ground and then connect not one but two
neighboring pads to it with separate bonding
wires: one carries no current and serves as the
analog reference ground on the IC, the other
carries the potentially polluting currents.
Similarly, on the IC, use separate metal
runs to connect sensitive devices. In figure 17-18
the left-hand connection can create an error.
Assume the runs lead to emitters carrying 1mA.
With say 50 squares (at 30mOhms per square) of
additional aluminum for the upper device, the
voltage drop is 1.5mV, creating a current
Fig. 17-18: Proper
connection (on the right)
mismatch of 6% at room temperature. With the
for matching devices. balanced connection on the right this is avoided.

Back-Lapping and Gold-Plating
To fit into small, shallow packages, wafers are often thinned down
by back-lapping (a somewhat messy, wet grinding operation). This
removes not only the oxide layer on the back but any diffusions which may
have taken place there, giving direct access to the substrate material. If you
add a gold-plating step you get a low-resistance connection directly to the
substrate.
Ordinarily such a connection is not essential (the substrate is also
contacted from the top). But if you have sinned and allowed high substrate
currents, you may be able to suppress the resulting effects in this way.
DRC and LVS
A computer is clearly not as smart as a human being (or so we like

to think), but it is adamantly intolerant of errors and it never tires.
There are two checking operations required when a layout is
finished. The first is Design Rule Checking (DRC), where it is made sure
that the dimensions and spacings in each layer in each device and for all the
connections obey the design rules.
The second compares the layout with the (simulated) schematic
(layout versus schematic, or LVS).
One has to face the humiliating fact that the human being is not well
suited for either job. Great attention to an excruciating amount of detail is
required, which we cannot handle without making mistakes.
Only if DRC and LVS are done by computer can you be certain that
the chip will contain what you think it contains.
* * *
Thus ends this book of the minority field in the world of semiconductors. A
field past glamour, often neglected, but undeniably essential. And a field of
great satisfaction for those who know it.

References
Chapter 1
History of the Transistor:
Pearson, G.L. and Brattain, W.H.: "History of Semiconductor Research", Proceedings of

the IRE, December 1955, pp. 1794-1806
Shockley, W.: "The Invention of the Transistor", National Bureau of Standards Publication
# 388, May 1974
Shockley, William: "The Path to the Conception of the Junction Transistor", IEEE
Transactions on Electron Devices, July 1976, pp. 597-620
Brattain, Walter H.: "Genesis of the Transistor", The Physics Teacher, March 1968, pp.
109-114
History of the Integrated Circuit:
Wolff, Michael F.: "The Genesis of the Integrated Circuit", IEEE Spectrum, August 1976,
pp. 45-53
Interviews with Phil Ferguson, Victor Grinich, Jean Hoerni, Eugene Kleiner and Robert
Noyce, 1983
Reid, T.R.: "The Chip", Simon and Schuster, 1984
Transistor Design:
Muller, Richard and Kamins, Theodore: "Device Electronics for Integrated Circuits", John
Wiley and Sons, 1977
Roulston, David: "Bipolar Semiconductor Devices", McGraw-Hill, 1990
Chapter 2
Antognetti, Paolo and Massobrio, Guiseppe: "Semiconductor Device Modeling with

Spice", McGraw-Hill, 1988
Kundert, Kenneth: "The Designer's Guide to Spice and Spectre", Kluwer Academic
Publishers, 1995
Berkeley BSIM model information is available at www-device.eecs.berkeley.edu/~bsim3/
Edition February 2005 References-1

Chapter 5
Fig. 5-7: This circuit is usually attributed to Bob Widlar, but in his paper and patent he
considered only 1:1 emitter ratios. Widlar, "Some Circuit Design Techniques for Linear
Integrated Circuits," IEEE Transactions on Circuit Theory, Dec. 1965, pp. 586-590.
Widlar, "Low-value current source for integrated circuits," US Patent 3,320,439, 1967
Fig. 5-14: George Erdi, "Starting to Like Electronics in Your Twenties", p 172, in
Williams, "Analog Circuit Design", Butterworth-Heinemann, Stoneham, MA, 1991. Erdi,
US Patent 4,837,496, 1989
Chapter 6
dB: Martin, W.H., "DeciBel - The New Name for the Transmission Unit, Bell System
Technical Journal, January 1929
Steinmetz: Wagoner, C.D., "Steinmetz Revisited", IEEE Spectrum, April 1965, pp.82-95.
Kline, Ronald R., "Steinmetz", Johns Hopkins University Press, 1992
Fourier: Encyclopedia Britannica
Chapter 7
Hilbiber, D.F., "A New Semiconductor Voltage Standard", International Solid State
Circuits Conference, 1964 (ISSCC 1993 Commemorative Supplement, pp. 34-35)
Widlar, R. J., "New Developments in IC Voltage Regulators", ISSCC Digest of Technical

Papers, Feb. 1970, pp.32-33, and IEEE Journal of Solid-State Circuits, Feb. 1971, pp. 2-7
Brokaw, A. P., "A Simple Three-Terminal IC Bandgap Reference", IEEE Journal of Solid-
State Circuits, December 1974, pp. 388-393. Brokaw, "Solid-State Regulated Voltage
Supply", US Patent 3,887,863, June 3, 1975
Widlar, R.J., "Temperature Compensated Bandgap IC Voltage References", U.S. Patent

4,249,122, Feb. 3, 1981
Gunawan, M., Meijer, G., Fonderie, J. and Huijsing, J., "A Curvature-Corrected Low-
Voltage Bandgap Reference", IEEE Journal of Solid State Circuits, June 1993, pp. 667-670
Chapter 8
Solomon, James E.: "The Monolithic Op Amp: A Tutorial Study", IEEE Journal of Solid
State Circuits, December 1974, pp. 314-332

Figures 8-10, 8-11 and 8-14: Output stage and base current compensation scheme were
derived from Linear Technology Corporation's LT6011
Hogervorst, Ron, et al: "A Compact Power-Efficient 3V CMOS Rail-to-Rail Input/Output

Operational Amplifier for VLSI Cell Libraries, IEEE Journal of Solid State Circuits,
December 1994, pp. 1505-1513
De Langen, Klaas-Jan and Huijsing, Johan H.: "Compact Low-Voltage Power Efficient
Operational Amplifier Cells for VLSI, IEEE Journal of Solid State Circuits, October 1998,
pp. 1482-1496
Chapter 10
Figure 10-2 is derived from the National Semiconductor LM13700. A similar concept is
used in the RCA (now Intersil) CA3280
Figure 10-7: Nedungadi, A. and Viswanathan, T.: "Design of Linear CMOS

Transconductance Elements", IEEE Transactions on Circuits and Systems, October 1984,
pp. 891-894
Chapter 11
Low-Voltage 555: Camenzind, Hans R.: "Redesigning the old 555", IEEE Spectrum,
September 1997, pp. 80-85
Matthys, Robert J.: "Crystal Oscillators", revised edition, Krieger Publishing Company,
1992
Chapter 12
Gardner, Floyd M.: "Phaselock Techniques", John Wiley and Sons, second edition, 1979
Grebene, Alan B. and Camenzind, Hans R.: "Frequency-Selective Integrated Circuits

Using Phase-Lock Techniques", IEEE Journal of Solid State Circuits, August 1969, pp.
216-225
Chapter 13
Sallen, R.P. and Key, E.L.: "A Practical Method of Designing RC Active Filters", IRE
Transactions on Circuit Theory, March 1955, pp. 74-85
Butterworth, S.: "On the Theory of Filter Amplifiers", Wireless Engineer, 1930, pp. 536-
541
Brodersen, R.W., Gray, P.R. and Hodges, D.A.: "MOS Switched Capacitor Filters",
Proceedings of the IEEE, January 1979, pp. 61-75

Chapter 14
Pressman, Abraham I.: "Switching Power Supplies", McGraw-Hill, 1991
Billings, Keith: "Switchmode Power Supply Handbook", McGraw-Hill, 1989, 1999
Camenzind, H.R.: "Modulated Pulse Power Amplifiers for Integrated Circuits", IEEE
Transactions on Audio and Electroacoustics, September 1966, pp. 136-140
Attwood, Brian E.: "Design Parameters Important for the Optimization of Very-High
Fidelity PWM (Class D) Audio Amplifiers", Journal of the Audio Engineering Society,
November 1983, pp. 842-853
Duncan, Ben: "High Performance Audio Amplifiers", Newnes, 1996
Chapter 15
Analog Devices: "Analog-Digital Conversion Handbook", Prentice-Hall, 1986
Van de Plasche, Rudy: "Integrated Analog-to-Digital and Digital-to-Analog Converters",

Kluwer, 1994
Boser, Bernhard E. and Wooley, Bruce A.: "The Design of Sigma-Delta Modulation
Analog-to-Digital Converters", IEEE Journal of Solid-State Circuits, December 1988, pp.
1298-1308
Candy, James C. and Temes, Gabor C.: "Oversampling Delta-Sigma Data Converters",
IEEE Press, 1992
Analog Devices: "Sigma-Delta ADCs and DACs", Application Note AN-283
Chapter 16
Gilbert, Barrie: "A New Wide-Band Amplifier Technique", IEEE Journal of Solid-State
Circuits, December 1968, pp. 353-365
Gilbert, Barrie: "A High-Performance Monolithic Multiplier Using Active Feedback",

IEEE Journal of Solid-State Circuits, December 1974, pp. 364-373

Camenzind: Designing Analog Chips Index
Index
1/f noise 6-6 Buck regulator 14-9

555 Timer 11-3 Buried layer 1-17
Buried Zener diode 1-29
AC analysis 2-3 Butterworth 13-3, 13-5
Active emitter length 1-19
Active filters 13-1 Capacitance 1-6
Active load 4-5 Capacitor models 2-17
ADC 15-7 Capacitors 1-32
Aluminum 1-6 Capture range 12-4
AM detection 12-5 Cascode 1-22
Analog to digital 15-7 Cat's whisker 1-2
Antimony 1-10 Cauer 13-7
Arsenic 1-10 Celsius scale 16-11
Auto-zero 8-15 Centigrade scale 16-11
Averaging 16-7 Channel 1-25
Chebyshev 13-3, 13-5
Back-gate 1-26 Chopper-stabilized amplifiers 8-15
Back-lapping 17-12 Class A 14-12
Bandgap curvature 7-5 Class B 14-12
Bandgap References 7-1 Class AB 14-13
Band-pass filters 13-6 Class D 14-16
Bardeen 1-8 CMOS current sources 5-7
Base 1-9 CMOS transistors 1-23, 17-7
BCD 15-2 Collector 1-9
Bel 6-1 Common-mode 8-2
Bell Laboratories 1-7, 1-9, 6-1 Comparators 9-1
Berkeley 2-1 Concen6ration 1-5
Bessel 13-3, 13-5 Conduction band 1-3
BICMOS 1-17, 1-33 Copper-oxide 1-2
Binary coded decimal 15-2 Cross-unders 17-10
Binary weighted 15-3 Crystal oscillators 11-16
Bipolar transistor 1-9, 1-34, 17-1 Current comparators 9-6
Bipolar transistor model 2-10 Current DAC 15-5
Bipolar transistor pattern 17-3 Current density 7-2
Boltzman constant 1-6 Current gain 2-11
Boost regulator 14-11 Current ratio 3-5
Boron 1-4 Current sinks 3-2
Brattain 1-7 Current sources 3-2, 5-1
Braun, Ferdinand 1-2
Breakdown voltage 1-6 DAC 15-1
Brokaw 7-3 Darlington configuration 4-7
BSIM 2-14 Darlington, Sidney 4-8
Edition February 2005 Index-1

dB 6-1 Fourier 6-6

DC analysis 2-2 Fourier analysis 2-5, 6-6
Decibel 6-1 Fourier transform 2-5
Delta-sigma converter 12-8 Four-quadrant multiplier 12-1
Delta-VBE 7-2 Frequency compensation 6-9, 8-2
Depletion layer 1-6, 1-18 ft 1-22
Depletion region 1-5 Full-wave 16-8
Detector 16-5
Differential pair 4-1 Gain 1-9, 1-18, 2-11
Diffused resistors 1-30, 17-6 Gain control 10-2
Diffusion 1-10 Galena 1-2
Diffusion current 1-6, 2-9 Gallium 1-10
Diffusion gradients 17-9 Gate capacitance 1-33
Digital to analog 15-1 Gaussian distribution 2-6
Diode 1-2, 1-5, 1-27 Germanium 1-3
Diode-connected transistor 1-28 Gibney, Robert B. 1-8
Diode model 2-8 Gilbert cell, 16-1
Diode thermometer 16-12 Global nodes 2-12
Distortion 2-5, 6-6, 8-16, 10-2 gm 4-2
Divider ADC 15-5 Gold-plating 17-12
Divider DAC 15-1 Gradients 17-9
Doping 1-5 Gray code 15-2
Doping level 1-5, 1-6 Ground connections 17-11
Drain 1-24 Group delay 13-4
D to A 15-1
DRC 17-12 Half-wave 16-7
Dynamic emitter resistance 4-2, 10-1 Hall effect 1-2, 1-4
Hall, Edwin 1-2
Early effect 1-18 Harmonics 6-7
Early voltage 1-18 hFE 1-18
Electro-migration 14-5 High current transistors 17-4
Electron charge 1-6 High-pass filters 13-6
Electron orbits 1-3 Hilbiber 7-1
Electrons 1-3 Hoerni 1-11, 1-12
Elliptic filter 13-7 Holes 1-4
Emitter 1-9 HSPICE 2-14
Emitter ratios 3-5 Hysteresis 9-2
End-effect 1-30
Energy bands 1-3 Implanted resistors 1-30
Enhancement mode 1-25 Integrated circuit 1-13
Epi-shift 1-17, 17-4 Intermodulation distortion 6-8
Epitaxial layer 1-17 Ion Implantation 1-17
Erdi current source 5-6 Is 1-6
Isolation 1-17, 1-18, 1-20
Fairchild Semiconductor 1-11 Isolation pattern 17-2
Fast Fourier transform 2-5, 6-6
Filters 13-1 Johnson noise 6-5
Flicker noise 6-6 Junction capacitance 1-6, 1-21
FM detection 12-5 Junction isolation 1-18
Folded cascode stage 8-5 Junction transistor 1-9, 1-10

Ohms per square (Ω/*) 1-29

k 1-5, 1-26 Op-amps 8-1
Kelvin scale 16-10 Oscillator 11-4
Kelvin connection 17-11 OTA 10-1
Kilby 1-13
Pad models 2-17
Ladder DAC 15-4 Parallel resonance 11-18
Lateral PNP transistor 1-22 Peak detector 16-5
Lateral PNP transistor model 2-13 Pederson 2-1
Lateral PNP transistor patterns 17-5 Phase 2-3, 6-9
Lead sulfite 1-2 Phase margin 6-13, 8-3
LC oscillators 11-15 Phase-locked loop 12-1
Lock range 12-4 Phosphorus 1-4
Low drop-out 14-4 Photoresist 1-12, 1-14
Low-pass filters 13-1 Pin models 2-17
LVS 17-12 Pinch resistors 1-31
Planar process 1-12, 1-14
Mask 1-12, 1-14, 17-1, 17-8 PLL 12-1
Matching 1-23, 1-31, 17-9 PNP transistors 1-10
Mesa transistor 1-11 Point-contact transistor 1-9, 1-10
Metal runs 17-11 Pole 6-9
Miller capacitance 1-21, 8-16 Poly resistors 1-30
Miller effect 1-21, 8-16 Poly-crystalline silicon 1-24
Minority carriers 1-9 Positive feedback 11-7
Mixed-mode processes 1-33 Power amplifiers 14-12, 14-5
Models 2-1, 2-8 PTAT 5-4, 16-10
Monotonic 15-3 P-type 1-4
Monte Carlo analysis 2-7 Pulse generator 11-12
Moore 1-11 Pulse-width modulation 14-8, 14-16
MOS transistor 1-23 Punch-through 1-21
MOS transistor model 2-14 PWM 14-8, 14-16
Multiplier 12-1, 16-3
Multiplying DAC 15-2 q 1-6
Neper 6-1 R-2R DAC 15-4

Noise 2-11, 6-4 Radiation 14-18
Noise analysis 2-4 Rail-to-rail 8-14, 9-5
Noise current 6-5 re 4-1, 10-1
Noise voltage 2-4 Rectifier 16-7
Normal distribution 2-6 Regulators 14-1, 14-8
Noyce 1-11, 1-13 Resistivity 1-6, 1-29
NPN transistor 1-10, 1-16, 1-17 Resistor models 2-16
NPN transistor model 2-12 Resistor noise 6-5
N-type 1-4 Resistors 1-29, 17-6
nV/rtHz 2-4, 6-6 Rho (ρ) 1-6
N-well 1-24, 1-26 Ring oscillator 12-6
RMS 6-2
Offset binary 15-2 Root-mean-square 6-3
Offset voltage 4-2
Ohm-cm 1-6

Sallen & Key filter 13-2 Transfer curve 4-6

Schmitt trigger 12-7 Transfer function 2-3
Schmitt, Otto 12-8 Transient analysis 2-4
Schottky diode 1-3 Transistor 1-7, 1-9
Second-order temperature Transistor model 2-10
compensation 7-7 Triangle-wave generator 11-9
Seebeck coefficient 1-31, 17-7 Twin-T filter 13-7
Segmented DAC 15-2, 15-4 Twos complement 15-2
Selenium 1-2, 1-3
Self-aligning 1-24 Up-down isolation 1-21
Self-insulating 1-24
Semiconductors 1-2 Valence 1-3
Sensitivity analysis 2-3 Valence electrons 1-3
Series resonance 11-18 Variations 2-6
Sheet resistance 1-29 VBE 3-1, 5-1, 7-1
Shockley 1-7 VCO 11-1, 12-1
Shockley Semiconductor Voltage breakdown 1-21
Laboratories 1-11 Voltage coefficient 1-30
Shot noise 6-5 Voltage-Controlled Oscillator 11-1,
Signetics 11-1 12-1
Sign + magnitude 15-2
Silicon 1-3 Washed emitter 17-2
Silicon, density 1-5 White noise 6-5
Silicon-dioxide 1-12 Widlar 3-1, 7-1, 7-6, 7-11
Simetrix 2-1, 2-5, 2-6 Widlar current mirror 3-1
Sine-wave generator 11-11 Wilson current mirror 3-3
Single crystal 1-3 Wilson, A.H. 1-3
Slew rate 8-4
Source 1-24 Zener diodes 1-28
Space-charge layer 1-5 Zero 6-11
SPICE 2-1 Zero-crossing detector 16-12
Split collector 1-23 Zone refining 1-3
Spread spectrum 14-18
Standard cells 1-1
Start-up 5-6
Steinmetz 6-2
Subcircuit 2-11
Substrate current 1-20
Substrate PNP transistor 1-20, 1-27
Successive approximation 15-7
Surface 1-7
Switched-capacitor filters 13-8
Switching regulators 14-8
Switching power amplifiers 14-15
Thermometer 16-10
Threshold voltage 1-26
Timers 11-4, 11-14
Transconductance 1-26
Transconductance Amplifier 10-1

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Copyright 2004, 2005 Hans Camenzind.

This book is can be downloaded without fee from

Re-publishing of any part or the whole is prohibited.

Edition February 2005 All rights reserved

CMOS Bandgap References 7-13

Edition February 2005 All rights reserved

"Everything is going digital". Cell phones, television, video disks,

Edition February 2005 All rights reserved

Hence this book. It should give you an overview of the world of

Academic text books on IC design are often filled with mathematics.

Edition February 2005 All rights reserved

Let's assume your IC design needs an operational amplifier. Which

Edition February 2005 1-1 All rights reserved

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In the background, mostly at universities and large corporate

Edition February 2005 1-3 All rights reserved

Edition February 2005 1-4 All rights reserved

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measured between opposite surfaces of a cube of material with a side-length

The (Bipolar) Transistor

Edition February 2005 1-7 All rights reserved

Edition February 2005 1-8 All rights reserved

management on December 23, 1947.

have a current gain of 100 or even 500.

Edition February 2005 1-9 All rights reserved

Edition February 2005 1-10 All rights reserved

Edition February 2005 1-11 All rights reserved

remaining piece a mesa-like shape.

Edition February 2005 1-12 All rights reserved

The Integrated Circuit

Edition February 2005 1-13 All rights reserved

Let's take a closer look at a basic processing step in the Planar

Edition February 2005 1-14 All rights reserved

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Edition February 2005 1-16 All rights reserved

themselves according to the existing crystal structure.

Edition February 2005 1-17 All rights reserved

This transistor is isolated from its neighbors (and other components)

shallow depletion layer takes 180

base depth. As the collector 120

layers widen. In the collector 60

side of the collector), but in the Vc/V 1V/div

base region it narrows the

Edition February 2005 1-18 All rights reserved

collector. At low current this 250

in the base is sufficiently 200

small. But as the collector 150

current increases (and with it

of the base causes a

Edition February 2005 1-19 All rights reserved

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Let's use the integrated NPN transistor as an example. There are

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nowhere near the advertised ft (cutoff frequency).

The Case of the Lateral PNP Transistor

Edition February 2005 1-22 All rights reserved

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In 1964 a startup, General Microelectronics, felt it had licked the

Edition February 2005 1-24 All rights reserved