Verilog Source Code:
module logicgates (x,y,A,B,C,D,E,F,G); // Starting of module //
Input x,y; // Input variables //
Output A,B,C,D,E,F,G; // Output variables //
assign A= ~x;
assign B= x&y;
assign C= x|y;
assign D= ~(x&y);
assign E= ~(x|y);
assign F= x^y;
assign G= ~(x^y);
endmodule // End of module //
Verilog Testbench Code:
module logicgates_tb;
// Inputs
reg x;reg y;
// Outputs
wire A;wire B;wire C;wire D;wire E;wire F;wire G;
// Instantiate the Unit Under Test (UUT)
logicgates uut (.x(x), .y(y), .A(A), .B(B), .C(C), .D(D), .E(E), .F(F), .G(G));
initial begin
// Initialize Inputs
#100 x = 0; y = 0;
#100 x = 0; y = 1;
#100 x = 1; y = 0;
#100 x = 1; y = 1;
end
endmodule
>>HALF ADDER
module hadder(A,B,S,C); // Starting of module //
input A,B; // Declaring Input
Variables //
output S,C; // Declaring Output
Variables //
assign S=(A^B); // Assigning the vales of logical
operations //
assign C=(A&B);
endmodule // End of module //
>>FULL ADDER
module fadder(A,B,C,S,C0); // Starting of
module //
input A,B,C; // Declaring Input
Variables //
output S,C0; // Declaring Output Variables //
assign C0=(A&B)|(B&C)|(C&A); // Assigning Values to
Logical expression //
assign S=(A^B^C);
endmodule
// End of module //
>>PARALLEL ADDER
module pa(
input[3:0]a,
input[3:0]b,
input[3:0]c,
output s,
output c0
);
wire c0,c1,c2;
FA f1(a[0],b[0],c,s[0],c0);
FA f2(a[1],b[1],c,s[1],c1);
FA f3(a[2],b[2],c,s[2],c2);
FA f4(a[3],b[3],c,s[3],c3);
endmodule
Verilog Testbench Code:
>>HALF ADDER
module hadder_tb;
// Inputs
reg A;
reg B;
// Outputs
wire S;
wire C;
// instantiate the unit under test (uut)
ha uut (.a(a), .b(b), .s(s), .c(c));
initial
begin
// initialize inputs
#100 A=0; B=0;
#100 A=0; B=1;
#100 A=1; B=0;
#100 A=1; B=1;
End
End module
>>FULL ADDER
module fadder_tb;
//Inputs
reg A;
reg B;
reg C;
//Outputs
Wire S;
Wire C0;
//instantiate the unit under test
fa uut (.a(a), .b(b), .s(s), .c0(c0));
initial
begin
// initialize inputs
#100 A=0;B=0;C=0;
#100 A=0;B=0;C=1;
#100 A=0;B=1;C=0;
#100 A=0;B=1;C=1;
#100 A=1;B=0;C=0;
#100 A=1;B=0;C=1;
#100 A=1;B=1;C=0;
#100 A=1;B=1;C=1;
end
endmodule
>>PARALLEL ADDER
module pa_tb;
// Inputs
reg [3:0] a;
reg [3:0] b;
reg cin;
// Outputs
wire cout;
wire [3:0] s;
padder uut (.a(a), .b(b), .cin(cin), .cout(cout), .s(s)); // Instantiate the Unit Under
Test (UUT)
initial
begin
a [3:0]=4’b0000;b [3:0] = 4’b0000;cin = 1’b0;
#100 a[3:0]=4'b1011;b[3:0]=4'b1000;cin=1'b0;
end
endmodule
Verilog Source Code:
>> ENCODER
module encoder(a,b,c,d,e,f,g,h,x,y,z); // Starting of
module //
input a,b,c,d,e,f,g,h; // Declaring Input
Variables //
output x,y,z; // Declaring Output
Variables //
assign x=(e|f|g|h);
assign y=(c|d|g|h); // assigning Values to logical
expression //
assign z=(b|d|f|h);
endmodule // End of module //
>> DECODER
module decoder(a,b,c,d,e,f,g,h,x,y,z); // Starting of
module //
input x,y,z; // Declaring Input
Variables //
output a,b,c,d,e,f,g,h; // Declaring Output
Variables //
assign a=(~x)&(~y)&(~z);
assign b=(~x)&(~y)&(z);
assign c=(~x)&(y)&(~z); //Assigning values to logical
Expression//
assign d=(~x)&(y)&(z);
assign e=(x)&(~y)&(~z);
assign f=(x)&(~y)&(z);
assign g=(x)&(y)&(~z);
assign h=(x)&(y)&(z);
endmodule // End of module //
Verilog Testbench:
>> ENCODER
module encoder_tb;
// Inputs
reg a;reg b;reg c;reg d;reg e;reg f;reg g;reg h;
// Outputs
wire x;wire y;wire z;
// Instantiate the Unit Under Test (UUT)
encoder uut
(.a(a), .b(b), .c(c), .d(d), .e(e), .f(f), .g(g), .h(h), .x(x), .y(y), .z(z));
initial
begin
// Initialize Inputs
#100 a = 0;b = 0;c = 0;d = 0;e = 0;f = 0;g = 0;h = 0; // Wait 100 ns
for global reset //to finish
#100 a = 1;b = 0;c = 0;d = 0;e = 0;f = 0;g = 0;h = 0;
#100 a = 0;b = 1;c = 0;d = 0;e = 0;f = 0;g = 0;h = 0;
#100 a = 0;b = 0;c = 1;d = 0;e = 0;f = 0;g = 0;h = 0;
#100 a = 0;b = 0;c = 0;d = 1;e = 0;f = 0;g = 0;h = 0;
#100 a = 0;b = 0;c = 0;d = 0;e = 1;f = 0;g = 0;h = 0;
#100 a = 0;b = 0;c = 0;d = 0;e = 0;f = 1;g = 0;h = 0;
#100 a = 0;b = 0;c = 0;d = 0;e = 0;f = 0;g = 1;h = 0;
#100 a = 0;b = 0;c = 0;d = 0;e = 0;f = 0;g = 0;h = 1;
end
endmodule
>>DECODER
module decoder_tb;
// Inputs
reg x; reg y; reg z;
// Outputs
wire a; wire b; wire c; wire d; wire e; wire f; wire g; wire h;
// Instantiate the Unit Under Test (UUT)
decoder uut
(.a(a), .b(b), .c(c), .d(d), .e(e), .f(f), .g(g), .h(h), .x(x), .y(y), .z(z));
initial begin
// Initialize Inputs
#100 x=0;y=0;z=0; // Wait 100 ns for global reset to finish
#100 x=0;y=0;z=1;
#100 x=0;y=1;z=0;
#100 x=0;y=1;z=1;
#100 x=1;y=0;z=0;
#100 x=1;y=0;z=1;
#100 x=1;y=1;z=0;
#100 x=1;y=1;z=1;
end
endmodule
Verilog Source Code:
8x1 Multiplexer:
module M8X1(input a, b, c, d, e, f, g, h, x, y,z,
output out );
assign out=((~x)&(~y)&(~z)&a)|((~x)&(~y)&(z)&b)|((~x)&(y)&(~z)&c)|((~x)&(y)&(z)&d)|
((x)&(~y)&(~z)&e)|((~x)&(y)&(~z)&f)|((x)&(y)&(~z))&g|((x)&(y)&(z)&h);
endmodule
1X8 Demultiplexer:
module demux18( // Starting of module //
input i, x, y, z, // Declaring Input Variables //
output a, b, c, d, e, f, g, h); // Declaring Output Variables //
assign a=(~x)&(~y)&(~z)&i;assign b=(~x)&(~y)&(z)&i;
assign c=(~x)&(y)&(~z)&i;
assign d=(~x)&(y)&(z)&i; // Assigning values to logical
expression //
assign e=(x)&(~y)&(~z)&i;
assign f=(x)&(~y)&(z)&i;
assign g=(x)&(y)&(~z)&i;
assign h=(x)&(y)&(z)&i;
endmodule // End of module //
Verilog Test bench Code:
8x1 Multiplexer:
module MUX8X1_TB;
reg a; reg b; reg c; reg d; reg e; reg f; reg g; reg h; reg x; reg y; reg z;
wire out;
M8X1 uut (.a(a), .b(b),.c(c),.d(d),.e(e),.f(f),.g(g),.h(h),.x(x),.y(y),.z(z),.out(out));
initial begin
a = 1; b = 0; c = 1; d = 0; e = 1; f = 0; g = 1; h = 0;x = 0; y = 0; z =
0;
#100; x = 0; y = 0; z = 1;
#100; x = 0; y = 1; z = 0;
#100; x = 0; y = 1; z = 1;
#100; x = 1; y = 0; z = 0;
#100; x = 1; y = 0; z = 1;
#100; x = 1; y = 1; z = 0;
#100; x = 1; y = 1; z = 1;
end
endmodule
1X8 Demultiplexer:
module demux18_tb;
reg i; reg x; reg y; reg z;
wire a; wire b; wire c; wire d; wire e; wire f; wire g; wire h;
demux18 uut (.i(i),.x(x),.y(y),.z(z),.a(a),.b(b),.c(c), .d(d),.e(e),.f(f),.g(g),.h(h));
initial begin
i = 1;
x = 0; y = 0; z = 0;
#100; x = 0; y = 0; z = 1;
#100; x = 0; y = 1; z = 0;
#100; x = 0; y = 1; z = 1;
#100; x = 1; y = 0; z = 0;
#100; x = 1; y = 0; z = 1;
#100; x = 1; y = 1; z = 0;
#100; x = 1; y = 1; z = 1;
end
endmodule
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