SystemVerilog basics, data types, language features

• What are the Features of SV?

• What are the various data types available in SystemVerilog? Can you provide
examples?

• What are all the data types present in verilog and system verilog?

• What are the different data types in SV?

• Why are we going for system verilog? What are disadvantages of verilog ?

• What is the main advantage of system Verilog?

• What is logic data type?

• Why do we use logic data type?

• What is 4 state data type in SV?

• What is 2 state data type in SV?

• What is difference between logic and byte?

• What is the default value of reg, real, logic?

• What is the difference between logic, net, wire and reg?

• What is the difference between reg and wire in SystemVerilog?

• What is the difference between logic and reg in SystemVerilog? What are the default
values of wire and reg?

• Difference between bit-reg, int-integer.

• What is the go-to reputation operator in SystemVerilog? (repetition operator)

Arrays, queues, collection types and methods

• Explain arrays and queues.

• What are packed and unpacked arrays in SystemVerilog? Can you give examples?

• Difference between packed arrays and unpacked arrays and syntax for the same.

• What are dynamic arrays and associative arrays.

• Difference between dynamic arrays and associative arrays.

• Difference between dynamic and associative array?

• What is the difference between dynamic and associate arrays?

• What is the difference between dynamic and associate arrays? (duplicate)

• Difference between queue and associative arrays.

• What are the types of arrays in SV?

• What are stratified queues in SystemVerilog?

 • What are the inbuilt functions for associative arrays and queues in SystemVerilog?

• What are the inbuilt functions for associative arrays and queues in SystemVerilog?
(duplicate)

• Declare a 16 bit associative array?

• How do you use array methods to find numbers greater than 5 in a given array?

OOP: classes, inheritance, polymorphism, copies, overriding, casting

• What is inheritance?

• What is polymorphism?

• What is polymorphism in SystemVerilog, and when do we use it?

• Explain Oops concepts

• Explain inheritance with code

• Explain polymorphism with code

• What is an abstract class?

• What is a singleton class?

• What are properties and methods?

• How do we inherit properties and methods?

• How to access the parent method in child class?

• How can you override a method in parent class?

• Write snippets on how to override classes.

• How to override the constraints?

• How to override constraint?

• What is a super keyword?

• When do we use casting in SystemVerilog? Can you provide examples?

• What is casting? What is static casting? What are the components in verification?

• How to deallocate a memory for a class handle.

• Explain shallow copy and deep copy with example

• Write Snippets for deep copy and shallow copy.

• Explain the difference between shallow copy and deep copy with code and diagram

• What are the object-oriented programming concepts in SystemVerilog? How do

virtual classes work?

• Explain virtual class

• What is OOP?
 • What is the difference between structure and class?

• What is the difference between structs and unions in SystemVerilog?

• What is the difference between typedef and enum in SystemVerilog?

Processes, tasks, functions, scheduling, regions

• What are the different processes in SystemVerilog (fork..join, fork..join_any,

fork..join_none)? How can we achieve inheritance? What is the super keyword?

• Explain Fork join, join_any, join_none.

• Difference between fork join any and fork join none.

• What is system verilog event schedule?

• What is Event scheduling in SV and what is happening in each event? INC? and WRAP
type in what type of memories are used?

• What is Event scheduling in SV and what is happening in each event?

• What are the regions in SystemVerilog?

• Difference between task and function in SV?

• Difference between task and functions.

• What are Task and functions with respect to both Verilog and in SV enhancements?

• Can a task be declared in a function ?

• Write snippet for Calling task inside function.

• Write tb top code.

• What is the start method in SystemVerilog, and when is it used?

• How do you write a function to calculate the sum of two numbers?

• Write a System Verilog code to sum 2 numbers with help from a function.

• Can you write SystemVerilog code for a given design? (You can attach the design
details for this.)

• How do you connect a monitor to a DUT (Design Under Test)?

Interfaces, virtual interfaces, modports, clocking blocks

• What is an interface in SystemVerilog, and how is it used?

• What is interface?

• What is the use of interfaces?

• What is a virtual interface?

• What is virtual interface in SV and why do we use virtual interface?

• What is the need of a virtual interface in system verilog?

 • How to send the virtual interface data to the dut/Design.

• We have one signal in DUT but that signal is not in the interface. How did you get
that signal into the test bench ? Write SV code.

• What is modport?

• What is modport? (duplicate)

• What is the use of clocking block?

• Where do we define clocking block?

• How is setup and hold time in clocking block different from normal setup and hold
time?

Mailboxes, semaphores and synchronization

• What are mailboxes and semaphores in SystemVerilog? How do they differ?

• What is a mailbox?

• Show mailbox connection and show mailbox send transaction from one class and
one mailbox receive the transaction

• What are semaphores?

• What is semaphore?

• What is semaphore?

• What is semaphore and how it is used in a program?

• How semaphore implement blocking methods?

Assertions (SVA)

• What are the types of assertions?

• What are different types of assertions?

• Explain Assertion and its types.

• For a signal A to be low for a 4 clock cycle, write Assertion code.

• How do you write an assertion to check a clock signal?

• Write assertion for fifo full, empty condition.

• Write an assertion that a is high after 2 clock cycle b should be high for 1 to 3 clock
cycle after c is asserted.

• Write an assertion that a is high after 2 clock cycle b should be high for 1 to 3 clock
cycle after c is asserted. (duplicate)

• Write assertion code for finding a glitch. Draw Glitch circuit.

• Write assertion for JK f/f

• A signal ‘A’ should be high for 100 consecutive clock cycles.

Coverage (functional, code, bins, cross)

• What is Coverage?

• What is functional coverage?

• What is the difference between code coverage and functional coverage in

SystemVerilog?

• What is the difference between functional and code coverage?

• Explain Code coverage and functional coverage with example.

• What is cross coverage in SystemVerilog, and how does it differ from code and
functional coverage?

• How can you achieve 100% coverage in your verification process? What does it mean
if you have 100% functional coverage but only 80% code coverage?

• If functional coverage is not 100% and what will you do if it is not 100%?

• What are the different types of bins in SystemVerilog?

• What are code coverage bins?

• What is a wildcard bin?

• What is the difference between conditional and branch bins?

• What is the Cover point?

• How many bins will be created for the covergroup shownmodule top; bit 6:0 a; int b;
covergroup vk_coverage; coverpoint a; coverpoint b ( bins b_bin1 = {1, 2, 3, 4, 5}; bins b_bin2 =
default; ) endgroup endmodule

• How many bins will be created for the covergroup shown (same snippet repeated)

• Explain functional coverage for full adder.

Randomization and constraints: concepts, operators, usage

• What are constraints?

• What are the constraints in SystemVerilog? Can you explain the different types of
constraints?

• What is a constraint logic, and how does it work?

• What are hard and soft constraints?

• What are types of constraints?

• What are Constraints and why are they used?

• Why do we need constraints?

• Randomisation concepts

• What are the different types of randomization in SystemVerilog?

 • Generate random string alphabet for five times.

• What is the start method in SystemVerilog, and when is it used? (listed also in
Processes)

• Difference between rand and $random.

• Where is pre_randomize() and Post Randomize used?

• What is cross-functional model error in SystemVerilog? (kept here as it often appears

in randomized modeling contexts)

Constraint coding exercises and patterns

• How do you write code to generate numbers greater than 5?

• How do you write a constraint to generate a multiple of 5?

• How do you write a constraint for a bit signal that is high for 3 cycles and low for 2
cycles out of 5?

• Can you write a constraint to generate numbers in descending order in a queue?

• Write SV code to Generate random numbers in ascending order without using inbuilt
sort methods.

• Can you provide a specific example of constraints like 010203040506?

• Write chess constraints.

• Write a constraint to fill an array of size 1024 and 32 bit width by having a even
number for each nibble.

• Write a constraint to count the number of 0’s in a number, SV code for a signal which
is going high and after 500 ns after the first signal going high another signal has to go low.

• Write a constraint for ascending order don’t use array methods?

• Write a constraint to consider 1 bit variable that should be 1 for 3 times ?

• 0,2,0,4,0,6,….. write constraints to generate this pattern.

• Write Constraint for Fibonacci series.

• Write a constraint to generate fibonacci series.

• Write a constraint to generate sequences of prime numbers.

• Write a constraint to generate even numbers in odd locations and odd numbers in
even locations in a dynamic array.

• Write a constraint to make diagonal elements same in 2d array.

• Write constraint for Even in odd location and odd in even location

• Write constraint for two arrays is equal.

• Write a constraint for a 16 bit associative array and generate even no. in odd location
and also odd in even location?
 • Write a constraint to fill an array of size 1024 and 32 bit width by having a even
number for each nibble. (duplicate)

• Write constraint for int a, it should not generate values b/w 100 to 200.

• Write constraint for int a, it should not generate values b/w 100 to 200. (duplicate)

• Randomize the 4*4 matrix where two diagonals should be stored with 1 and
probability of getting 1 is 90% (should not consider remaining locations). Write SV code for above
conditions.

UVM basics: factory, config DB, TLM, overrides

• What is factory registration in SystemVerilog, and when is it used?

• What is the Configuration Database (Config DB) in SystemVerilog?

• What are TLM (Transaction-Level Modeling) ports in SystemVerilog?

• Write global factory overriding syntax?

• Write global factory overriding syntax? (duplicate)

Tools and commands

• What is the command used to invoke VCS and Verdi?

Synchronization/handshaking and digital design basics

• What is a handshaking mechanism in digital design?

• How would you design an XOR gate using a multiplexer?

• What is frequency division in digital circuits?

• What is set up and hold time?

• How sequential circuits are realised?

• How flip-flops are intialized in sequential circuits?

• What is Input and Output Skew?

DUT/testbench issues and debugging

• If a test is running in an infinite loop and it is not stopping then how to stop and how
to check the bug? If an objection is given in the test file?

• If a test is running in an infinite loop and it is not stopping then how to stop and how
to check the bug? If an objection is given in the test file? (duplicate)

• How do you connect a monitor to a DUT (Design Under Test)? (also listed under
Processes)

Miscellaneous/other

• What are callbacks in SV?

• What is constraint logic, and how does it work? (duplicate phrasing retained)
• What is the difference between structure and class? (also under OOP)

• Difference between @ev and wait(ev.Triggered).