74 HC 4316
74 HC 4316
74 HC 4316
16 16 1 SOEIAJ16 F SUFFIX CASE 966 1 A L, WL Y, YY W, WW G = Assembly Location = Wafer Lot = Year = Work Week = PbFree Package 74HC139A ALYWG
LogicLevel Translator for On/Off Control and Enable Inputs Fast Switching and Propagation Speeds High ON/OFF Output Voltage Ratio Diode Protection on All Inputs/Outputs Analog PowerSupply Voltage Range (VCC VEE) = 2.0 to 12.0 V Digital (Control) PowerSupply Voltage Range (VCC GND) = 2.0 V to 6.0 V, Independent of VEE Improved Linearity of ON Resistance Chip Complexity: 66 FETs or 16.5 Equivalent Gates PbFree Packages are Available*
ORDERING INFORMATION
Device MC74HC4316AN MC74HC4316ANG MC74HC4316ADR2 MC74HC4316ADR2G MC74HC4316AFEL MC74HC4316AFELG Package PDIP16 PDIP16 (PbFree) SOIC16 Shipping 500 Units / Box 500 Units / Box 2500/Tape&Reel
*For additional information on our PbFree strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.
Semiconductor Components Industries, LLC, 2005
For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D.
MC74HC4316A
XA YA YB XB B ON/OFF CONTROL C ON/OFF CONTROL ENABLE GND 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 VCC A ON/OFF CONTROL D ON/OFF CONTROL XD YD YC XC VEE
FUNCTION TABLE
Inputs Enable L L H X = Dont Care. On/Off Control H L X State of Analog Switch On Off Off
XA A ON/OFF CONTROL
1 15 LEVEL TRANSLATOR
ANALOG SWITCH
YA
XB B ON/OFF CONTROL
4 5 LEVEL TRANSLATOR
ANALOG SWITCH
YB ANALOG OUTPUTS/INPUTS
XC C ON/OFF CONTROL
10 6 LEVEL TRANSLATOR
ANALOG SWITCH
11
YC
13 14 7 LEVEL TRANSLATOR
ANALOG SWITCH
12
YD
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MC74HC4316A
MAXIMUM RATINGS
Symbol VCC VEE VIS Vin I Parameter Value Unit V V V V Positive DC Supply Voltage (Ref. to GND) (Ref. to VEE) 0.5 to + 7.0 0.5 to + 14.0 7.0 to + 0.5 VEE 0.5 to VCC + 0.5 Negative DC Supply Voltage (Ref. to GND) Analog Input Voltage DC Input Voltage (Ref. to GND) 0.5 to VCC + 0.5 25 750 500 450 DC Current Into or Out of Any Pin Power Dissipation in Still Air mA PD Plastic DIP* EIAJ/SOIC Package* TSSOP Package* mW Tstg TL Storage Temperature 65 to + 150 260 C C Lead Temperature, 1 mm from Case for 10 Seconds (Plastic DIP, SOIC or TSSOP Package) Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied, damage may occur and reliability may be affected. *Derating Plastic DIP: 10 mW/C from 65 to 125C EIAJ/SOIC Package: 7 mW/C from 65 to 125C TSSOP Package: 6.1 mW/C from 65 to 125C For high frequency or heavy load considerations, see Chapter 2 of the ON Semiconductor HighSpeed CMOS Data Book (DL129/D).
This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this highimpedance circuit. For proper operation, Vin and Vout should be constrained to the range GND v (Vin or Vout) v VCC. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or VCC). Unused outputs must be left open. I/O pins must be connected to a properly terminated line or bus.
Min 2.0
Max 6.0
Unit V V V V V
6.0 VEE
GND
VIO* TA
Operating Temperature, All Package Types Input Rise and Fall Time (Control or Enable Inputs) (Figure 10)
55 0 0 0 0
C ns
tr, tf
*For voltage drops across the switch greater than 1.2 V (switch on), excessive VCC current may be drawn; i.e., the current out of the switch may contain both VCC and switch input components. The reliability of the device will be unaffected unless the Maximum Ratings are exceeded.
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MC74HC4316A
Guaranteed Limit v 85C 1.5 2.1 3.15 4.2 0.5 0.9 1.35 1.8 Symbol VIH Parameter Test Conditions VCC V 2.0 3.0 4.5 6.0 2.0 3.0 4.5 6.0 6.0 55 to 25C 1.5 2.1 3.15 4.2 0.5 0.9 1.35 1.8 v 125C 1.5 2.1 3.15 4.2 0.5 0.9 1.35 1.8 Unit V Minimum HighLevel Voltage, Control or Enable Inputs Ron = Per Spec VIL Maximum LowLevel Voltage, Control or Enable Inputs Ron = Per Spec V Iin Maximum Input Leakage Current, Control or Enable Inputs Vin = VCC or GND VEE = 6.0 V 0.1 1.0 1.0 mA mA ICC Maximum Quiescent Supply Current (per Package) Vin = VCC or GND VEE = GND VIO = 0 V VEE = 6.0 6.0 6.0 2 4 20 40 40 160 NOTE: Information on typical parametric values can be found in Chapter 2 of the ON Semiconductor HighSpeed CMOS Data Book (DL129/D).
DC ELECTRICAL CHARACTERISTICS Digital Section (Voltages Referenced to GND) VEE = GND Except Where Noted
Guaranteed Limit v 85C 200 110 110 115 90 90 25 20 20 Symbol Ron Parameter Test Conditions VCC V 2.0* 45 4.5 6.0 2.0 4.5 4.5 6.0 2.0 4.5 4.5 6.0 6.0 VEE
V
55 to 25C 160 90 90 90 70 70 20 15 15
Unit W
Maximum ON Resistance
0.0 0.0 4.5 6.0 0.0 0.0 4.5 6.0 0.0 0.0 4.5 6.0 6.0
Vin = VIH VIS = VCC or VEE (Endpoints) IS v 2.0 mA (Figures 1, 2) Vin = VIH VIS = 1/2 (VCC VEE) IS v 2.0 mA Vin = VIL VIO = VCC or VEE Switch Off (Figure 3) Vin = VIH VIS = VCC or VEE (Figure 4)
DRon
Maximum Difference in ON Resistance Between Any Two Channels in the Same Package Maximum OffChannel Leakage Current, Any One Channel Maximum OnChannel Leakage Current, Any One Channel
Ioff
0.1
0.5
1.0
mA
Ion
6.0
6.0
0.1
0.5
1.0
mA
NOTE:
Information on typical parametric values can be found in Chapter 2 of the ON Semiconductor HighSpeed CMOS Data Book (DL129/D). *At supply voltage (VCC VEE) approaching 2.0 V the analog switchon resistance becomes extremely nonlinear. Therefore, for lowvoltage operation, it is recommended that these devices only be used to control digital signals.
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MC74HC4316A
Guaranteed Limit v 85C 50 8 7 Symbol tPLH, tPHL tPLZ, tPHZ tPZL, tPZH C Parameter Maximum Propagation Delay, Analog Input to Analog Output (Figures 8 and 9) VCC V 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 55 to 25C 40 6 5 v 125C 60 9 8 Unit ns Maximum Propagation Delay, Control or Enable to Analog Output (Figures 10 and 11) Maximum Propagation Delay, Control or Enable to Analog Output (Figures 10 and 11) Maximum Capacitance 130 40 30 140 40 30 10 160 50 40 175 50 40 10 200 60 50 250 60 50 10 ns ns ON/OFF Control and Enable Inputs pF Control Input = GND Analog I/O 35 35 35 Feedthrough 1.0 1.0 1.0 1. For propagation delays with loads other than 50 pF, see Chapter 2 of the ON Semiconductor HighSpeed CMOS Data Book (DL129/D). 2. Information on typical parametric values can be found in Chapter 2 of the ON Semiconductor HighSpeed CMOS Data Book (DL129/D). Typical @ 25C, VCC = 5.0 V 15 Power Dissipation Capacitance (Per Switch) (Figure 13)* pF CPD *Used to determine the noload dynamic power consumption: P D = CPD V CC2 f + ICC VCC . For load considerations, see Chapter 2of the ON Semiconductor HighSpeed CMOS Data Book (DL129/D).
Symbol BW Parameter Test Conditions VCC V VEE V Limit* 25C 150 160 160 Unit Maximum OnChannel Bandwidth or Minimum Frequency Response (Figure 5) OffChannel Feedthrough Isolation (Figure 6) fin = 1 MHz Sine Wave Adjust fin Voltage to Obtain 0 dBm at VOS Increase fin Frequency Until dB Meter Reads 3 dB RL = 50 W, CL = 10 pF fin Sine Wave Adjust fin Voltage to Obtain 0 dBm at VIS fin = 10 kHz, RL = 600 W, CL = 50 pF fin = 1.0 MHz, RL = 50 W, CL = 10 pF 2.25 4.50 6.00 2.25 4.50 6.00 2.25 4.50 6.00 2.25 4.50 6.00 2.25 4.50 6.00 2.25 4.50 6.00 2.25 4.50 6.00 2.25 4.50 6.00 2.25 4.50 6.00 2.25 4.50 6.00 2.25 4.50 6.00 2.25 4.50 6.00 2.25 4.50 6.00 2.25 4.50 6.00 MHz 50 50 50 40 40 40 60 130 200 30 65 100 dB Feedthrough Noise, Control to Switch (Figure 7) Vin v 1 MHz Square Wave (tr = tf = 6 ns) Adjust RL at Setup so that IS = 0 A RL = 600 W, CL = 50 pF RL = 10 kW, CL = 10 pF mVPP Crosstalk Between Any Two Switches (Figure 12) fin Sine Wave Adjust fin Voltage to Obtain 0 dBm at VIS fin = 10 kHz, RL = 600 W, CL = 50 pF fin = 1.0 MHz, RL = 50 W, CL = 10 pF 70 70 70 80 80 80 dB THD Total Harmonic Distortion (Figure 14) fin = 1 kHz, RL = 10 kW, CL = 50 pF THD = THDMeasured THDSource VIS = 4.0 VPP sine wave VIS = 8.0 VPP sine wave VIS = 11.0 VPP sine wave % 2.25 4.50 6.00 2.25 4.50 6.00 0.10 0.06 0.04 *Limits not tested. Determined by design and verified by qualification.
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MC74HC4316A
TBD
TBD
TBD
TBD
PLOTTER
MINI COMPUTER
DC ANALYZER
TBD
VCC
COMMON OUT
GND
VEE
MC74HC4316A
VCC
16
VCC
16
VCC N/C
VIH
Figure 3. Maximum Off Channel Leakage Current, Any One Channel, Test SetUp
VIS VCC 16 fin 0.1 mF ON RL VCC SELECTED CONTROL INPUT C L* VCC RL TO dB METER 16 fin 0.1 mF RL OFF RL C L* VCC TO dB METER
7 8 9 VEE
7 8 9 VEE
RL 7 8 9 VEE CONTROL
VCC
ANALOG OUT
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MC74HC4316A
VCC 16 ANALOG I/O ON ANALOG O/I 50 pF* TEST POINT ENABLE 50% CONTROL tPZL 7 8 9 SELECTED CONTROL INPUT VCC ANALOG OUT 50% tPZH 50% *Includes all probe and jig capacitance. tPHZ 10% 90% tPLZ tr tf VCC GND HIGH IMPEDANCE VOL VOH HIGH IMPEDANCE
POSITION 1 WHEN TESTING tPHZ AND tPZH 1 2 VCC 1 2 CONTROL OR ENABLE 8 9 VEE ON/OFF 50 pF* POSITION 2 WHEN TESTING tPLZ AND tPZL VCC 16 1 kW TEST POINT fin 0.1 mF RL
Figure 12. Crosstalk Between Any Two Switches, Test SetUp (Adjacent Channels Used)
VCC A 16 N/C ON/OFF N/C 10 mF fin ON RL 7 8 9 VEE CONTROL SELECTED CONTROL INPUT VEE C L* VIS
VCC 16
7 8 9
VCC
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MC74HC4316A
APPLICATIONS INFORMATION
0 10 20 30 dBm 40 50 60 70 80 90 100 1.0 2.0 FREQUENCY (kHz) 3.0 DEVICE SOURCE FUNDAMENTAL FREQUENCY
The Enable and Control pins should be at VCC or GND logic levels, VCC being recognized as logic high and GND being recognized as a logic low. Unused analog inputs/outputs may be left floating (not connected). However, it is advisable to tie unused analog inputs and outputs to VCC or VEE through a low value resistor. This minimizes crosstalk and feedthrough noise that may be picked up by the unused I/O pins. The maximum analog voltage swings are determined by the supply voltages VCC and VEE. The positive peak analog voltage should not exceed VCC. Similarly, the negative peak analog voltage should not go below VEE. In the example below, the difference between VCC and VEE is 12 V.
Therefore, using the configuration in Figure 16, a maximum analog signal of twelve volts peaktopeak can be controlled. When voltage transients above VCC and/or below VEE are anticipated on the analog channels, external diodes (Dx) are recommended as shown in Figure 17. These diodes should be small signal, fast turnon types able to absorb the maximum anticipated current surges during clipping. An alternate method would be to replace the Dx diodes with MOSORBs (MOSORBt is an acronym for high current surge protectors). MOSORBs are fast turnon devices ideally suited for precise dc protection with no inherent wear out mechanism.
VCC = 6 V +6V 6 V +6V SELECTED CONTROL INPUT VEE 8 6 V ANALOG I/O 16 ON ANALOG O/I +6V 6 V Dx
VCC Dx
Figure 16.
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MC74HC4316A
VCC = 5 V +5 V
ANALOG SIGNALS R* R* R* R* R*
16
16
HC4016A
CONTROL INPUTS 9 7
VCC = 12 V 12 V POWER SUPPLY R1 GND = 6 V R2 VEE = 0 V R1 = R2 VCC ANALOG INPUT SIGNAL C R3 R4 VEE ANALOG OUTPUT SIGNAL 12 V 0
12 VPP
1 OF 4 SWITCHES R1 = R2 R3 = R4
Figure 19. Switching a 0to12 V Signal Using a Single Power Supply (GND 0 V)
CHANNEL 4
1 OF 4 SWITCHES 1 OF 4 SWITCHES COMMON I/O 1 OF 4 SWITCHES 1 OF 4 SWITCHES INPUT 1 OF 4 SWITCHES + 0.01 mF 1 2 3 4 CONTROL INPUTS LF356 OR EQUIVALENT OUTPUT
CHANNEL 3
CHANNEL 2
CHANNEL 1
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MC74HC4316A
PACKAGE DIMENSIONS
A
16 9
B
1 8
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL. 4. DIMENSION B DOES NOT INCLUDE MOLD FLASH. 5. ROUNDED CORNERS OPTIONAL.
F S
T H G D
16 PL
SEATING PLANE
J T A
M
0.25 (0.010)
DIM A B C D F G H J K L M S
INCHES MIN MAX 0.740 0.770 0.250 0.270 0.145 0.175 0.015 0.021 0.040 0.70 0.100 BSC 0.050 BSC 0.008 0.015 0.110 0.130 0.295 0.305 0_ 10 _ 0.020 0.040
MILLIMETERS MIN MAX 18.80 19.55 6.35 6.85 3.69 4.44 0.39 0.53 1.02 1.77 2.54 BSC 1.27 BSC 0.21 0.38 2.80 3.30 7.50 7.74 0_ 10 _ 0.51 1.01
B
1 8
8 PL
0.25 (0.010)
G F
K C T
SEATING PLANE
X 45 _
M D
16 PL M
0.25 (0.010)
T B
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MC74HC4316A
PACKAGE DIMENSIONS
SOEIAJ16 F SUFFIX CASE 96601 ISSUE O
16
LE Q1 E HE M_ L DETAIL P
Z D e A VIEW P
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS D AND E DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS AND ARE MEASURED AT THE PARTING LINE. MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 5. THE LEAD WIDTH DIMENSION (b) DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE LEAD WIDTH DIMENSION AT MAXIMUM MATERIAL CONDITION. DAMBAR CANNOT BE LOCATED ON THE LOWER RADIUS OR THE FOOT. MINIMUM SPACE BETWEEN PROTRUSIONS AND ADJACENT LEAD TO BE 0.46 ( 0.018). DIM A A1 b c D E e HE L LE M Q1 Z MILLIMETERS MIN MAX 2.05 0.05 0.20 0.35 0.50 0.18 0.27 9.90 10.50 5.10 5.45 1.27 BSC 7.40 8.20 0.50 0.85 1.10 1.50 10 _ 0_ 0.70 0.90 0.78 INCHES MIN MAX 0.081 0.002 0.008 0.014 0.020 0.007 0.011 0.390 0.413 0.201 0.215 0.050 BSC 0.291 0.323 0.020 0.033 0.043 0.059 10 _ 0_ 0.028 0.035 0.031
b 0.13 (0.005)
M
A1 0.10 (0.004)
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MC74HC4316A/D