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    Booth Wallace Multiplier

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    rameshdurairaj
    This document summarizes a Booth encoded Wallace tree multiplier implemented in Verilog. It describes Booth encoding as a method to multiply positive and negative numbers efficiently. A Wallace tree is used to reduce the number of partial products generated. A carry look-ahead adder adds the final intermediate results. The document outlines the background, standard multiplier method, Booth's algorithm, modules used including a 2's complement generator, Booth encoder, partial product generator, Wallace tree and carry look-ahead adder. It provides details on the implementation including the 0.6um process, chip area, number of transistors and performance metrics.

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    Booth Wallace Multiplier

    Uploaded by

    rameshdurairaj
    178 views34 pages
    This document summarizes a Booth encoded Wallace tree multiplier implemented in Verilog. It describes Booth encoding as a method to multiply positive and negative numbers efficiently. A Wallace tree is used to reduce the number of partial products generated. A carry look-ahead adder adds the final intermediate results. The document outlines the background, standard multiplier method, Booth's algorithm, modules used including a 2's complement generator, Booth encoder, partial product generator, Wallace tree and carry look-ahead adder. It provides details on the implementation including the 0.6um process, chip area, number of transistors and performance metrics.

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    This document summarizes a Booth encoded Wallace tree multiplier implemented in Verilog. It describes Booth encoding as a method to multiply positive and negative numbers efficiently. A Wallace tree is used to reduce the number of partial products generated. A carry look-ahead adder adds the final intermediate results. The document outlines the background, standard multiplier method, Booth's algorithm, modules used including a 2's complement generator, Booth encoder, partial product generator, Wallace tree and carry look-ahead adder. It provides details on the implementation including the 0.6um process, chip area, number of transistors and performance metrics.

    Copyright:

    Attribution Non-Commercial (BY-NC)
    Download as PPT, PDF, TXT or read online from Scribd
    Download as ppt, pdf, or txt
    178 views34 pages

    Booth Wallace Multiplier

    Uploaded by

    rameshdurairaj
    This document summarizes a Booth encoded Wallace tree multiplier implemented in Verilog. It describes Booth encoding as a method to multiply positive and negative numbers efficiently. A Wallace tree is used to reduce the number of partial products generated. A carry look-ahead adder adds the final intermediate results. The document outlines the background, standard multiplier method, Booth's algorithm, modules used including a 2's complement generator, Booth encoder, partial product generator, Wallace tree and carry look-ahead adder. It provides details on the implementation including the 0.6um process, chip area, number of transistors and performance metrics.

    Copyright:

    Attribution Non-Commercial (BY-NC)
    Download as PPT, PDF, TXT or read online from Scribd
    Download as ppt, pdf, or txt
    of 34

    Booth Encoded Wallace Tree Multiplier

    Ruida Yun Nahid Rahman

    Importance
    Booth encoding is an effective method for multiplication of both positive and negative numbers. Wallace tree reduces the number of partial products to be added into 2 final intermediate results. Carry Look-ahead Adder used to add these results to generate the final output.

    Background of our work

    Multiplication of unsigned (+ve ) numbers


    Multiplicand Multiplier 0110 (=6) x 1011 (=11) ----------0110 0110 0000 0110 ----------01000010 (=66) Logically can be expressed as AND operation:

    if MR=1 assign MD if MR=0 assign all zeros

    In a 4-bit 2s complement number system..


    Multiplicand Multiplier 0110 (=6) x 1011 (=-5, signed number) ----------0110 0110 0000 0110 ----------01000010 (=66) Therefore, 8-bit result cannot be generated from 2 4bit inputs in a signed number system.

    Standard Multiplier Method


    Multiplicand Multiplier 00000110 x 11111011 --------------00000110 00000110 00000000 00000110 00000110 00000110 00000110 -----------------------11100010 (=6) (=-5, signed number)

    (=-30)

    Booths Algorithm
    Introduces a new symbol: indicating multiplication by -1. Multiplier is recoded in terms of 1, 0 & . Example: 1011 is recoded as: 10 AND operation changes as: if MR=1 assign MD if MR=0 assign all zeros if MR= assign -MD

    Our MR now becomes 4-bit again..


    Multiplicand 0110 (=6)

    Multiplier

    x 10 (=-5) --------------11111010 (-MD, sign extended) 00000000 (All zeros) 00000110 (MD, sign extended) 11111010 (-MD, sign extended) ---------------11100010 (=-30 , 8 bits of LSB)

    Generating

    Not possible to implement in hardware. Therefore, done by inspecting a multiplier bit and its previous bit and generating 2 control signals x and z. Whether the MR is , 1 or 0, depends on these signals according to:

    Reco ded MR 0

    M[i]

    M[i-1]

    1
    0

    0
    1 1

    1
    0 1

    0
    1 0

    1
    1 0

    Wallace Tree

    Tasks in Project
    Generating

    2s complement of MD for

    MD. Recoding MR/generating x and z. Generating partial products. Sign extension. Compressing the partial products. Adding the final 2 operands for multiplication result.

    Team Management
    Nahid:

    Booth Encoder Partial Product Generator

    Ruida:

    Wallace Tree Carry Look-ahead Adder

    (Smaller modules generated and tested as necessary Website: http://www.eecs.tufts.edu/~ryun01/vlsi)

    Modules in our project..

    2s Complement Generator

    Booth Encoder

    Partial Product Generator (a)

    Partial Product generator

    Wallace Tree

    Carry Look-ahead Adder

    Multiplier

    Chip Architecture

    Floor plan

    Final Layout

    No, its not a gun

    Verilog Simulation Results

    LVS for Final Chip

    Spectre_S Simulation for Final Chip

    Post-Layout Simulation for Final Chip

    Full Chip Implementation Details


    Fabrication Process: Final Chip Area: Number of PMOS: Number of NMOS: Total number of transistors: Speed: Power Dissipation:

    AMI 0.6u C5N 4.2mm*1.5mm 3040 3040 6080 20 MHz 15.14 mW

    Drawbacks

    Original Booths algorithm used where modified radix-4 algorithm could be used. Ripple Carry Adder used in 2s Complement Generator. Area and time not optimized; very slow chip.

    Goals Achieved
    As novice cadence users, our primary goal for this project was more of an academic nature:

    We have been able to achieve completeness and overall functional accuracy in our work. The project was foundational and served as a great learning experience. It also provided us with valuable experience in effective collaboration, work ethics, and a very enjoyable ongoing intercommunication between different project groups.

    Acknowledgements

    Our research advisor Prof. Valencia Joyner for all her support. All our new friends at the ECE department.

    Thank you..

    ~Ruida, Nahid.

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