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    Quartus Ii 13.0.1

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    Trần Ngọc Lâm
    QUARTUS II DEVELOPMENT SYSTEM is a fully-integrated design tool. A project is: + checked for Design Entry errors + compiled + simulated (functional or timing) + analyzed for timing + used to generate programming file. This course doesn't cover the architecture of Altera's FPGA LE logic element.

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    Quartus Ii 13.0.1

    Uploaded by

    Trần Ngọc Lâm
    239 views46 pages
    QUARTUS II DEVELOPMENT SYSTEM is a fully-integrated design tool. A project is: + checked for Design Entry errors + compiled + simulated (functional or timing) + analyzed for timing + used to generate programming file. This course doesn't cover the architecture of Altera's FPGA LE logic element.

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    QUARTUS II 13.0.1

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    © © All Rights Reserved

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    QUARTUS II DEVELOPMENT SYSTEM is a fully-integrated design tool. A project is: + checked for Design Entry errors + compiled + simulated (functional or timing) + analyzed for timing + used to generate programming file. This course doesn't cover the architecture of Altera's FPGA LE logic element.

    Copyright:

    © All Rights Reserved
    Download as PPT, PDF, TXT or read online from Scribd
    Download as ppt, pdf, or txt
    239 views46 pages

    Quartus Ii 13.0.1

    Uploaded by

    Trần Ngọc Lâm
    QUARTUS II DEVELOPMENT SYSTEM is a fully-integrated design tool. A project is: + checked for Design Entry errors + compiled + simulated (functional or timing) + analyzed for timing + used to generate programming file. This course doesn't cover the architecture of Altera's FPGA LE logic element.

    Copyright:

    © All Rights Reserved
    Download as PPT, PDF, TXT or read online from Scribd
    Download as ppt, pdf, or txt
    of 46

    QUARTUS II INTRODUCTION

    USING VERILOG DESIGN



    A TYPICAL FPGA CAD FLOW
    Design Entry
    Synthesis
    Functional Simulation
    Design correct?
    Timing Analysis and Simulation
    Timing requirements met?
    Fitting (Place and Route)
    Yes
    No
    Programming and Configuration
    Yes
    No
    QUARTUS II DEVELOPMENT
    SYSTEM
    Fully-integrated Design Tool

    Multiple Design Entry Methods
    Logic Synthesis
    Place and Route
    Simulation (functional and timing)
    Timing and Power Analysis
    Device Programming and Configuration
    Design Entry (1 of 2)
    The desired circuit is specified by:
    A schematic diagram
    A hardware description language,
    such as:
    Verilog
    VHDL
    AHDL
    Design Entry (2 of 2)
    Design Entry by a schematic diagram
    Design Entry by a hardware description
    language
    Synthesis
    The entered design is synthesized into a
    circuit that consists of the logic elements
    (LEs) provided in the FPGA chip.
    LE is the smallest unit of logic of Alteras
    FPGA. Its compact and provides advanced
    features with efficient logic ultilization.
    This course doesnt cover the architecture
    of Alteras FPGA
    LE logic element
    Fitting (placement and routing)
    The placement of the LEs defined in the
    netlist into the LEs in an actual FPGA chip,
    also choose routing wires in the chip to
    make the required connections between
    specific LEs
    Timing Analysis
    Analyze the propagation delays along the
    various paths in the fitted circuit
    Timing Simulation
    The fitted circuit is tested to verify both its
    functional correctness and timing
    Programming and Configuration
    The design circuit is implemented in a
    physical FPGA chip by programming the
    configuration switches that configure the
    LEs and establish the required wiring
    connections
    Quartus II Project Management
    What is a Project ?
    - A logic circuit or subcircuit
    - A project is:
    + checked for design entry errors
    + compiled
    + simulated (functional or timing)
    + analyzed for timing
    + used to generate programming file
    Quartus II works on one project at a time and
    keeps all information for that project in a single
    directory (folder).

    Quartus II Project New Project
    Select File > New Project Wizard
    New Project Wizard help us create a
    new project and preliminary project
    settings, including the following:
    Project name and directory
    Name of the top-level design entity
    Project files and libraries
    Target device family and device
    EDA tool settings
    You can change or add the settings of
    the project with the Settings
    command (Assignment menu)
    1
    2
    Quartus II Project Directory, Name, Top-
    Level Entity
    You can choose any
    directory name if you
    prefer. If we have not yet
    created the directory of
    the project, Quartus II
    asking if it should create
    the desired directory.
    The project must have a
    name, which is usually
    the same as the top-level
    design entity
    Quartus II Project Add Files
    To specify existing
    files should be
    included in the
    project.
    Click Next if we do
    not have any existing
    files.

    3
    Quartus II Project Family and Device
    Settings
    To specify the type of
    device in which the
    designed circuit will be
    implemented. In case of
    DE2 board, we choose:
    The device is
    EP2C35F672C6 which
    is the FPGA used on
    DE2 board
    The target device family
    is Cyclone II
    Quartus II Project EDA Tools
    Settings
    To specify any third-
    party tools that
    should be used. EDA
    is means Electronic
    Design Automation,
    a commonly used
    term for CAD
    software for
    electronic circuits.
    4
    Quartus II - Summary
    5
    Design Entry using Verilog An
    example
    module light(x1,x2,f);
    input x1,x2;
    output f;
    assign f = (x1&~x2)|(~x1&x2);
    endmodule
    Design Entry using Verilog Quartus II
    Text Editor (1 of 6)
    Select File >
    New to get
    the right
    figure, then
    choose
    Verilog HDL
    File, and
    click OK
    1
    2
    4
    3
    Design Entry using Verilog Quartus II
    Text Editor (2 of 6)
    Quartus II open the
    Text Window
    Editor. The default
    name of design file
    is Verilog1.v. The
    first step is to
    specify a name for
    the file that will be
    created. Select File
    > Save As
    Design Entry using Verilog Quartus II
    Text Editor (3 of 6)
    In the box labeled Save
    as type choose Verilog
    HDL File.
    In the box labeled
    File name , type light
    Put a checkmark in the
    box Add file to current
    project
    Click Save
    Design Entry using Verilog Quartus II
    Text Editor (4 of 6)
    Type the Verilog
    code of our
    design into Text
    Editor.
    Save the file
    light.v by choose
    File > Save.
    Design Entry using Verilog Quartus Text
    Editor (5 of 6)
    Design Entry using Verilog Quartus II Text
    Editor (6 of 6)
    We can change
    the options of
    Text Editor of
    Quartus II by
    the settings in
    Tools >
    Options > Text
    Editor
    Design Entry using Verilog Adding
    Design Files
    If light.v is not a part of
    the project, this file must
    be added to the project.
    For example: if you did
    not use the Quartus II
    Text Editor, then you
    place a copy of the file
    light.v, which you created
    using some other text
    editor, into the directory
    introductorial. To add this
    file to the project, click on
    the light.v file and click
    Open
    Compilation (1 of 2)
    Verilog code in the design file
    light.v is processed by the
    application program called the
    Compiler.
    The Compiler :
    - Analyze the code
    - Synthesize the circuit
    - Generate an implementation of
    the circuit for the target chip.
    Selecting Processing > Start
    Compilation
    1
    2
    Compilation (2 of 2)
    3
    Simulating Analysis & Synthesis
    1
    Simulating Analysis & Synthesis
    Simulating Start EDA Nestlist Writer
    2
    Simulating Start EDA Nestlist Writer
    Simulating Create VWF file
    3
    Simulating
    Simulating Set End Time
    4
    5
    Simulating Insert Node or Bus
    6
    7
    Simulating
    8
    9
    Simulating
    10
    Simulating
    Uncompleted Waveform
    Simulating Editing waveform
    Edit waveform
    Simulating Choose Simulator
    11
    12
    Simulating Run
    Run Functional Simulation
    Simulating Done!
    Completed Waveform
    Some references
    "Altera's Quartus

    II software is such a superior


    development environment that I am quickly
    forgetting about any other PLD (programmable logic
    device) design tool."
    Can Nguyen, Principal Staff Engineer,
    Broadband Communications Sector, Motorola

    "Quartus

    II software is superior compared to other


    programmable logic tool offerings, which allows us
    to focus our time on meeting customer needs, rather
    than laboring over tool usage.
    Dr. Greg Caso, VP Engineering, Escape Communications

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