Vlsi Wires

Lecture 14:
Wires
Outline
Introduction
Interconnect Modeling
Wire Resistance
Wire Capacitance
Wire RC Delay
Crosstalk
Repeaters
14: Wires
CMOS VLSI Design 4th Ed.
Introduction
Chips are mostly made of wires called interconnect
In stick diagram, wires set size
Transistors are little things under the wires
Many layers of wires
Wires are as important as transistors
Speed
Power
Noise
Alternating layers run orthogonally
14: Wires
Wire Geometry
Pitch = w + s
Aspect ratio: AR = t/w
Old processes had AR << 1
Modern processes have AR 2
Pack in many skinny wires
t
h
14: Wires
Layer Stack
AMI 0.6 mm process has 3 metal layers
M1 for within-cell routing
M2 for vertical routing between cells
M3 for horizontal routing between cells
Modern processes use 6-10+ metal layers
M1: thin, narrow (< 3l)
High density cells
Mid layers
Thicker and wider, (density vs. speed)
Top layers: thickest
For VDD, GND, clk
14: Wires
Interconnect Modeling
Current in a wire is analogous to current in a pipe
Resistance: narrow size impedes flow
Capacitance: trough under the leaky pipe must fill first
Inductance: paddle wheel inertia opposes changes in flow rate
Negligible for most
wires
14: Wires
Lumped Element Models

Wires are a distributed system
Approximate with lumped element models
N segments
R
R/N
R/N
C/N
C/N
R
C
L-model
C/2
R/N
R/N
C/N
C/N
R/2 R/2
C/2
p-model
C
T-model
3-segment p-model is accurate to 3% in simulation

L-model needs 100 segments for same accuracy!
Use single segment p-model for Elmore delay
14: Wires
Wire Resistance
r = resistivity (W*m)
r l
l
R
R
t w
w
R = sheet resistance (W/)
is a dimensionless unit(!)
Count number of squares
R = R * (# of squares)
l
w
t
1 Rectangular Block
R = R (L/W) W
14: Wires
4 Rectangular Blocks
R = R (2L/2W) W
= R (L/W) W
Choice of Metals
Until 180 nm generation, most wires were aluminum
Contemporary processes normally use copper
Cu atoms diffuse into silicon and damage FETs
Must be surrounded by a diffusion barrier
Metal
Bulk resistivity (mW cm)
Silver (Ag)
1.6
Copper (Cu)
1.7
Gold (Au)
2.2
Aluminum (Al)
2.8
Tungsten (W)
5.3
Titanium (Ti)
43.0
14: Wires
Example
Compute the sheet resistance of a 0.22 mm thick Cu
wire in a 65 nm process. The resistivity of thin film
Cu is 2.2 x 10-8 Wm. Ignore dishing.
2.2 108 m
R
0.10 W /
6
0.22 10 m
Find the total resistance if the wire is 0.125 mm wide
and 1 mm long. Ignore the barrier layer.
1000 m m
R 0.10 /
800 W
0.125 m m
14: Wires
10
Wire Capacitance
Wire has capacitance per unit length
To neighbors
To layers above and below
Ctotal = Ctop + Cbot + 2Cadj
s
w
layer n+1
h2
Ctop
t
h1
layer n
Cbot
Cadj
layer n-1
14: Wires
11
Capacitance Trends
Parallel plate equation: C = eoxA/d
Wires are not parallel plates, but obey trends
Increasing area (W, t) increases capacitance
Increasing distance (s, h) decreases capacitance
Dielectric constant
eox = ke0
e0 = 8.85 x 10-14 F/cm
k = 3.9 for SiO2
Processes are starting to use low-k dielectrics
k 3 (or less) as dielectrics use air pockets
14: Wires
12
Wire RC Delay
Estimate the delay of a 10x inverter driving a 2x
inverter at the end of the 1 mm wire. Assume wire
capacitance is 0.2 fF/mm and that a unit-sized
inverter has R = 10 KW and C = 0.1 fF.
tpd = (1000 W)(100 fF) + (1000 + 800 W)(100 + 0.6 fF) = 281 ps
14: Wires
13
Example
14: Wires
14
Wire Energy
Estimate the energy per unit length to send a bit of
information (one rising and one falling transition) in a
CMOS process.
E = (0.2 pF/mm)(1.0 V)2
14: Wires
= 0.2 pJ/bit/mm
= 0.2 mW/Gbps/mm
15
Crosstalk
A capacitor does not like to change its voltage
instantaneously.
A wire has high capacitance to its neighbor.
When the neighbor switches from 1-> 0 or 0->1,
the wire tends to switch too.
Called capacitive coupling or crosstalk.
Crosstalk effects
Noise on nonswitching wires
Increased delay on switching wires
14: Wires
16
Crosstalk Delay
Assume layers above and below on average are quiet
Second terminal of capacitor can be ignored
Model as Cgnd = Ctop + Cbot
Effective Cadj depends on behavior of neighbors
A
B
Miller effect
C
Cgnd
DV
Ceff(A)
MCF
Constant
VDD
Cgnd + Cadj
Switching with A
Cgnd
Switching opposite A
2VDD Cgnd + 2 Cadj 2
14: Wires
adj
Cgnd
17
Crosstalk Noise
Crosstalk causes noise on nonswitching wires
If victim is floating:
model as capacitive voltage divider
DVvictim
Cadj
Cgnd v Cadj
DVaggressor
Aggressor
DVaggressor
Cadj
Victim
Cgnd-v
14: Wires
DVvictim
18
Noise Implications
So what if we have noise?
If the noise is less than the noise margin, nothing
happens
Static CMOS logic will eventually settle to correct
output even if disturbed by large noise spikes
But glitches cause extra delay
Also cause extra power from false transitions
Dynamic logic never recovers from glitches
Memories and other sensitive circuits also can
produce the wrong answer
14: Wires
19
Repeaters
R and C are proportional to l
RC delay is proportional to l2
Unacceptably great for long wires
Break long wires into N shorter segments
Drive each one with an inverter or buffer
Wire Length: l
Driver
Receiver
N Segments
Segment
l/N
Driver
14: Wires
l/N
Repeater
l/N
Repeater
Repeater
Receiver
20
Repeater Design
How many repeaters should we use?
How large should each one be?
Equivalent Circuit
Wire length l/N
Wire Capacitance Cw*l/N, Resistance Rw*l/N
Inverter width W (nMOS = W, pMOS = 2W)
Gate Capacitance C*W, Resistance R/W
RwlN
R/W
14: Wires
Cwl/2N Cwl/2N
C'W
21
Repeater Results
Write equation for Elmore Delay
Differentiate with respect to W and N
Set equal to 0, solve
2 RC
RwCw
N
t pd
l
W
14: Wires
2 2
RC RwCw
~40 ps/mm
in 65 nm process
RCw
RwC
22
Repeater Energy
Energy / length 1.87CwVDD2
87% premium over unrepeated wires
The extra power is consumed in the large
repeaters
If the repeaters are downsized for minimum EDP:
Energy premium is only 30%
Delay increases by 14% from min delay
14: Wires
23

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Lecture 14:

CMOS VLSI Design 4th Ed.

CMOS VLSI Design 4th Ed.

CMOS VLSI Design 4th Ed.

CMOS VLSI Design 4th Ed.

CMOS VLSI Design 4th Ed.

Lumped Element Models

3-segment p-model is accurate to 3% in simulation

CMOS VLSI Design 4th Ed.

CMOS VLSI Design 4th Ed.

Bulk resistivity (mW cm)

CMOS VLSI Design 4th Ed.

CMOS VLSI Design 4th Ed.

CMOS VLSI Design 4th Ed.

CMOS VLSI Design 4th Ed.

CMOS VLSI Design 4th Ed.

CMOS VLSI Design 4th Ed.

CMOS VLSI Design 4th Ed.

CMOS VLSI Design 4th Ed.

2VDD Cgnd + 2 Cadj 2

CMOS VLSI Design 4th Ed.

CMOS VLSI Design 4th Ed.

CMOS VLSI Design 4th Ed.

CMOS VLSI Design 4th Ed.

CMOS VLSI Design 4th Ed.

CMOS VLSI Design 4th Ed.

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