VLSI DESIGN

Introduction to microelectronics
Speed/power performance of available technologies.
METAL-OXIDE-SEMICONDUCTOR (MOS)
Technology
Types of MOS devices are pMOS, nMOS, CMOS and BiCMOS devices.
•
nMOS FABRICATION
NMOS fabrication steps
Summary of An nMOS Process
• Processing takes place on a p-doped silicon crystal wafer on which is grown a 'thick'
layer of Si02.
• Mask 1-Pattern Si02 to expose the silicon surface in areas where paths in the
diffusion layer or gate areas of transistors are required. Deposit thin oxide over alL
For this reason, this mask is often known as the 'thinox' mask but some texts refer
to it as the diffusion mask.
• Mask 2-Pattern the ion implantation within the thinox region where depletion mode
devices are to be produced-self-aligning.
• Mask 3-Deposit polysilicon over all (I _5 Jlm thick typically), then pattern using
Mask 3. Using the same mask, remove thin oxide layer where it is not covered by
polysilicon.
• Diffuse n + regions into areas where thin oxide has been removed. Transistor drains
and sources are thus self-aligning with respect to the gate structure&.
• Mask 4--Grow thick oxide over all and then etch for contact cuts.
• Mask 5-Deposit metal and pattern with Mask 5!
• Mask 6-Would be required for the overglassing process step.
 CMOS FABRICATION STEPS
• There are different methods in which CMOS can be fabricated
1.Nwell process
2.Pwell process
3.Twin tub process
 Introduction
p-well Process to microelectronics
CMOS p-well inverter showing V00 and Vss substrate connections
In summary, typical processing steps are:
• Mask 1 - defines the areas in which the deep p-well diffusions are to take place.
• Mask 2 - defines the thinox regions, namely those areas where the thick oxide is
to be stripped and thin oxide grown to accommodate p- and n-transistors and wires.
• Mask 3 - used to pattern the polysilicon layer which is deposited after the thin
oxide.
• Mask 4 - A p-plus mask is now used (to be in effect "Anded" with Mask 2) to define
all areas where p-diffusion is to take place.
• Mask 5 - This is usually performed using the negative form of the p-plus mask and
defines those areas where n-type diffusion is to take place.
• Mask 6 - Contact cuts are now defined.
• Mask 7 - The metal layer pattern is defined by this mask.
Mask 8 - An overall passivation (overglass) layer is now applied and Mask 8 ts
needed to define the openings for access to bonding pads.
n-well Process
Cross-sectional view of n-well CMOS Inverter
 Twin-Tub Process

.• A logical extension of the p-well and n-well approaches is the twin-

tub fabrication process

Twin-tub structure.
BICMOS TECHNOLOGY
BICMOS Fabrication
BICMOS Fabrication In an n-well Process
• The fabrication of BICMOS is a combination of NMOS, PMOS and BJT.
In the fabrication process some layers are used such as channel stop
implant, thick layer oxidation and guard rings.
• Advantages of BiCMOS technology
• It has low power dissipation than bipolar technology alone.
• It has the bidirectional capability
• ince it is a grouping of bipolar and CMOS technologies we can use BJT
if speed is a critical parameter and we can use MOS if power is a
critical parameter and it can drive high capacitance loads with
reduced cycle time.
Drawbacks of BiCMOS technology
• The fabrication process of this technology is comprised of both the CMOS and bipolar technologies
increasing the complexity.
• Due to increase in the complexity of the fabrication process, the cost of fabrication also increases.
• As there are more devices, hence, less lithography.
BiCMOS technology and Applications
• It can be analyzed as AND function of high density and speed.
• This technology is used as an alternate of the previous bipolar, ECL and CMOS in the market.
• the BiCMOS speed performance is better than the that of bipolar( finite budget for power)
• This technology is well suited for the intensive input/output applications.
• The applications of BiCMOS were initially in RISC microprocessors rather than traditional CISC
microprocessors.
• This technology excels its applications, mainly in two areas of microprocessors such as memory and
input/output.
• It has a number of applications in analog and digital systems, resulting in the single chip spanning the
analog-digital boundary.
• It can be used for sample and hold applications as it provides high impedance inputs.
• This is also used in applications such as adders, mixers, ADC and DAC.
 LATCHU
P
• It is a short-circuit/low impedance channel generated between power and
ground rails of MOSFET results in high current leading to IC damage
• CAUSE
• +ve or - ve voltage spike on input or output
• Supply voltage exceeds the absolute maximum rating
• Due to high-power microwave interface
 Drain-to-Source Current IDS Versus Voltage VDS Relationships :

• Consider the diagram below in which electrons will flow source to drain.

• So, the drain current is given by

The Non-saturated Region :
• Let us consider the Id vs Vd relationships in the non-saturated region.
• The charge induced in the channel due to the voltage difference between the gate and the channel, Vgs
(assuming substrate connected to source).
• The voltage along the channel varies linearly with distance X from the source due to the IR drop in the
channel.
• In the non-saturated state the average value is Vds/2.
• Also the effective gate voltage Vg = Vgs – Vt where Vt, is the threshold voltage needed to invert the
charge under the gate and establish the channel.
So by combining the above two equations, we get
 The Saturated Region

Saturation begins when Vds = Vgs - Vt since at this point the IR drop in the channel
equals the effective gate to channel voltage at the drain and we may assume that the
current remains fairly constant as Vds increases further. Thus
MOS transistor characteristics .

Depletion mode
Enhancement mode
 Transconductance expresses the relationship between output current Ids and the input voltage V11 and is
defined as

To find an expression for g,. in terms of circuit and transistor parameters, consider that the charge in
channel Qc is such that

where 't is transit time. Thus change in current

but change in charge

so that

Now

In saturation
and substituting for

Alternatively,
 MOS TRANSISTOR FIGURE OF MERIT ro0

An indication of frequency response may be obtained from the parameter o where

This shows that switching speed depends on gate voltage above threshold and on carrier
mobility and inversely as the square of channel length. A fast circuit requires that g"' be
as high as possible.
 ASPECTS OF MOS TRANSISTOR THRESHOLD VOLTAGE Vt

The threshold voltage Vt may be expressed as:

𝑄 𝐵 −𝑄𝑆𝑆
𝑉 𝑡= ∅ 𝑚𝑠 2 ∅ 𝑓𝑁
𝐶0

QB = the charge per unit area in the depletion layer beneath the oxide

QSS = charge density at Si:Si02 interface

C0 = capacitance per unit gate area

ms = work function difference between gate and Si

fN = Fermi level potential between inverted surface and bulk Si.
To evaluate Vt each term is determined as follows:

VSB = substrate bias voltage (negative w.r.t. source for nMOS, positive for pMOS)
q = 1.6 X 10-19 coulomb
N = impurity concentration in the substrate (NA or ND as appropriate)
si= relative permittivity of silicon = 11.7
ni = intrinsic electron concentration (1.6 x 1010/cm3 at 300°K)
k = Boltzmann constant = 1.4 x 10-23 joule/°K
VLSI Design Flow
VLSI Design Flow
Y-Chart
 MOS circuits are formed on four basic layers:

 N-diffusion
 P-diffusion
 Polysilicon
 Metal

These layers are isolated by one another by thick or thin silicon dioxide insulating layers.
 Stick Diagrams

 VLSI design aims to translate circuit concepts onto silicon.

 Stick diagrams convey layer information through colour codes (or monochrome
encoding).

 Acts as an interface between symbolic circuit and the actual layout.

 Stick Diagrams

 It shows relative placement of components.

 Goes one step closer to the layout

 Helps plan the layout and routing

A stick diagram is a cartoon of a layout.

 Stick Diagrams

 Does not show

• Exact placement of components
• Transistor sizes
• Wire lengths, wire widths, tub boundaries.
• Any other low level details such as parasitics..
 Stick Diagrams – Notations
Metal 1

poly

ndiff

pdiff
Can also draw
in shades of
gray/line style.

Similarly for contacts, via, tub etc..

CMOS Stick Diagram Monochrome
Stick Diagrams – Some rules
Rule 1.
When two or more ‘sticks’ of the same type cross or
touch each other that represents electrical contact.
Stick Diagrams – Some rules
Rule 2.
When two or more ‘sticks’ of different type cross or
touch each other there is no electrical contact.
(If electrical contact is needed we have to show the connection explicitly).
Stick Diagrams – Some rules
Rule 3.
When a poly crosses diffusion it represents a
transistor.

Note: If a contact is shown then it is not a transistor.

 Stick Diagrams – Some rules
Rule 4.
In CMOS a demarcation line is drawn to avoid touching of p-diff with n-diff.
All PMOS must lie on one side of the line and all NMOS will have to be on
the other side.
Draw the Stick Diagram
VDD

x x

Gnd
How to draw Stick Diagrams
 Stick Diagrams
VDD
VDD
X

X
x x x
x X

Gnd Gnd
n-diffusion p-diffusion

polysilicon

Metal 1 Metal 2
 Scaling of MOS circuits
 The scaling down of feature size generally leads to improved performance

Scaled NMOS transisor

 SCALING MODELS AND SCALING FACTORS

• Constant electric field scaling model.

• Constant voltage scaling model.
• A combined voltage and dimension scaling model.
• In order to accommodate the three models, two scaling factors
• ---1/ and 1/-- are used
• 1/ is used for all other linear dimensions, both vertical and horizontal to the chip surface.
• 1/ --is chosen as the scaling factor for supply voltage VDD and gate oxide thickness D.
• For the constant field model =.
• For the constant voltage model =1.
 SCALING FACTORS FOR DEVICE PARAMETERS

1. Gate Area Ag
Ag = L.W

 where L and W are the channel length and width respectively.

 Both are scaled by 1/.

 Thus Ag is scaled by l/2

 SCALING FACTORS FOR DEVICE PARAMETERS

2. Gate capacitance Per Unit Area C0 or Cox

 SCALING FACTORS FOR DEVICE PARAMETERS

3. Gate capacitance Cg
Electrical Rules
Choice of layers
 Typical area capacitance values for MOS circuits

STANDARD UNIT OF CAPACITANCE □Cg

Typical sheet resistances (Rs) for MOS layers
SRAM core cell circuit
• The value is stored in the middle four transistors

• which form a pair of inverters connected in a loop

• The other two transistors control access to the memory cell by the bit lines

• A read or write is performed when the cell is selected

• To read, bit and bit’ are pre-charged to VDD before the select line is allowed to go

high
• One of the cell’s inverters will have its output at 1, and the other at 0; which inverter is 1

depends on the value stored

• for example, the right-hand inverter’s output is 0, the bit’ line will be drained to VSS

through that inverter’s pulldown and the bit line will remain high

• If the opposite value is stored in the cell, the bit line will be pulled low while bit’ remains

high

• To write, the bit and bit’ lines are set to the desired values, then select is set to 1.
Layout of a pair of SRAM core cells.
 Read-Only Memories

Read-Only Memories are nonvolatile

–Retain their contents when power is removed

•Mask-programmed ROMs use one transistor per bit

–Presence or absence determines 1 or 0
ROM Example
MOS NOR ROM
MOS NOR ROM Layout
MOS NAND ROM
MOS NAND ROM Layout
 DRAM

Observations

1T DRAM requires a sense amplifier for each bit line, due

to charge redistribution read-out.
DRAM memory cells are single ended in contrast to SRAM
cells.
The read-out of the 1T DRAM cell is destructive; read and
refresh operations are necessary for correct operation.

When writing a “1” into a DRAM cell, a threshold voltage is

lost. This charge loss can be circumvented by bootstrapping
the word lines to a higher value than VDD.
Content Addressable Memories (CAMs)
Content Addressable Memories (CAMs)
10T CAM Cell
 Serial Access Memories

􀂋Serial access memories do not use an address

•Shift Registers
•Serial In Parallel Out (SIPO)
•Parallel In Serial Out (PISO)
•Queues (FIFO, LIFO)
 Shift Register

Shift registersstore and delay data

􀂋Simple design: cascade of registers
•Watch your hold times!
 Serial In Parallel Out

􀂋1-bit shift register reads in serial data

•After N steps, presents N-bit parallel output
 Parallel In Serial Out

􀂋Load all N bits in parallel when shift = 0

•Then shift one bit out per cycle
 Queues

􀂋Queuesallow data to be read and written at different

rates.
􀂋Read and write each use their own clock, data
􀂋Queue indicates whether it is full or empty
􀂋Build with SRAM and read/write counters (pointers)
Programmable Logic Array
 PLAs

􀂋A Programmable Logic Arrayperforms any function in

sum-of-products form.
􀂋Literals: inputs & complements
􀂋Products / Minterms: AND of literals
􀂋Outputs: OR of Minterms
PLA Schematic
PLA Schematic & Layout
 Why Testing?

• To determine the presence of fault(s) in a given circuit.

– No amount of testing can guarantee that a circuit (chip, board or system) is fault-free.
– We carry out testing to increase our confidence in proper working of the circuit.
• Verification is an alternative to testing, used to verify the correctness of a design.
– Simulation-based approach.
– Formal methods.
 Need for Testing

• Physical defects are likely in manufacturing

– Missing connections (opens)
– Bridged connections (shorts)
– Imperfect doping, processing steps
– Packaging
• Yields are generally low
– Yield = Fraction of good die per wafer
• Need to weed out bad die before assembly
• Need to test during operation
– Electromagnetic interference, mechanical stress, electromigration, alpha particles
 Verification v/s Testing

Verifies correctness of Verifies correctness of

design manufactured h/w.

Performed by simulation, Two-part process:

h/w emulation, or formal 1. Test generation
methods. 2. Test application

Performed once prior to Test application

manufacturing. performed on every
manufactured device.

Responsible for quality of Responsible for quality of

design. devices.
Combinational and Sequential testing,
 Levels of Testing

• Testing can be carried out at various levels:

– Chip level
– Board level
– System level
• Cost :: Rule of 10
– It costs 10 times more to test a device as we move to the next higher level in the
product manufacturing process.
 Alternate Way of Classification

• Transistor level
• Gate lebel
• RTL level
• Functional level
• Behavioral level

PRIMARY FOCUS OF THIS COURSE:-

Chip-level testing

Gate-level design
 Some Real Defects in Chips

• Processing Faults
– missing contact windows, parasitic transistors, oxide breakdown
• Material Defects
– bulk defects (cracks, crystal imperfections)
– surface impurities (ion migration)
• Time-Dependent Failures
– dielectric breakdown, electron migration
• Packaging Failures
– contact degradation, seal leaks
 Faults, Errors and Failures

• Fault: A physical defect within a circuit or a system

– May or may not cause a system failure
• Error: Manifestation of a fault that results in incorrect circuit (system) outputs or states
– Caused by faults
• Failure: Deviation of a circuit or system from its specified behavior
– Fails to do what it should do
– Caused by an error
Fault Error Failure
 Faults in CMOS

S1: S-A-0

S2: short
 An example: a car with a flat tire

– Fault : pin puncture in the tire

– Error : Erroneous state of air pressure in the tire
– Failure : Car cannot be driven safely
 How To Do Test?

• Fault Modeling
– Identify target faults
– Limit the scope of test generation
• Test Generation
– Automatic or Manual
• Fault Simulation
– Assess completeness of tests
Testability Analysis
– Analyze a circuit for potential problem on test
generation
• Design For Testability
– Design a circuit for guaranteed test generation
– Introduce both area overhead and performance
degradation
 Overheads of Testing

• Design for Testability (DFT)

– Chip area overhead
– Yield reduction
– Performance overhead
• Software processes of test
– Test generation
– Fault simulation
• Manufacturing test
– Automatic Test Equipment (ATE) cost
– Test center operational cost
 Traditional Design Flow

• Conduct testing after design

 Design for Testability

Two key concepts

• Observability

• Controllability
 Examples of physical defects include

 Defects in silicon substrate

 Photolithographic defects

 Mask contamination and scratches

 Process variations and abnormalities

 Oxide defects
 Examples of physical defects include

The physical defects can cause electrical faults and logical faults. The electrical faults include:
 Shorts (bridging faults)

 Opens

 Transistor stuck-on, stuck-open

 Resistive shorts and opens

 Excessive change in threshold voltage

 Excessive steady-state currents

 Examples of physical defects include
The electrical faults in turn can be translated into logical faults. The logicalfaults include:

 Logical stuck-at-0 or stuck-at-I

 Slower transition (delay fault)

 AND-bridging, OR-bridging
 Design Strategies for test

1. Ad-Hoc DFT Method

2. Scan based approach
-Scan Design Techniques
-Scan Path
-Level sensitivity scan design (LSSD)
-Boundary Scan Test (BST)

3. Self-test and Built-in-self test

Figure: Level sensitivity scan design

Boundary Scan (JTAG: IEEE 1149.1b)
Built-In Self-Testing (BIST)
 Chip level Test Techniques

1. Regular Logic Arrays

2. Memories
3. Random Logic
 System level test techniques

Test Access Port (TAP):

• TCK(The Test Clock Input)

• TMS(The Test Mode Select)

• TDI(The Test Data Input)

• TDO(The Test Data Output)

• It also has an optional signal

• TRST*(The Test Reset Signal)

 System level test techniques

Test architecture

The test architecture consists of:

• The TAP interface pins

• A set of test-data registers

• An instruction register

• A TAP controller

Boundary scan register

Linear-Feedback Shift Register (LFSR)
 Layout for improved testability

As faults occur in a physical medium over Which we have control, some precautions taken at the layout level
can improve the likelihood of undesirable shorts and opens Gallay advances some rules for improving testability
based on observations of failure odes in nmos circuits that were builts. Shorts And opens in the metal layer and
shorts in the diffusion layer dominated the faults. It is quite probable that a completely different set Of rules
would be needed for each different cmos technology. This seems a fruitful area for further research