WELCOME

TO
TRAINING PROGRAMME
ON
8051 MICROCONTOLLER
&
APPLICATIONS
September 1-2,2008

DEPARTMENT OF ECE
MVGR COLLEGE OF ENGINEERING
July 4,CHINTALAVALASA,VIZIANAGARAM
2015

DAY 2
SESSION 1

July 4, 2015

Contents

More Instructions
Ports
Timers & Counters
Serial port communication
Interrupts

July 4, 2015

July 4, 2015

Logical Operations
ANL - ORL - XRL
EXAMPLE:
ANL

dest, source; dest=dest and source

MOV
R5,#89H;
10001001
ANL
R5,#08H;
00001000
therefore R5=00001000(08H)

July 4, 2015

Logical Operations.
CPL

Example:
MOV
L01: CPL
MOV
ACALL
SJMP

July 4, 2015

;1s complement
A,#55H
A
P1,A
DELAY
L01

;A=01010101 B

Logical Operations.
RR RL RRC RLC A
EXAMPLE:
RR A
RR:
RRC:

RL:
RLC:
July 4, 2015

C
7

LOOP and JUMP Instructions

DJNZ:
Write a program to clear ACC, then
add 3 to the accumulator ten time
Solution:
MOV
MOV
AGAIN: ADD
DJNZ
MOV

A,#0;
R2,#10
A,#03
R2,AGAING ;repeat until R2=0 (10 times)
R5,A

July 4, 2015

 Other conditional jumps :

JZ

Jump if A=0

JNZ

Jump if A/=0

DJNZ

Decrement and jump if A/=0

CJNE A,byte

Jump if A/=byte

CJNE reg,#data

Jump if byte/=#data

JC

Jump if CY=1

JNC

Jump if CY=0

JB

Jump if bit=1

JNB

Jump if bit=0

JBC

Jump if bit=1 and clear bit

July 4, 2015

SJMP and LJMP:

LJMP(long jump)
LJMP is an unconditional jump. It is a 3-byte instruction in
which the first byte is the opcode, and the second and third
bytes represent the 16-bit address of the target location. The
20byte target address allows a jump to any memory location
from 0000 to FFFFH.
SJMP(short jump)
In this 2-byte instruction. The first byte is the opcode and the
second byte is the relative address of the target location. The
relative address range of 00-FFH is divided into forward and
backward jumps, that is , within -128 to +127 bytes of memory
relative to the address of the current PC.
July 4, 2015

10

CJNE , JNC
Exercise:
Write a program that compare R0,R1.
If R0>R1 then send 1 to port 2,
else if R0<R1 then send 0FFh to port 2,
else send 0 to port 2.

July 4, 2015

11

CALL Instructions
Another control transfer instruction is the CALL
instruction, which is used to call a subroutine.
LCALL(long call)
In this 3-byte instruction, the first byte is the opcode
an the second and third bytes are used for the address
of target subroutine. Therefore, LCALL can be used
to call subroutines located anywhere within the 64K
byte address space of the 8051.
July 4, 2015

12

 ACALL (absolute call)

ACALL is 2-byte instruction in contrast to LCALL,
which is 13 bytes. Since ACALL is a 2-byte instruction,
the target address of the subroutine must be within 2K
bytes address because only 11 bits of the 2 bytes are used
for the address. There is no difference between ACALL
and LCALL in terms of saving the program counter on
the stack or the function of the RET instruction. The only
difference is that the target address for LCALL can be
anywhere within the 64K byte address space of the 8051
while the target address of ACALL must be within a 2Kbyte range.
July 4, 2015

13

I/O PROGRAMMING

P1.0
P1.1
P1.2
P1.3
P1.4
P1.5
P1.6
P1.7
RST
(RXD)P3.0
(TXD)P3.1
(INT0)P3.2
(INT1)P3.3
(T0)P3.4
(T1)P3.5
(WR)P3.6
(RD)P3.7
XTAL2
XTAL1
GND

July 4, 2015

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20

8051
(8031)

40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21

Vcc
P0.0(AD0)
P0.1(AD1)
P0.2(AD2)
P0.3(AD3)
P0.4(AD4)
P0.5(AD5)
P0.6(AD6)
P0.7(AD7)
EA/VPP
ALE/PROG
PSEN
P2.7(A15)
P2.6(A14)
P2.5(A13)
P2.4(A12)
P2.3(A11)
P2.2(A10)
P2.1(A9)
P2.0(A8)

14

I/O Port Programming.

Port 1 pins 1-8

Port 1 is denoted by P1.

P1.0 ~ P1.7
We use P1 as examples to show the operations on ports.
P1 as an output port (i.e., write CPU data to the external pin)
P1 as an input port (i.e., read pin data into CPU bus)

July 4, 2015

15

Other Pins
P1, P2, and P3 have internal pull-up resisters.
P1, P2, and P3 are not open drain.
P0 has no internal pull-up resistors and does not connects to
Vcc inside the 8051.
P0 is open drain.
Compare the figures of P1.X and P0.X.
However, for a programmer, it is the same to program P0, P1,
P2 and P3.
All the ports upon RESET are configured as output.

July 4, 2015

16

A Pin of Port 0
Read latch

TB2

Internal CPU
bus

Write to latch

Clk

P1.X
Q

TB1
Read pin

July 4, 2015

P0.X
pin

8051 IC

M1

P1.x
17

Tri-state Buffer
Output

Input

Tri-state control
(active high)

July 4, 2015

Low

Highimpedance
(open-circuit)

18

Port 0 pins 32-39

P0 is an open drain.
Open drain is a term used for MOS chips in the same way
that open collector is used for TTL chips.
When P0 is used for simple data I/O we must connect it to
external pull-up resistors.
Each pin of P0 must be connected externally to a 10K ohm
pull-up resistor.
With external pull-up resistors connected upon reset, port 0
is configured as an output port.

July 4, 2015

19

Port 0 with Pull-Up Resistors

Vcc

July 4, 2015

Port 0

P0.0
DS5000 P0.1
P0.2
8751
P0.3
P0.4
8951
P0.5
P0.6
P0.7

10 K

20

Dual Role of Port 0

When connecting an 8051/8031 to an external memory, the 8051
uses ports to send addresses and read instructions.
8031 is capable of accessing 64K bytes of external memory.
16-bit address P0 provides both address A0-A7, P2 provides
address A8-A15.
Also, P0 provides data lines D0-D7.
When P0 is used for address/data multiplexing, it is connected to the
74LS373 to latch the address.
There is no need for external pull-up resistors as shown in
Chapter 14.

July 4, 2015

21

74LS373
PSEN
ALE
P0.0
P0.7

74LS373

G
D

OE
OC
A0
A7
D0
D7

EA
P2.0

A8

P2.7

A15

8051
July
4, 2015

ROM

22

Reading ROM (1/2)

P0.0

2. 74373 latches the

address and send to
OE
ROM
OC
G 74LS373
A0

P0.7

A7

PSEN
ALE

1. Send address to
ROM

Address
D0
D7

EA
P2.0

A8

P2.7

A12

8051
July 4, 2015

ROM

23

Reading ROM (2/2)

PSEN
ALE
P0.0
P0.7

2. 74373 latches the

address and send to
ROM

74LS373

G
D

Address

OE
OC
A0
A7
D0
D7

EA

3. ROM send the

instruction back
P2.0

A8

P2.7

A12

8051
July
4, 2015

ROM

24

ALE Pin
The ALE pin is used for de-multiplexing the
address and data by connecting to the G pin of
the 74LS373 latch.
When ALE=0, P0 provides data D0-D7.
When ALE=1, P0 provides address A0-A7.
The reason is to allow P0 to multiplex address and
data.

July 4, 2015

25

Port 2 pins 21-28

Port 2 does not need any pull-up resistors since
it already has pull-up resistors internally.
In an 8031-based system, P2 are used to
provide address A8-A15.

July 4, 2015

26

Port 3 pins 10-17

Port 3 does not need any pull-up resistors since it already has
pull-up resistors internally.
Although port 3 is configured as an output port upon reset, this
is not the way it is most commonly used.
Port 3 has the additional function of providing signals.
Serial communications signal RxD, TxD Chapter 10
External interrupt /INT0, /INT1 Chapter 11
Timer/counter T0, T1 Chapter 9
External memory accesses in 8031-based system /WR,
/RD Chapter 14

July 4, 2015

27

Port 3 Alternate Functions

P3 Bit

Function

Pin

P3.0

RxD

10

P3.1

TxD

11

P3.2

INT0

12

P3.3

INT1

13

P3.4

T0

14

P3.5

T1

15

P3.6

WR

16

P3.7

RD

17

July 4, 2015

28

A Pin of Port 1
Read latch

TB2

Vcc
Load(L1)

Internal CPU
bus

Write to latch

Clk

P1.X
pin

P1.X
Q

M1

TB1

P0.x

Read pin

July 4, 2015

8051 IC

29

Hardware Structure of I/O Pin

Each pin of I/O ports
Internal CPU bus communicate with CPU
A D latch store the value of this pin
D latch is controlled by Write to latch
Write to latch 1 write data into the D latch
2 Tri-state buffer
TB1: controlled by Read pin
Read pin 1 really read the data present at the pin
TB2: controlled by Read latch
Read latch 1 read value from internal latch
A transistor M1 gate
Gate=0: open
Gate=1: close
July 4, 2015

30

Writing 1 to Output Pin P1.X

Read latch

Vcc

TB2

Load(L1) 2. output pin is

Vcc

1. write a 1 to the pin

Internal CPU
bus

Write to latch

Clk

P1.X
pin

P1.X
Q

M1

output 1

TB1
Read pin

July 4, 2015

8051 IC

31

Writing 0 to Output Pin P1.X

Read latch

Vcc

TB2

Load(L1) 2. output pin is

ground

1. write a 0 to the pin

Internal CPU
bus

Write to latch

Clk

P1.X
pin

P1.X
Q

M1

output 0

TB1
Read pin

July 4, 2015

8051 IC

32

Port 1 as Output Write to a Port

Send data to Port 1

BACK:

MOV
A,#55H
MOV
P1,A
ACALL
DELAY
CPL A
SJMP BACK

Let P1 toggle.
You can write to P1 directly.
July 4, 2015

33

Reading High at Input Pin

Read latch
1.

TB2

write a 1 to the pin MOV

P1,#0FFH
Internal CPU bus

2. MOV A,P1

Vcc

external pin=High
Load(L1)

P1.X pin

P1.X
Write to latch

Clk

M1

TB1
Read pin
3. Read pin=1 Read latch=0
Write to latch=1

July 4, 2015

8051 IC

34

Reading Low at Input Pin

Read latch
1.

Vcc

2. MOV A,P1

TB2

write a 1 to the pin

Load(L1)

external pin=Low

MOV P1,#0FFH
Internal CPU bus

P1.X pin

P1.X
Write to latch

Clk

M1

TB1
Read pin
3. Read pin=1 Read latch=0
Write to latch=1

July 4, 2015

8051 IC

35

Port 1 as Input Read from Port

In order to make P1 an input, the port must be programmed by writing 1 to

all the bit.

BACK:

MOV
MOV
MOV
MOV
SJMP

A,#0FFH
P1,A
A,P1
P2,A
BACK

;A=11111111B
;make P1 an input port
;get data from P0
;send data to P2

To be an input port, P0, P1, P2 and P3 have similar methods.

July 4, 2015

36

Instructions For Reading an Input Port

Following are instructions for reading external pins of ports:

Mnemonics

Examples

Description

MOV A,PX

MOV A,P2

Bring into A the data at P2

pins

JNB PX.Y,..

JNB P2.1,TARGET

Jump if pin P2.1 is low

JB PX.Y,..

JB P1.3,TARGET

Jump if pin P1.3 is high

MOV C,PX.Y

MOV C,P2.4

Copy status of pin P2.4 to CY

July 4, 2015

37

Read-Modify-Write Instructions
Mnemonics

Example

ANL

ANL P1,A

ORL

ORL P1,A

XRL

XRL P1,A

JBC PX.Y, TARGET

JBC P1.1, TARGET

CPL

CPL P1.2

INC

INC

DEC

DEC P1

DJNZ PX, TARGET

DJNZ P1,TARGET

MOV PX.Y,C

MOV P1.2,C

CLR PX.Y

CLR P1.3

SETB PX.Y

SETB P1.4

July 4, 2015

P1

38

Timer/Counter Logic

July 4, 2015

39

PROGRAMMING 8051 TIMERS

Timer 0 registers
TL0 ( timer 0 low byte )
TH0 ( timer 0 high byte )

July 4, 2015

40

Timer 1 registers
TL1 ( timer 1 low byte )
TH1 ( timer 1 high byte )

July 4, 2015

41

TMOD (timer mode) register

July 4, 2015

42

July 4, 2015

43

July 4, 2015

44

Operation of Timer on
Mode-0

July 4, 2015

45

Operation of Timer in
Mode 1

July 4, 2015

46

Operation of Timer in
Mode 2

July 4, 2015

47

Operation of Timer in
Mode 3

July 4, 2015

48

8051 SERIAL
COMMUNICATION

July 4, 2015

49

Basics of serial
communication

July 4, 2015

50

July 4, 2015

51

Start and stop bits

July 4, 2015

52

SCON (Serial control) register

July 4, 2015

53

SM0,SM1
SM0 and SM1 are D7 and D6 of the SCON

SM0
0
0
1
1

SM1
0
Serial Mode 0
1
Serial Mode 1,8 bit data,
1 stop bit, 1 start bit
0
Serial Mode 2
1
Serial Mode 3

July 4, 2015

54

Doubling the baud rate in the

8051
1. To use a higher frequency crystal
2. To change a bit in the PCON register
D7

D0

SMO
D

--

--

MOV A,PCON
SETB ACC.7
MOV PCON,A

July 4, 2015

--

GF1

GF0

PD

IDL

;place a copy of PCON in ACC

;make D7=1
;now SMOD=1 without
;changing any other bits
55

Baud rates for SMOD=0

Machine cycle freq. = 11.0592 MHz / 12 = 921.6 kHz
and
921.6 kHz / 32 = 28,800 Hz since SMOD = 0

July 4, 2015

56

Baud rates for SMOD=1

Machine cycle freq. = 11.0592 MHz / 12 = 921.6 kHz
and
921.6 kHz / 16 = 57,600 Hz since SMOD = 1

July 4, 2015

57

INTERRUPTS PROGRAMMING

July 4, 2015

58

Six interrupts in the 8051

July 4, 2015

59

Step in enabling an
interrupt

July 4, 2015

60

Writing the ISR

Example:
Writing the ISR for Timer0 interrupt

ORG 0000H
;reset
LJMP MAIN
ORG 000BH
;Timer0 entry point
T0ISR: .
;Timer0 ISR begins
.
RETI
;return to main program
MAIN: .
;main program
.
.
END
July 4, 2015

61

July 4, 2015

62

Interrupt priority upon reset

July 4, 2015

63

July 4, 2015

64

8051 Instruction Set

ACALL: Absolute Call

JC: Jump if Carry Set

PUSH: Push Value Onto Stack

ADD, ADDC: Add Acc. (With Carry)

JMP: Jump to Address

RET: Return From Subroutine

AJMP: Absolute Jump

JNB: Jump if Bit Not Set

RETI: Return From Interrupt

ANL: Bitwise AND

JNC: Jump if Carry Not Set

RL: Rotate Accumulator Left

CJNE: Compare & Jump if Not Equal

JNZ: Jump if Acc. Not Zero

RLC: Rotate Acc. Left Through Carry

CLR: Clear Register

JZ: Jump if Accumulator Zero

RR: Rotate Accumulator Right

CPL: Complement Register

LCALL: Long Call

RRC: Rotate Acc. Right Through Carry

DA: Decimal Adjust

LJMP: Long Jump

SETB: Set Bit

DEC: Decrement Register

MOV: Move Memory

SJMP: Short Jump

DIV: Divide Accumulator by B

MOVC: Move Code Memory

SUBB: Sub. From Acc. With Borrow

DJNZ: Dec. Reg. & Jump if Not Zero

MOVX: Move Extended Memory

SWAP: Swap Accumulator Nibbles

INC: Increment Register

MUL: Multiply Accumulator by B

XCH: Exchange Bytes

JB: Jump if Bit Set

NOP: No Operation

XCHD: Exchange Digits

JBC: Jump if Bit Set and Clear Bit

ORL: Bitwise OR

XRL: Bitwise Exclusive OR

POP: Pop Value From Stack

Undefined: Undefined Instruction

July 4, 2015

65

DAY 1
End of session 1

July 4, 2015

66