Timing and Control Instruction Cycle Memory Reference Instructions Input-Output and Interrupt Complete Computer Description

Basic Computer Orgsnization and Design
Lecture 11
Overview
Instruction Codes
Computer Registers
Computer Instructions
Timing and Control
Instruction Cycle
Memory Reference
Instructions
Input-Output and Interrupt
Complete
CSE 211, Computer Organization
and Computer
Architecture

Lecture 11
Introduction
Every different processor type has its own design (different

registers, buses, microoperations, machine instructions, etc)
Modern processor is a very complex device
It contains
Many registers
Multiple arithmetic units, for both integer and floating point calculations
The ability to pipeline several consecutive instructions to speed
execution
Etc.
However, to understand how processors work, we will start

with a simplified processor model

Lecture 11
Basic Computer
The Basic Computer has two components, a processor

and memory
The memory has 4096 words in it
4096 = 212, so it takes 12 bits to select a word in
memory
Each word is 16 bits long
CPU
RAM
0
15
40
95

Lecture 11
Instruction
Program
A sequence of (machine) instructions
(Machine) Instruction
A group of bits that tell the computer to perform a
specific operation (a sequence of micro-operation)
The instructions of a program, along with any needed
data are stored in memory
The CPU reads the next instruction from memory
It is placed in an Instruction Register (IR)
Control circuitry in control unit then translates the
instruction into the sequence of microoperations
necessary to implement it
CSE 211, Computer Organization and Architecture

Lecture 11
Instruction Format
A computer instruction is often divided into two parts

An opcode (Operation Code) that specifies the
operation for that instruction
An address that specifies the registers and/or locations
in memory to use for that operation
In the Basic Computer, since the memory contains 4096 (=
212) words, we needs 12 bit to specify which memory
address this instruction will use
In the Basic Computer, bit 15 of the instruction specifies
the addressing mode (0: direct addressing, 1: indirect
addressing)
Since the memory words, and hence the instructions, are
16 bits long, that leaves
3 bits
for the instructions opcode
Instruction
Format
15 14
12 11
Address
I Opcode
Addressing
mode

Lecture 11
Addressing Mode
The address field of an instruction can represent either

Direct address: the address in memory of the data to use (the address of the
operand), or
Indirect address: the address in memory of the address in memory of the data
to use
Direct addressing
Indirect addressing
22
457
0 ADD
457
35 1 ADD
300
300
1350
1350
Operand
Operand
AC
AC
Effective Address (EA)

The address, that can be directly used without modification to access an
operand for a computation-type instruction, or as the target address for a
branch-type instruction

Lecture 11
Processor Register
A processor has many registers to hold instructions,

addresses, data, etc
The processor has a register, the Program Counter (PC)
that holds the memory address of the next instruction
to get
Since the memory in the Basic Computer only has
4096 locations, the PC only needs 12 bits
In a direct or indirect addressing, the processor needs
to keep track of what locations in memory it is
addressing: The Address Register (AR) is used for this
The AR is a 12 bit register in the Basic Computer
When an operand is found, using either direct or
indirect addressing, it is placed in the Data Register
(DR). The processor then uses this value as data for its
operation
The Basic Computer has a single general purpose
register the Accumulator (AC)

Lecture 11
Processor Register
The significance of a general purpose register is that

it can be referred to in instructions
e.g. load AC with the contents of a specific memory location;
store the contents of AC into a specified memory location
Often a processor will need a scratch register to store

intermediate results or other temporary data; in the
Basic Computer this is the Temporary Register (TR)
The Basic Computer uses a very simple model of
input/output (I/O) operations
Input devices are considered to send 8 bits of character data to
the processor
The processor can send 8 bits of character data to output
devices
The Input Register (INPR) holds an 8 bit character

gotten from an input device
The Output Register (OUTR) holds an 8 bit character
to be send to an output device

Lecture 12
11
Processor Register
Registers in the Basic Computer

11
PC
11
Memory
4096 x 16
AR
15
IR
CPU
15
15
TR
7
OUTR
DR
7
15
INPR
AC
List of BC Registers
DR
AR
AC
IR
PC
TR
INPR
OUTR
16
12
16
12
16
8
8
Data Register
Holds memory operand
Address Register
Holds address for memory
Accumulator
Processor register
16
Instruction Register
Holds instruction cod
Program Counter
Holds address of instruction
Temporary Register
Holds temporary data
Input Register
Holds input character
Output Register
Holds output character

Lecture 12
12
Common Bus System
The registers in the Basic Computer are

connected using a bus
This gives a savings in circuitry over complete
connections between registers

Lecture 12
13
Common Bus System

S1
S0
Memory unit
4096 x 16
Write
Bus
7
Address
Read
AR
LD INR CLR
PC
LD INR CLR
DR
LD
E
INR
3
CLR
AC
ALU
LD
INR
4
CLR
INPR
IR
TR
LD
LD INR
OUTR
LD
CLR
Cloc
k

Lecture 12
14
Common Bus System
Three control lines, S2, S1, and S0 control which

register the bus selects as its input
S2
0
0
0
0
1
1
1
1
S1 S0 Register
0 0x
0 1 AR
1 0 PC
1 1 DR
0 0 AC
0 1 IR
1 0 TR
1 1 Memory
Either one of the registers will have its load signal

activated, or the memory will have its read signal
activated
Will determine where the data from the bus gets loaded
The 12-bit registers, AR and PC, have 0s loaded onto

the bus in the high order 4 bit positions
When the 8-bit register OUTR is loaded from the bus,
the data comes from the low order 8 bits on the bus

Lecture 13
15
Basic Computer Instructions
Basic Computer Instruction Format

1. Memory-Reference Instructions (OP-code = 000 ~ 110)
15
I
14 12 11
Opcode
0
Address
2. Register-Reference Instructions (OP-code = 111, I = 0)

15
0
12 11
Register operation
1 1
3. Input-Output Instructions
15
1
12 11
1 1
(OP-code =111, I = 1)
0
I/O operation

Lecture 13
16
Basic Computer Instructions

Symbol
AND
ADD
LDA
STA
BUN
BSA
ISZ
Hex Code
I=0
I=1
0xxx 8xxx
1xxx 9xxx
2xxx Axxx
3xxx Bxxx
4xxx Cxxx
5xxx
Dxxx
6xxx
Exxx
Description
AND memory word to AC
Add memory word to AC
Load AC from memory
Store content of AC into memory
Branch unconditionally
Branch and save return address
Increment and skip if zero
CLA
CLE
CMA
CME
CIR
CIL
INC
SPA
SNA
SZA
SZE
HLT
7800
7400
7200
7100
7080
7040
7020
7010
7008
7004
7002
7001
Clear AC
Clear E
Complement AC
Complement E
Circulate right AC and E
Circulate left AC and E
Increment AC
Skip next instr. if AC is positive
Skip next instr. if AC is negative
Skip next instr. if AC is zero
Skip next instr. if E is zero
Halt computer
INP
OUT
SKI
SKO
ION
IOF
F800
F400
F200
F100
F080
F040
Input character to AC
Output character from AC
Skip on input flag
Skip on output flag
Interrupt on
Interrupt off

Lecture 13
17
Instruction Set Completeness
A computer should have a set of instructions so that the user can

construct machine language programs to evaluate any function that is
known to be computable.
Instruction Types
Functional Instructions
- Arithmetic, logic, and shift instructions
- ADD, CMA, INC, CIR, CIL, AND, CLA
Transfer Instructions
- Data transfers between the main memory and the processor registers
- LDA, STA
Control Instructions
- Program sequencing and control
- BUN, BSA, ISZ
Input/output Instructions
- Input and output
- INP, OUT

Lecture 14
18
Control Unit
Control unit (CU) of a processor translates from machine

instructions to the control signals for the microoperations
that implement them
Control units are implemented in one of two ways
Hardwired Control
CU is made up of sequential and combinational circuits to generate the
control signals
Microprogrammed Control
A control memory on the processor contains microprograms that
activate the necessary control signals
We will consider a hardwired implementation of the control

unit for the Basic Computer

Lecture 14
19
Timing and Control
Control unit of Basic Computer
15
Instruction register (IR)

14 13 12
11 - 0
Other inputs
3x8
decoder
7 6543 210
D0
Combinational
Control
logic
D7
T15
T0
15 14 . . . . 2 1 0
4 x 16
decoder
4-bit
sequence
counter
(SC)
Increment (INR)
Clear (CLR)
Clock
Control
signals

Lecture 14
20
Timing Signals
- Generated by 4-bit sequence counter and 416 decoder

- The SC can be incremented or cleared.
- Example: T0, T1, T2, T3, T4, T0, T1, . . .
Assume: At time T4, SC is cleared to 0 if decoder output D3 is active.
Clock
T0
D3T4: SC 0
T1
T2
T3
T0
T1
T2
T3
T4
D3
CLR
SC
T4
T0

Lecture 15
21
Instruction Cycle
In Basic Computer, a machine instruction is executed in the

following cycle:
1. Fetch an instruction from memory
2. Decode the instruction
3. Read the effective address from memory if the instruction has an indirect
address
4. Execute the instruction
After an instruction is executed, the cycle starts again at step

1, for the next instruction
Note: Every different processor has its own (different) instruction cycle

Lecture 15
22
Fetch and Decode
Fetch and Decode
T0: AR PC (S0S1S2=010, T0=1)

T1: IR M [AR], PC PC + 1 (S0S1S2=111, T1=1)
T2: D0, . . . , D7 Decode IR(12-14), AR IR(0-11), I IR(15)
T1
S2
T0
S1
Bus
S0
Memory
unit
7
Address
Read
AR
LD
PC
INR
IR
LD
5
Clock
Common bus

Lecture 16
23
Flow Chart (Instruction Cycle)

Start
SC <-- 0
AR
<-- PC
T0
T1
IR <-- M[AR],
PC <-- PC + 1
T2
Decode Opcode in IR(12-14),

AR <-- IR(0-11),
I <-- IR(15)
(Register or I/O) = 1
(I/O) = 1
I
D7
= 0 (register)
T3
Execute
input-output
instruction
SC <-- 0
= 0 (Memory-reference)
T3
Execute
register-reference
instruction
SC <-- 0
= 0 (direct)
(indirect) = 1
I
T3
AR <-- M[AR]
T3
Nothing
Execute
memory-reference
instruction
SC <-- 0
T4

Lecture 16
24
Determining Type of Instruction
D'7IT3: AR M[AR]
D'7I'T3: Nothing
D7I'T3:Execute a register-reference
instr.
D7IT3: Execute an input-output instr.

Lecture 16
25
Register Reference Instruction
Register Reference Instructions are identified when

- D7 = 1, I = 0
- Register Ref. Instr. is specified in b0 ~ b11 of IR
- Execution starts with timing signal T3
r = D7 IT3 => Register Reference Instruction
Bi = IR(i) , i=0,1,2,...,11
CLA
CLE
CMA
CME
CIR
CIL
INC
SPA
SNA
SZA
SZE
HLT
r:
rB11:
rB10:
rB9:
rB8:
rB7:
rB6:
rB5:
rB4:
rB3:
rB2:
rB1:
rB0:
SC 0
AC 0
E0
AC AC
E E
AC shr AC, AC(15) E, E AC(0)
AC shl AC, AC(0) E, E AC(15)
AC AC + 1
if (AC(15) = 0) then (PC PC+1)
if (AC(15) = 1) then (PC PC+1)
if (AC = 0) then (PC PC+1)
if (E = 0) then (PC PC+1)
S 0 (S is a start-stop flip-flop)

Lecture 17
26
Memory Reference Instructions
Symbol
AND
ADD
LDA
STA
BUN
BSA
ISZ
Operation
Decoder
D0
D1
D2
D3
D4
D5
D6
Symbolic Description
AC AC M[AR]
AC AC + M[AR], E Cout
AC M[AR]
M[AR] AC
PC AR
M[AR] PC, PC AR + 1
M[AR] M[AR] + 1, if M[AR] + 1 = 0 then PC PC+1
- The effective address of the instruction is in AR and was placed there during
timing signal T2 when I = 0, or during timing signal T3 when I = 1
- Memory cycle is assumed to be short enough to complete in a CPU cycle
- The execution of MR instruction starts with T4
AND to AC
D0T4:
D0T5:
ADD to AC
D1T4:
D1T5:
DR M[AR]
AC AC DR, SC 0
Read operand
AND with AC
DR M[AR]
AC AC + DR, E Cout, SC 0
Read operand
Add to AC and store carry in E

Lecture 17
27
LDA: Load to AC
D2T4:
DR M[AR]
D2T5:
AC DR, SC 0
STA: Store AC
D3T4:
M[AR] AC, SC 0
BUN: Branch Unconditionally
D4T4:
PC AR, SC 0
BSA: Branch and Save Return Address
M[AR] PC, PC AR + 1
Memory, PC, AR at time T4
20
PC = 21
BSA
135
Next instruction
AR = 135
136
Subroutine
BUN
Memory, PC after execution

20
21
Next instruction
135
21
135
Subroutine
PC = 136
135
BSA
BUN
135

Lecture 17
28
BSA:
D5T4: M[AR] PC, AR AR + 1

D5T5: PC AR, SC 0
ISZ: Increment and Skip-if-Zero

D6T4: DR M[AR]
D6T5: DR DR + 1
D6T4: M[AR] DR, if (DR = 0) then (PC PC + 1), SC 0

Lecture 17
29
Flow Chart - Memory Reference

Memory-reference
instruction
Instructions
AND
ADD
D0T 4
DR M[AR]
D1T 4
DR M[AR]
D 0T 5
AC AC DR
SC 0
BUN
AC AC + DR
E Cout
SC 0
BSA
M[AR] PC
AR AR + 1
D 5T 5
D 3T 4
M[AR] AC
SC 0
DR M[AR]
D2T 5
AC DR
SC 0
ISZ
D 5T 4
PC AR
SC 0
STA
D2T 4
D 1T 5
D 4T 4
PC AR
SC 0
LDA
D6T 4
DR M[AR]
D6T 5
DR DR + 1
D 6T 6
M[AR] DR
If (DR = 0)
then (PC PC + 1)
SC 0

Lecture 18
30
Input/Output and Interrupt
A Terminal with a keyboard and a Printer

Input-Output Configuration
Input-output
terminal
Printer
Serial
communication
interface
Receiver
interface
Computer
registers and
flip-flops
OUTR
FGO
AC
INPR
OUTR
FGI
FGO
IEN
Input register - 8 bits

Output register - 8 bits
Input flag - 1 bit
Output flag - 1 bit
Interrupt enable - 1 bit
Keyboard
Transmitter
interface
INPR
FGI
Serial Communications Path

Parallel Communications Path
- The terminal sends and receives serial information

- The serial info. from the keyboard is shifted into INPR
- The serial info. for the printer is stored in the OUTR
- INPR and OUTR communicate with the terminal serially and with the AC
in parallel.
- The flags are needed to synchronize the timing difference between I/O
device and the computer

Lecture 18
31
Input/Output Instructions
D7IT3 = p
IR(i) = Bi, i = 6, , 11
INP
OUT
SKI
SKO
ION
IOF
p:
pB11:
pB10:
pB9:
pB8:
pB7:
pB6:
SC 0
AC(0-7) INPR, FGI 0
OUTR AC(0-7), FGO 0
if(FGI = 1) then (PC PC + 1)
if(FGO = 1) then (PC PC + 1)
IEN 1
IEN 0
Clear SC
Input char. to AC
Output char. from AC
Skip on input flag
Skip on output flag
Interrupt enable on
Interrupt enable off

Lecture 18
32
Interrupt Initiated Input/Output
- Open communication only when some data has to be passed --> interrupt.
- The I/O interface, instead of the CPU, monitors the I/O device.
- When the interface founds that the I/O device is ready for data transfer,
it generates an interrupt request to the CPU
- Upon detecting an interrupt, the CPU stops momentarily the task
it is doing, branches to the service routine to process the data
transfer, and then returns to the task it was performing.
IEN (Interrupt-enable flip-flop)

- can be set and cleared by instructions
- when cleared, the computer cannot be interrupted

Lecture 18
33
Flow Chart of Interrupt Cycle

R = Interrupt f/f
=0
Instruction cycle
IEN
=1
=1
=1
Interrupt cycle
Store return address

in location 0
M[0] PC
Fetch and decode

instructions
Execute
instructions
=0
INPR
OUTR
FGI
FGO
IEN

Input flag - 1 bit
Output flag - 1 bit
Branch to location 1
PC 1
FGI
=0
=1
FGO
IEN 0
R0
=0
R1
- The interrupt cycle is a HW implementation of a branch and save return address

operation.
- At the beginning of the next instruction cycle, the instruction that is read from
memory is in address 1.
- At memory address 1, the programmer must store a branch instruction that sends
the control to an interrupt service routine
- The instruction that returns the control to the original program is "indirect BUN 0"

Lecture 18
34
Register Transfer Operations in

Interrupt
Memory Cycle
Before interrupt
0
1
BUN
After interrupt cycle
1120
Main
Program
255
PC = 256
0
PC = 1
256
0
I/O
Program
1
BUN
1120
Main
Program
255
256
1120
1120
BUN
I/O
Program
0
BUN
Register Transfer Statements for Interrupt Cycle

- R F/F 1 if IEN (FGI + FGO)T0T1T2
T0T1T2 (IEN)(FGI + FGO): R 1
- The fetch and decode phases of the instruction cycle
must be modified Replace T0, T1, T2 with R'T0, R'T1, R'T2
- The interrupt cycle :
RT0:
AR 0, TR PC
RT1:
M[AR] TR, PC 0
RT2:
PC PC + 1, IEN 0, R 0, SC 0

Lecture 19
35
Complete Computer Design

start
SC 0, IEN 0, R 0
=0(Instruction
Cycle)
=1(Interrupt
Cycle)
RT0
RT0
AR PC
AR 0, TR PC
RT1
IR M[AR], PC PC + 1
RT1
M[AR] TR, PC 0
RT2
RT2
AR IR(0~11), I IR(15)
D0...D7 Decode IR(12 ~ 14)
=1(Register or I/O)
=1 (I/O)
D7IT3
Execute
I/O
Instruction
=0 (Register)
D 7IT3
Execute
RR
Instruction
PC PC + 1, IEN 0
R 0, SC 0
=0(Memory Ref)
D7
=1(Indir)
=0(Dir)
D7IT3
AR <- M[AR]
D7IT3
Execute MR
Instruction
INPR
OUTR
FGI
FGO
IEN
Idle
D7T4

Input flag - 1 bit
Output flag - 1 bit

Lecture 19
36
Fetch
Decode
Indirect
Interrupt
Memory-Reference
AND
ADD
LDA
STA
BUN
BSA
ISZ
RT0:
RT1:
RT2:
D7IT3:
RT0:
RT1:
RT2:
D0T4:
D0T5:
D1T4:
D1T5:
D2T4:
D2T5:
D3T4:
D4T4:
D5T4:
D5T5:
D6T4:
D6T5:
D6T6:
AR PC
IR M[AR], PC PC + 1
D0, ..., D7 Decode IR(12 ~ 14),
AR IR(0 ~ 11), I IR(15)
AR M[AR]
R1
AR 0, TR PC
M[AR] TR, PC 0
PC PC + 1, IEN 0, R 0, SC 0
DR M[AR]
AC AC DR, SC 0
DR M[AR]
AC AC + DR, E Cout, SC 0
DR M[AR]
AC DR, SC 0
M[AR] AC, SC 0
PC AR, SC 0
M[AR] PC, AR AR + 1
PC AR, SC 0
DR M[AR]
DR DR + 1
M[AR] DR, if(DR=0) then (PC PC + 1),
SC 0

Lecture 19
37
Register-Reference
CLA
CLE
CMA
CME
CIR
CIL
INC
SPA
SNA
SZA
SZE
HLT
Input-Output
INP
OUT
SKI
SKO
ION
IOF
D7IT3 = r
IR(i) = Bi
r:
rB11:
rB10:
rB9:
rB8:
rB7:
rB6:
rB5:
rB4:
rB3:
rB2:
rB1:
rB0:
D7IT3 = p
IR(i) = Bi
p:
pB11:
pB10:
pB9:
pB8:
pB7:
pB6:
(Common to all register-reference instr)

(i = 0,1,2, ..., 11)
SC 0
AC 0
E0
AC AC
E E
AC shr AC, AC(15) E, E AC(0)
AC shl AC, AC(0) E, E AC(15)
AC AC + 1
If(AC(15) =0) then (PC PC + 1)
If(AC(15) =1) then (PC PC + 1)
If(AC = 0) then (PC PC + 1)
If(E=0) then (PC PC + 1)
S0
(Common to all input-output instructions)
(i = 6,7,8,9,10,11)
SC 0
AC(0-7) INPR, FGI 0
OUTR AC(0-7), FGO 0
If(FGI=1) then (PC PC + 1)
If(FGO=1) then (PC PC + 1)
IEN 1
IEN 0

Lecture 19
38
Design of a Basic Computer(BC)
Hardware Components of BC
A memory unit: 4096 x 16.
Registers:
AR, PC, DR, AC, IR, TR, OUTR, INPR, and SC
Flip-Flops(Status):
I, S, E, R, IEN, FGI, and FGO
Decoders:
a 3x8 Opcode decoder
a 4x16 timing decoder
Common bus: 16 bits
Control logic gates:
Adder and Logic circuit: Connected to AC
Control Logic Gates
- Input Controls of the nine registers
- Read and Write Controls of memory
- Set, Clear, or Complement Controls of the flip-flops
- S2, S1, S0 Controls to select a register for the bus
- AC, and Adder and Logic circuit

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Basic Computer Orgsnization and Design

Basic Computer Orgsnization and Design

Every different processor type has its own design (different

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