8255 A

8255 A
Programmable Peripheral
Interface
Fig: The connections between an 8086,8255 and three

peripherals
Pin Diagram
40 pins
Consists of three 8 bit ports
named Port A(PA) ,Port
B(PB) and Port C (PC)
The ports A,B,C can be
programmed as input or
output ports
Pin functions
Data bus(D0-D7):
These are 8-bit bi-directional buses, connected to 8086 data
bus for transferring data.
CS:
This is Active Low signal. When it is low, then only this chip is
enabled.
RD:
This is Active Low signal, when it is Low read operation will
take place.
WR:
This is Active Low signal, when it is Low Write operation
will take place.
CS(A -A A1
A0
Selected entity
Address
0
1):
0 are used
0
A and control
These pins
to0select thePort
ports
register.
0
0
1
Port B
0
Port C
Control register
RESET:
This is used to reset the device. That means clear control
registers.
PA0-PA7:
It is the 8-bit bi-directional I/O pins used to send the
data to peripheral or to receive the data from peripheral.
PB0-PB7: Similar to PA
PC0-PC7:
This is also 8-bit bidirectional I/O pins. These lines are
divided into two groups.
PC0 to PC3 (Lower Groups)
PC4 to PC7 (Higher groups)
Internal block diagram
Data Bus buffer:

It is a bidirectional 8-bit Data buffer.
Used to interface 8255 with system bus.
Upon execution of the processors input or output
instructions, data and control /status words are received
or transmitted by the buffer
The direction of data buffer is decided by Read/Write
Control Logic.
Read/Write Control Logic:

Manages all data transfer between chip and processor
on accepting the control signals from control and address buses
of system
Control signal are
and
Address signals are A0,A1,and
Group A and Group B control:

The chip is further divided into Group A and B and send the
command to the individual control blocks.
Group A send the control signal to port A and Port C

PC7-PC4 (Upper).
Group B send the control signal to port B and Port C

PC3-PC0 (Lower) .
Fig: Address decoding and connections between the 8086

and the 8255
Address Decoding
The NAND gate output should be 0 , which is
connected to CS pin of 8255 in order to enable chip
When the address lines A7 to A3 and A0 have the following
bit status, and that is when the chip gets selected/enabled.
The Address of Port A,B,C can be computed as,

When A2 and A1 are 00 ,then A7 A0 is 1100 0000
i.e.C0H .This is the address of Port A.
ENTITY
ADDRESS(HEX)
CONTROL REGISTER
C6
PORT A
C0
PORT B
C2
PORT C
C4
Address of the ports of 8255 for the connection
PROGRAMMING THE PPI

Programming the chip involves writing of a particular word to
the control register
The control register is an 8 bit register which can be written
into .
The bits of this word (control word) will decide the way the
ports of the chip are to be configured.
Ports A,B and C are grouped into two -Groups A and B .
Group A consists of Port A and upper 4 bits (PC4-PC7) of Port
C.
Group B then obviously includes Port B and Port C lower (PC0
PC3 ) .
Group A ports can have three operational modes(0,1 and 2)
Group B ports have only two modes of operation.
Fig: Control word format of

8255
MODES OF OPERATION
Three modes
Mode 0: Basic input/output
Mode 1 : Strobed input/output
Mode 3 : Bi-directional bus
Mode 0 :
This is the simplest and most widely used mode .
Two 8 bit ports A and B ,and the 4 bit ports Port C upper
and Port C lower ,may be used independently .
Data is simply taken in from an input port or given to an output
port .
The specifications of this mode are
i) Two 8 bit ports and two 4 bit ports
ii) Any port can be input or output
iii) Outputs are latched
iv) Inputs are not latched
v) 16 different input/output combinations possible
Example:
Q) Design the control word to configure the ports of an
8255 chip in mode 0 ,with ports B and Port C upper (PCU)
as inputs and Port A and Port C lower (PCL) as outputs.
Solution:
Mode 0: I/O mode ,D7=1
D7
D6
D5
D1
D0
1 0 0 0 1 0 1
D4
0
D3
D2
Mode 1:
This is the handshaking mode .Handshaking implies
data transfer in which the communicating devices
exchange request and acknowledge control signals.
For 8255 operating in this mode ,Ports A and B pins are
used for data transfer ,while 4 bits each of Port C are
used for generating the handshaking signals
Specification
i) Each group contains one 8 bit port and one 4 bit port
.The 4 bit port is used for handshaking.
ii) The 8 bit port can be either an input or an output.
iii) Input and output are latched.
iv) The 4 bit port is used for control and status of the 8 bit
data port.
v) Interrupt logic is supported.
Mode 2:
This is the bidirectional mode.
Only Group A can use this mode .Here Port A is used for
transmitting as well as receiving data.
Handshaking signals generated by the upper 4 bits of
Port C maintain bus discipline for proper flow of data in the
required direction.
Basic functional definitions of this mode is
i)Used in Group A only.
ii) One 8-bit, bi-directional bus port (Port A) and a 5- bit control
port
(Port C).
iii) Both inputs and outputs are latched.
iv)The 5-bit control port (Port C) is used for control and status
for the 8- bit, bi-directional bus port (Port A).
BIT SET RESET MODE

This is a special mode and is applicable only for the bits of
Port C.
In the control word format ,if the MSB is made 0 (D7=0) the bit
set /reset (BSR)mode takes effect .
In this mode , any bit of Port C can be set or reset by
specifying the bit which has to be set or reset .
But at a time ,only one bit can be addressed and that bit is
to be either set or reset .
Fig: BSR
control word
format
Example
Q) Write the BSR control words for the following cases.
i)PC0 to be set
ii) PC7 to be reset
iii)PC1 to be set
Solution:
Note:-Refer control word format of BSR

mode in previous slide

8255 A

Uploaded by

Copyright:

Available Formats

8255 A

Uploaded by

Document Information

Original Title

Copyright

Available Formats

Share this document

Share or Embed Document

Sharing Options

Did you find this document useful?

Is this content inappropriate?

Copyright:

Available Formats

8255 A

Uploaded by

Copyright:

Available Formats

8255 A

Fig: The connections between an 8086,8255 and three

Internal block diagram

Data Bus buffer:

Read/Write Control Logic:

Address signals are A0,A1,and

Group A and Group B control:

Group A send the control signal to port A and Port C

Group B send the control signal to port B and Port C

Fig: Address decoding and connections between the 8086

The Address of Port A,B,C can be computed as,

PROGRAMMING THE PPI

Fig: Control word format of

BIT SET RESET MODE

Note:-Refer control word format of BSR

You might also like