ENCS 533 Advanced Digital

Design

Lecture 2
Introduction to VHDL
Introduction

VHDL: VHSIC Hardware Description

Language
VHSIC: Very High Speed Integrated Circuits
Well look at some simple design in VHDL
These examples can be tried in Active HDL
tool or other tools
A simple example
NAND gate
a

b nandgate
c

1st thing to do:

Say what it looks like to the rest of the system
List of inputs and outputs
Port map
 Port map: inputs and outputs
a ENTITY nandgate IS
nandgate PORT ( a, b: IN STD_LOGIC;
b c
c: OUT STD_LOGIC );
END;

Uppercase is a VHDL keyword

Lower case is name I have chosen

Mode can be IN or OUT

 Port map: inputs and outputs
a ENTITY nandgate IS
nandgate PORT ( a, b: IN STD_LOGIC;
b c
c: OUT STD_LOGIC );
END;

Type STD_LOGIC can be 0, 1, X or U.

X means unknown
U means uninitialized
 Architecture
a ENTITY nandgate IS
nandgate PORT ( a, b: IN STD_LOGIC;
b c
c: OUT STD_LOGIC );
END;

Now we know how many inputs and outputs

Next we say how outputs derive values from inputs:
Architecture
 Architecture
a ENTITY nandgate IS
nandgate PORT ( a, b: IN STD_LOGIC;
b c
c: OUT STD_LOGIC );
END;

ARCHITECTURE simple OF nandgate IS

BEGIN
c <= a NAND b;
END;
Simulate it

Check our design by giving it inputs

Simulator says what the output would do

Output is 0 when both inputs are 1:

It works
Multiple architectures
We can give more than 1 architecture
Distinguish them by different names
ARCHITECTURE simple OF nandgate IS
BEGIN
c <= a NAND b;
END;

ARCHITECTURE complicated OF nandgate IS

BEGIN
c <= NOT ( a AND b );
END;
BEGIN and END statements
A block is a group of statements that should
be treated as one

C: Block defined by { and }

for (i=1; i<=n; i++)
{
a[i]=i;
b[i]=a[i]*a[i];
}
BEGIN and END statements
A block is a group of statements that should
be treated as one

VHDL: Block defined by BEGIN and END

FOR i IN ( 1 TO N ) LOOP
BEGIN
a(i) = i;
b(i) = a(i) * a(i);
END LOOP;
Semicolons
; indicates end of statement.
Statements that "open up" a block don't take
semicolons:
C:
for (i=1; i<=n; i++); /* WRONG semicolon */
{; /* ALSO WRONG semicolon */
a[i]=i;
b[i]=a[i]*a[i];
}
Semicolons
; indicates end of statement.
Statements that "open up" a block don't take
semicolons:
VHDL:
FOR i IN ( 1 TO N ) LOOP; --WRONG semicolon
BEGIN; --ALSO WRONG semicolon
a(i) = i;
b(i) = a(i) * a(i);
END LOOP;
ENTITY doesnt need a BEGIN
ENTITY nandgate IS
PORT ( a, b: IN STD_LOGIC; c: OUT STD_LOGIC );
END;

ARCHITECTURE simple OF nandgate IS

BEGIN
c <= a NAND b;
END;
Style issues

VHDL is not case sensitive.

In (black and white) books, VHDL keywords
are normally in one particular case
In editors, VHDL keywords are normally in
one particular colour
 Style issues
These are the same:
ENTITY nandgate IS
PORT ( a, b: IN STD_LOGIC; c: OUT STD_LOGIC);
END;

entity NANDGATE is
port ( A, B: in std_logic; C: out std_logic);
end;

entity nandgate is
port ( a, b: in std_logic; c: out std_logic);
end;
Spaces, indents and line breaks
Have no effect on code meaning
Used to enhance clarity
These are the same:
ENTITY nandgate IS
PORT ( a, b: IN STD_LOGIC; c: OUT STD_LOGIC);
END;

ENTITY nandgate IS
PORT ( a, b: IN STD_LOGIC;
c: OUT STD_LOGIC);
END;
Annotating END statements
ENTITY nandgate IS
PORT ( a, b: IN STD_LOGIC; c: OUT STD_LOGIC);
END;
ARCHITECTURE simple OF nandgate IS
BEGIN
c <= a NAND b;
END;

Its good style to say what you are ENDing

Annotating END statements
ENTITY nandgate IS
PORT ( a, b: IN STD_LOGIC; c: OUT STD_LOGIC);
END;
ARCHITECTURE simple OF nandgate IS
BEGIN
c <= a NAND b;
END ARCHITECTURE simple;

Its good style to say what you are ENDing

Often helps avoid bugs or confusion
Usually optional
Comments

Comments are introduced by two dashes

-- This is a comment
Libraries

void main ()
{
printf(My first C program);
}

ERROR: printf not found

Libraries

#include <stdio.h>
void main ()
{
printf(My first C program);
}

Works OK
The IEEE library
ENTITY nandgate IS a
PORT ( a, b: IN STD_LOGIC; b nandgate
c
c: OUT STD_LOGIC);
END ENTITY nandgate;
ARCHITECTURE simple OF nandgate IS
BEGIN
c <= a NAND b;
END ARCHITECTURE simple;

Error message Cannot recognise type STD_LOGIC.

Opening libraries
Definition of STD_LOGIC is held in library
Must open library in order to get at definitions
Main library is called IEEE

LIBRARY IEEE;
USE IEEE.XXXX.YYYY

XXXX is sub-library (package)

YYYY is feature that you want to use.
Opening libraries
Definition of STD_LOGIC is held in library
Must open library in order to get at definitions
Main library is called IEEE

LIBRARY IEEE;
USE IEEE.XXXX.ALL

If you want to open all features of the package

Using STD_LOGIC
LIBRARY ieee;
USE ieee.std_logic_1164.all;

ENTITY nandgate IS
a
PORT ( a, b: IN STD_LOGIC;
b nandgate
c: OUT STD_LOGIC ); c
END ENTITY nandgate;

ARCHITECTURE simple OF nandgate IS

BEGIN
c <= a NAND b;
END ARCHITECTURE simple;
Questions
What is the block diagram for this entity declaration?
ENTITY question1 IS
PORT ( a: IN STD_LOGIC; b: OUT STD_LOGIC;
c: IN STD_LOGIC; d: OUT STD_LOGIC );
END ENTITY question1;

What is wrong with this architecture (2 problems)?

ARCHITECTURE simple OF question1 IS
BEGIN
b <= a NAND c;
END ARCHITECTURE complicated;
What is the block diagram for this entity declaration?

ENTITY question1 IS
PORT ( a: IN STD_LOGIC; b: OUT STD_LOGIC;
c: IN STD_LOGIC; d: OUT STD_LOGIC );
END ENTITY question1;
Questions

What is wrong with this architecture?

ARCHITECTURE simple OF question1 IS
BEGIN
b <= a NAND c;
END ARCHITECTURE complicated;

Mismatch in architecture names

Output d is never assigned a value
Example 2

Arithmetic Logic Unit

Heart of a microprocessor
1st part of the assignment
To build ALU we need
Conditionals
Signals that are many bits wide
Arithmetic on signals
Conditionals
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;

b equals
c
Conditionals
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;

ENTITY equals IS a
PORT ( a, b: IN STD_LOGIC;
c: OUT STD_LOGIC); b equals
c
END ENTITY equals;
Conditionals
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;

ENTITY equals IS a
PORT ( a, b: IN STD_LOGIC;
c: OUT STD_LOGIC); b equals
c
END ENTITY equals;

ARCHITECTURE number1 OF equals IS

BEGIN
c <= '1' WHEN a=b ELSE '0';
END ARCHITECTURE number1;
Signals that are more than 1 bit
b c0
0
a
0

4 b1 c1
a 4 a
1
4 c
b c2
b 2
a
2

b3 c3
a
3

STD_LOGIC_VECTOR(0 TO 3)
Four members a(0), a(1), a(2) and a(3).
Each is of type STD_LOGIC.
Example of 4-bit device

b
LIBRARY ieee;
0 c0
a USE ieee.std_logic_1164.ALL;
0

b1 c1
a
1
ENTITY orgate IS
b c2 PORT
2
a
2
( a, b: IN STD_LOGIC_VECTOR(0 TO 3);
b3 c3 c: OUT STD_LOGIC_VECTOR(0 TO 3));
a
3 END ENTITY orgate;
Example of 4-bit device

b
ARCHITECTURE number1 OF orgate IS
0 c0
a
0
BEGIN
b1 c1 C(0) <= a(0) OR b(0);
a
1 C(1) <= a(1) OR b(1);
b
2
c2 C(2) <= a(2) OR b(2);
a
2
C(3) <= a(3) OR b(3);
b3 c3
a END ARCHITECTURE number1;
3
Example of 4-bit device

b
ARCHITECTURE number2 OF orgate IS
0 c0
a
0
BEGIN
b1 c1 c <= a OR b;
a
1 END ARCHITECTURE number2;
b c2
2
a
2

b3 c3
a
3

The compiler can figure out that

a,b,c are 4 bits wide
Example of 4-bit device

b
ARCHITECTURE number3 OF orgate IS
0 c0
a
0
BEGIN
b1 c1 C(0 TO 3) <= a(0 TO 3) OR b(0 TO 3);
a
1 END ARCHITECTURE number3;
b c2
2
a
2

b3 c3
a
3

Making the loop explicit

STD_LOGIC_VECTOR values

Single bit STD_LOGIC assignment:

a <= 1; --single quotes

4-bit STD_LOGIC_VECTOR assignment:

a <= 1110; -- double quotes.
 Direction of numbering

Can number upwards or downwards

a: STD_LOGIC_VECTOR(0 TO 3);

a <= 1110;
Element 0 a: STD_LOGIC_VECTOR(3 DOWNTO 0);
Element 1
Element 2 a <= 1110;
Element 3
Element 3
Element 2
Element 1
Element 0

Both represent the same decimal number

14 if its unsigned; -2 if its signed
Direction of numbering
In digital logic design bit 0 is usually lsb
So in VHDL index usually counts downwards
a: STD_LOGIC_VECTOR(0 TO 3);

a <= 1110;
Element 0 a: STD_LOGIC_VECTOR(3 DOWNTO 0);
Element 1
Element 2 a <= 1110;
Element 3
Element 3
Element 2
Element 1
Element 0
Arithmetic on STD_LOGIC_VECTORs

Comparator
4
a
4 g
b

g <= 1 WHEN a>b ELSE 0;

Signed or unsigned?
1111 is +15 or 1?
1110 is +14 or 2?
Arithmetic on STD_LOGIC_VECTORs

VHDL has two different versions of +,-,>,< etc.

STD_LOGIC_SIGNED
STD_LOGIC_UNSIGNED
Import one or the other
Arithmetic on STD_LOGIC_VECTORs
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_signed.ALL;

ENTITY comp IS 1111 will be interpreted as -1

PORT ( a, b: IN STD_LOGIC_VECTOR(3 DOWNTO 0);
g: OUT STD_LOGIC);
END ENTITY comp;

ARCHITECTURE simple OF comp IS

BEGIN
g <= 1 WHEN a>b ELSE 0;
END ARCHITECTURE simple;
Arithmetic on STD_LOGIC_VECTORs
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.ALL;

ENTITY comp IS 1111 will be interpreted as 15

PORT ( a, b: IN STD_LOGIC_VECTOR(3 DOWNTO 0);
g: OUT STD_LOGIC);
END ENTITY comp;

ARCHITECTURE simple OF comp IS

BEGIN
g <= 1 WHEN a>b ELSE 0;
END ARCHITECTURE simple;
 ALU example
16
Opcode Operation
a 16 00 a+b
16 alu c 01 ab
b
10 a and b
2 11 a or b
opcode
16 bit ALU
Operation is selected by opcode
 ALU example
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_signed.ALL;

ENTITY alu IS
PORT ( a, b: IN STD_LOGIC_VECTOR(15 DOWNTO 0);
opcode: IN STD_LOGIC_VECTOR(1 DOWNTO 0);
c: OUT STD_LOGIC_VECTOR(15 DOWNTO 0) );
END ENTITY alu;
ALU example
ARCHITECTURE simple OF alu IS
BEGIN
c <= a + b WHEN opcode=00
ELSE a - b WHEN opcode=01
ELSE a OR b WHEN opcode=10
ELSE a AND b WHEN opcode=11;
END ARCHITECTURE simple;
Simulate the ALU

a = 0000000001110111, 0077H.
b = 0000000000000001, 0001H.
As opcode changes 00,01,10,11, (0,1,2,3)
output gets a+b, then a-b, then a OR b then a AND c.
Synthesise the example

It works as expected
Synthesise to gate level description
Much quicker and easier than doing it the old
fashioned way
More flexible too
Summary

Intro to VHDL
Basic examples