MALVIYA NATIONAL INSTITUTE OF TECHNOLOGY, JAIPUR.

SYSTEM DESIGN LAB. INCHARGE: Ms. KOMAL SWAMI.

SUBMITTED BY: MANEESH Kr. CHOUDHARY ID:2013PEV5042

SUBMITTED TO: Ms. KOMAL SWAMI

INDEX
Sr DATE no
1 2 3 4 5 6 7 8 5-08-2013 5-08-2013 5-08-2013 5-08-2013 5-08-2013 5-08-2013 5-08-2013 5-08-2013

TITLE
DESIGN AND GATE USING VHDL CODE DESIGN OR GATE USING VHDL CODE DESIGN NAND GATE USING VHDL CODE DESIGN NOR GATE USING VHDL CODE DESIGN XOR GATE USING VHDL CODE DESIGN XNOR GATE USING VHDL CODE DESIGN NOT GATE USING VHDL CODE DESIGN FULL ADDDER GATE USING VHDL CODE

SIGN

EXPERIMENT NO. 1 Aim: To write the VHDL code for AND gate. Tools: Model sim student version VHDL software. Theory: 1. AND gate is a basic logic gate. 2. It gives the output high when all the inputs are high otherwise low. 3. It obeys commutative law (A.B = B.A). 4. It obeys associative law (i.e. (A.(B.C) = (A.B).C). TRUTH TABLE:
A 0 0 1 1 B 0 1 0 1 A.B 0 0 0 1

Code: library ieee; use ieee.std_logic_1164.all; entity and_2 is port (a,b: in bit; c: out bit); end entity; architecture arc_and_2 of and_2 is begin

c<=(a AND b); end architecture;

Screenshots:

Conclusion: We can check the operation either by writing the test bench or by forcing the inputs to see the output. Also there is a provision for looking outputs and inputs waveforms using clock generation method.

EXPERIMENT NO.2 Aim: To write the VHDL code for OR gate. Tools: Model sim student version VHDL software. Theory: 1. OR gate is a basic logic gate . 2. It gives the output high when one or more inputs are high otherwise low. 3. It obeys commutative law (A+B = B+A). 4. It obeys associative law (i.e. (A+(B+C) = (A+B)+C). TRUTH TABLE:
A 0 0 1 1 B 0 1 0 1 A+B 0 1 1 1

Code: library ieee; use ieee.std_logic_1164.all; entity or_2 is port (a,b: in bit; c: out bit); end entity; architecture arc_or_2 of or_2 is begin

c<=(a OR b); end architecture; Screenshots:

Conclusion: We can check the operation either by writing the test bench or by forcing the inputs to see the output. Also there is a provision for looking outputs and inputs waveforms using clock generation method.

EXPERIMENT NO.3 Aim: To write the VHDL code for NAND gate. Tools: Model sim student version VHDL software. Theory: 1. NAND gate is a universal logic gate . 2. It gives the output high when one or more inputs are low otherwise low. 3. It obeys commutative law {(A.B)= (B.A)}. 4. It does not obeys associative law. TRUTH TABLE:
A 0 0 1 1 B 0 1 0 1 (A.B) 1 1 1 0

Code: library ieee; use ieee.std_logic_1164.all; entity nand_2 is port (a,b: in bit; c: out bit); end entity; architecture arc_nand_2 of nand_2 is begin

c<=(a NAND b); end architecture; Screenshots:

Conclusion: We can check the operation either by writing the test bench or by forcing the inputs to see the output. Also there is a provision for looking outputs and inputs waveforms using clock generation method.

EXPERIMENT NO.4 Aim: To write the VHDL code for NOR gate. Tools: Model sim student version VHDL software. Theory: 1. NOR gate is a universal logic gate . 2. It gives the output high when all the inputs are low otherwise low. 3. It obeys commutative law{(A+B) = (B+A)}. 4. It does not obeys associative law. TRUTH TABLE:
A 0 0 1 1 B 0 1 0 1 (A+B) 1 0 0 0

Code: library ieee; use ieee.std_logic_1164.all; entity nor_2 is port (a,b: in bit; c: out bit); end entity; architecture arc_nor_2 of nor_2 is begin

c<=(a NOR b); end architecture; Screenshots:

Conclusion: We can check the operation either by writing the test bench or by forcing the inputs to see the output. Also there is a provision for looking outputs and inputs waveforms using clock generation method.

EXPERIMENT NO.5 Aim: To write the VHDL code for EX-OR gate. Tools: Model sim student version VHDL software. Theory: 1. EX-OR gate is a Derived logic gate . 2. It gives the output high when both the inputs are different. 3. It obeys commutative law(Aex-orB = Bex-orA). 4. It obeys associative law TRUTH TABLE:

A 0 0 1 1

B 0 1 0 1

A ex-or B 0 1 1 0

Code: library ieee; use ieee.std_logic_1164.all; entity xor_2 is port (a,b: in bit; c: out bit); end entity; architecture arc_xor_2 of xor_2 is begin

c<=(a XOR b); end architecture; Screenshots:

Conclusion: We can check the operation either by writing the test bench or by forcing the inputs to see the output. Also there is a provision for looking outputs and inputs waveforms using clock generation method.

EXPERIMENT NO.6 Aim: To write the VHDL code for X-NOR gate. Tools: Model sim student version VHDL software. Theory: 1. X-NOR gate is a derived logic gate . 2. It gives the output high when both inputs are same otherwise low. 3. It obeys commutative law(A x-nor B = B x-nor A). 4. It obeys associative law. 5. It is also called even no. of ones detector. TRUTH TABLE:
A B A xnor B 1 0 0 1

0 0 1 1

0 1 0 1

Code: library ieee; use ieee.std_logic_1164.all; entity xnor_2 is port (a,b: in bit; c: out bit); end entity;

architecture arc_xnor_2 of xnor_2 is begin c<=(a XNOR b); end architecture; Screenshots:

Conclusion: We can check the operation either by writing the test bench or by forcing the inputs to see the output. Also there is a provision for looking outputs and inputs waveforms using clock generation method.

EXPERIMENT NO.7 Aim: To write the VHDL code for NOT gate. Tools: Model sim student version VHDL software. Theory: 1. NOT gate is a basic logic gate . 2. It just inverts the input logic. 3. It is a single input gate. 4. It is also called as inverter. TRUTH TABLE:
Input 0 1 output 1 0

Code: library ieee; use ieee.std_logic_1164.all; entity not_2 is port (a: in bit; b: out bit); end entity; architecture arc_not_2 of not_2 is begin b<=(NOT a); end architecture;

Screenshots:

Conclusion: We can check the operation either by writing the test bench or by forcing the inputs to see the output. Also there is a provision for looking outputs and inputs waveforms using clock generation method.

EXPERIMENT NO.8 Aim: To write the VHDL code for FULL ADDER. Tools: Model sim student version VHDL software. Theory: 1. It is combinational circuit which adds three bits including previous carry gives sum and carry out for next higher bit. 2. SUM = (A XOR B XOR C) 3. CARRY =(A.B) + (B.C) + (A.C) TRUTH TABLE
A 0 0 0 0 1 1 1 1 B 0 0 1 1 0 0 1 1 C 0 1 0 1 0 1 0 1 SUM 0 1 1 0 1 0 0 1 Carry 0 0 0 1 0 1 1 1

Code: library ieee; use ieee.std_logic_1164.all; entity full_adder is port (a,b,c: in bit; sum, carry: out bit); end entity; architecture arc of full_adder is

begin sum<=a xor b xor c; carry=(a and b)or(b and c)or(c and a); end architecture; Screenshots:

Conclusion: We can check the operation either by writing the test bench or by forcing the inputs to see the output. Also there is a provision for looking outputs and inputs waveforms using clock generation method.