CONTROL UNIT

Fetch Cycle

• Fetch Cycle occurs at the beginning of each instruction cycle.

It causes an instruction to be fetched from memory.
MAR-Memory address register
• MAR is connected to the address lines of the system bus. It
specifies the address in memory for a read or write operation.
MBR- Memory buffer register
• MBR is connected to the data lines of the system bus. It
contains the value to be stored in memory or the last value
read from memory.
PC- Program counter
• PC holds the address of the next instruction to be fetched.
 IR-Instruction register

• IR holds the opcode of the current instruction.

• The fetch cycle consists of three steps and four
micro operations. The sequence of events are
given below.
T1 : MAR (PC)
Tt2 : MBR Memory
PC (PC) + 1
T3: IR (MBR)
• Where , t1, t2, t3- Time units(clock pulses).
• During the first time unit, the contents of the PC
are transferred to the MAR.
• During the second time unit, the contents of
memory location specified by MAR are
transferred to the MBR. Increment the contents
of PC by 1.
• During the third time unit , the contents of MBR
are transferred to the IR.
 Indirect cycle

• After the instruction is fetched, the next step is to fetch

source operands. If the instruction specifies and
indirect address, then an indirect cycle must precede
the execute cycle. The sequence of events is given
below.
T1 : MAR (IR Address))
T2 : MBR Memory
T3 : IR(Address) (MBR( Address))
• During the first time unit, the address portion of the IR
is transferred to the MAR.
• During the second time unit , the contents of
memory location specified by MAR are
transferred to MBR.
• During the third time unit, the address field of
the IR is updated from the MBR.
• Now the IR contains a direct address rather
than an indirect address.
 Execute cycle

• Fetch, indirect and interrupt cycles are simple and

predictable.
• Each involves a small, fixed sequence of micro operations.
• This is not true of the execute cycle. For a machine with ‘N’
different opcodes, there are ‘N’ different sequence of micro
operations can occur.
• Consider the following instruction.
ADD R1,X
• It adds the contents of the location X to register R1. To
execute this instruction, the following sequence of events
is needed.
T1 : MAR (IR Address))
T2 : MBR Memory
T3 : IR (R1)+(MBR)
• During the first time unit, the address portion
of the IR is loaded into the MAR.
• During the second time unit, the contents of
memory location specified by MAR are
transferred to MBR.
• During the third time uni0t, the contents of R1
and MBR are added by the ALU
 Interrupt cycle

• After the completion of the execute cycle, a test is made to determine

whether any enabled interrupts, the interrupt cycle occurs. The sequence of
events are given below.
T1 : MBR (PC)
T2 : MAR Save address.
PC Routine Address
T3 : Memory (MBR)
• During the first time unit, the contents of the PC are transferred to the MBR.
• During the second time unit, the MAR is loaded with the address at which
the contents of the PC are to be saved. The PC is loaded with the address of
the start of the interrupt processing routine.
• During the third time unit, the contents of the MBR are transferred to the
memory.
•  
 Instruction cycle

•The flowchart for instruction cycle is shown in

the Fig.
•IT defines the complete sequence of micro
operations, depending only on the instruction
sequence and the interrupt pattern.
•Assume a 2- bit register called the instruction
cycle code(ICC). The ICC designates the state of
the processor.
• At the end of each of the four cycles. The ICC
is set appropriately.
• The indirect cycle is always followed by the
execute cycle. The interrupt cycle is always
followed by the fetch cycle.
• For both the execute and fetch cycles, the next
cycle depends on the state of the system.
ICC Operation
00 Fetch cycle
01 Indirect cycle
10 Execute cycle
11 Interrupt cycle
 STRUCTURE OF CONTROL UNIT

The structure of control unit is shown in the fig. 1.23

• The inputs of the control unit are given below.
• Instruction register
• It holds the opcode of the current instruction is used to
determine which micro operations to perform during execute
cycle.
• Flags
• Flags are needed by the control unit to determine the status of
the processor and the outcome of previous ALU operations.
• For example , for the ISZ (Increment and skip if Zero)
instruction , the control unit will increment the PC if the Zero
flag is set.
 Clock
• It is referred to as the processor clock time or the clock
cycle time. The control unit causes one micro operation
or set of simultaneous micro operations to be
performed for each clock pulse.
• Control signals from control bus
• The control bus portion of the system bus provides
signals (interrupt signals and acknowledgements) to the
control unit.
• The outputs of the control unit are given below.
• Control signals within CPU
• Control signals that cause data to be moved from one
register to another.
• Control signals that activate the specific ALU functions.
• Control signals to control bus
– Control signals to memory
– Control signals to the I/O modules.
• In the fetch cycle, the control unit sending the
following control signals simultaneously.
• A control signal that opens gates, allowing the
contents of the MAR on to the address bus.
• A memory read control signal on the control bus.
• A control signal that allowing the contents of the
data bus to be stored in the MBR.
• Control signals to logic that add 1 to the contents
of the PC and store the result back to the PC
•Then the control unit sends a control signals that
opens gates between the MBR and IR.
• The control unit must decide whether to
perform an indirect cycle or an execute cycle next.
•For this , the control unit examines the IR to see if
an indirect memory reference is made.
• For the execute cycle , the control unit begins
by examining the opcode and decide which
sequence of micro operations to perform for
execute cycle.
•Consider a simple processor with a single
accumulator.
•The data paths and control signals are shown in
the fig. The control unit receives inputs from
the IR, clock and flags.
•With each clock cycle, the control unit reads all
the inputs and produces a set of control signals.
• The control unit controls the internal flow of
data. In the fetch cycle, the contents of the
MBR are transferred to the IR.
•
•For each path to the controlled, there is a gate . A
control signal from the control unit temporarily
opens the gate to let data pass.
•The various micro operations and control signals
are listed in the table
• In a hardware control unit, the control unit
produces out put control signals as a function
of its input signals. IT is shown in the fig. 1.26.
Here , instruction register, clock and flags are
the inputs.