Power Consumption

 Static and Dynamic Power

Power Consumption
 Power Analysis- cost and performance of
a logic gate
 the cost of heat which must be dissipated
out of the chip.
 Static, complementary CMOS gates are
remarkably efficient in their use of power
to perform computation
Power Consumption
 Power is consumed by gates in two
different ways:
 dynamic power : when gates drive
their outputs to new values
 static power: even when the gate is
quiet and its output is not changing.
 We can summarize this observation in a
formula:
P = P D + PS
Power Consumption
 Dynamic power: Gates are charging and
discharging their load capacitances.
 Static power : non-idealities in the
transistors cause them to conduct
current even when off.
 static power consumption exceeds
dynamic power consumption.
 Static power consumption is best
analyzed using Spice simulation.
Power Consumption

 The circuit has almost no steady-state

power consumption
 After the output capacitance has been
fully charged or discharged, only one of
the pullup and pulldown transistors is on.
Power and transistor size
 Power consumed - independent of the sizes
/resistances of pullup and pulldown transistors
 It depends only on the size of the capacitive load
at the output and the rate at which the inverter’s
output switches.
To understand why,
 consider the energy required to drive the
inverter’s output high calculated two ways:
1. by the current through the load capacitor CL
2. by the current through the pullup transistor,
represented by its effective resistance Rp.
Dynamic power calculation

 the energy required to charge the capacitor

Note
Dynamic power calculation
 The current through and voltage across the
pullup are:

 The energy required to charge the capacitor

 depends on the size of the load capacitance but

not the resistance of the pullup transistor
Energy per cycle
 The energy consumed in discharging the
capacitor
 discharging energy consumption= charging
power consumption
 single cycle requires the capacitor to both
charge and discharge
 The total energy consumption
CL (VDD  VSS ) 2
Power consumption
 Power = Energy per unit time
 The total power consumption is
f C L (VDD  VSS ) 2

 Dynamic power consumption in CMOS

circuits depends on the frequency at
which they operate
 Depends on clock frequency
Power consumption
 depends on the sizes of the transistors in
the circuit – only in that the transistors
largely determine CL
 current through the transistors doesn’t
determine power consumption
 The transistor current does determine the
maximum speed at which the circuit can
run, which indirectly determines power
consumption.
Dynamic power calculations
 depend on the current flowing through
capacitors;
 the resistors determine only maximum
operating speed, not power consumption
 SC gates can operate over a wide range of
voltages,
 trade delay for power consumption
 As we reduce power supply voltage, power
consumption goes down faster than does
delay
Speed Vs Power
 let’s consider changing the power supply
voltage from its original value V to a new V’
 the ratio of power consumptions P’/P is
proportional to V’2/V2
 ratio of rise times tr’/tr is proportional
to V/V’
The Speed-Power Product
 also known as the power-delay product
 an important measure of the quality of a
logic circuit family.
 Since delay can in general be reduced by
increasing power consumption
 speed-power product SP is
 independent of the operating frequency of the
circuit
 a quadratic function of the power supply
voltage
 A method for power consumption reduction -
voltage scaling:
 reduce power consumption by reducing the
power supply voltage and adding parallel logic
gates to make up for the lower performance.
Layout and Parasitics
 how to design the layout of a gate to
maximize performance and minimize area
 Consider the effects of adding resistance
and capacitance to each of the labeled
points of this layout
Layout and Parasitics

VDD

PMOS

Input Output

NMOS

Vss
Layout and Parasitics
•a
 Adding capacitance to point a adds
capacitance to the power supply wiring.
Capacitance on this node doesn’t slow
down the gate’s output.
 Resistance at a can cause problems.
Resistance in the VSS line can be modeled
by this equivalent circuit
Layout and Parasitics

 The power supply resistance is in series

with the pulldown
 The resistance slows down the gate
Layout and Parasitics
 But since both the transistor gates of the
pullup and pulldown are connected to the
same electrical node, we can be sure that
only one of them will be on in steady state.
 However, the dynamic logic circuits may not
work if the series power supply resistance is
too high, because the voltages supplied by
the gate with resistance may not properly
turn on succeeding transistor gates.
Layout and Parasitics
 The layout around point a should be
designed to minimize resistance.
 A small length of diffusion is required to
connect the transistors to the power lines,
 But power lines should be kept in metal as
long as possible.
 If the diffusion wire is wider than a via (to
connect to a wide transistor), several parallel
vias should be used to connect the metal
and diffusion lines.
Layout and Parasitics
 b
 Capacitance at b adds to the load of the gate
driving this node.
 However, the transistor capacitances are
much larger than the capacitance added by
the short wire feeding the transistor gates.
 Resistance at b actually helps isolate the
previous gate from the load capacitance.
 Gate layouts should avoid using large
sections of diffusion wire or a single via to
connect high-current wires.
Layout and Parasitics
 C
 Capacitance and resistance at c are
companions to parasitics at b
- form part of the load that this gate must
drive, along with the parasitics of the b
zone of the next gate.
 But if we consider a more accurate model
of the parasitics, we will see that not all
positions for parasitic R and C are equally
bad.
Layout and Parasitics

 consider the inverter’s load as two RC

sections
 One RC section is contributed by the wires
at point c, near the output
 the RC section comes from the long wire
connecting this gate to the next one.
 A large value for Rx, which is supplied by the
parasitics at point c, steals current from RLCL
 As Rx grows relative to RL, the voltage drop
across Rx increases, increasing the current
through Rx while decreasing the current
through RL
 As a result, more of the current supplied by the
gate will go through Cx
 Only after it is fully charged will CL get the full
current supplied by the gate.
Layout and Parasitics
 CL is almost certainly significantly larger than
Cx because it includes both the transistor
capacitances and the long-wire capacitance
 charge CL to switch the next gate as
quickly as possible.
 But charging/discharging of CL has been
delayed while Rx diverts current into Cx
Layout and Parasitics
 resistance close to the gate output is worse than
resistance farther away
 Close-in resistance must charge more capacitors,
slowing down the signal swing at the far end of
the wire.
 Therefore, the layout around c should be
designed to minimize resistance by:
 using as little diffusion as possible
- diffusion should be connected to metal (or
perhaps poly) as close to the channel as possible;
 using parallel vias at the diffusion/metal
interface to minimize resistance.
Switch Logic
 We can use switches to implement
Boolean functions.
 However, there is more than one way
to build a switch from transistors
 Parallel n-type and p-type transistors.
 it transmits logic 0 and 1 from drain to
source equally well
n-type switch
 A solitary n-type transistor
 requires only one transistor and one gate
signal
 it transmits a logic 0 well
 but when VDD is applied to the drain, the
voltage at the source is VDD - Vin.
 When switch logic drives gate logic, n-type
switches can cause electrical problems
n-type switch
 An n-type switch driving a
complementary gate causes the
complementary gate to run slower when
the switch input is :
 since the n-type pulldown current is
weaker when a lower gate voltage is
applied, the complementary gate’s
pulldown will not suck current off the
output capacitance as fast
n-type switch
 drives a pseudo-nMOS gate, disaster may
occur.
 A pseudo-nMOS gate’s ratioed transistors
depend on logic 0 and  inputs to occur
within a prescribed voltage range.
 If the n-type switch doesn’t turn on the
pseudo-nMOS pulldown strongly enough, the
pulldown may not divert enough current
from the pullup to force the output to a
logic 0.
switch logic delay
Alternative Gate Circuits
 Pseudo-nMOS Logic
 DCVS Logic
 Domino Logic