Universal Verification

Methodology
A rough approach

Ha Minh Tran Hanh

FJP.ETG-D
Prerequisites
• Oriented-Object-Programming
• Design pattern definitions
• System Verilog
Agenda
• Overview
• UVM Testbench architecture
• UVM Classes
• UVM Phases
• Factory in short
• UVM factory
• UVM config db
• Developing flow with sample project
Overview (1/2) - an “academic” approach
• Hybrid of technologies:
• Mentor’s AVM, Resources, TLM2, Phasing
• Mentor & Cadence’s OVM
• Verisity’s eRM
• Synopsys’s VMM-RAL
• Basics:
• Layered, object-oriented, modular reusable verification environment
• Allows separation of concerns among the various team members:
• Test writers: think at the transaction level, focusing on the functionality that must be
verified
• Testbench architects: focuses on how the test interacts with the Design Under Test (DUT)
Overview (2/2) - a “lazy” approach
• A framework:
• System Verilog/SystemC
• A set of pre-defined base classes, utilities and macros to serve:
• Adopting TLM easier
• Increasing readability and reusability
• Compacting code
Agenda
• Overview
• UVM Testbench architecture
• UVM Classes
• UVM Phases
• Factory in short
• UVM factory
• UVM config db
• Developing flow with sample project
UVM testbench architecture (1/3)
Simple single environment testbench architecture
UVM testbench architecture (2/3)

Simple clustering environment testbench

architecture
UVM testbench architecture (3/3)
• Test-vector/Testcase creating (suggestion):
1. Define different sets of configurations or different sequences
2. Invoke configurations/sequences to test class:
• Extend base test to invoke desired configuration/sequence
• Third-party libraries to invoke desired configuration/sequence
• Others …
Agenda
• Overview
• UVM Testbench architecture
• UVM Classes
• UVM Phases
• Factory in short
• UVM factory
• UVM config db
• Developing flow with sample project
UVM Classes
UVM Phases
• Build phases: all functions – execute in
zero time

• Run phases:
• Phases that run in parallel with run
phase are time consuming – tasks
are used
• Pre_reset to post_shutdown phases
should be called from test and env to
start sequences. Drivers, monitors
and other components should not
implement these phases.

• Cleanup phases: extract, check and report

phases are usually used by analysis
components.
Agenda
• Overview
• UVM Testbench architecture
• UVM Classes
• UVM Phases
• Factory in short
• UVM factory
• UVM config db
• Developing flow with sample project
Factory in short (1/4)

We will stuck with

ApbTrans unless
we declare a new
ApbDriver class
Factory in short (2/4)
Factory in short (3/4)
Factory in short (4/4)

uvm_factory is the factory

mechanism implemented in
UVM which also has macros to
support overriding by names,
types and at command line
UVM Factory (1/3)
• Manufacture (create) UVM objects and components
• Singleton object (uvm_factory)
• Basic operations:
• Registering objects and components types
• Designing components to use the factory to create objects or components
• Configuring the factory with type and instance overrides, both within and
outside components
UVM Factory (2/3) – Operation
UVM Factory (3/3) – References
• https://verificationacademy.com/verification-methodology-
reference/uvm/docs_1.1a/html/files/base/uvm_factory-svh.html
• https://verificationacademy.com/verification-methodology-
reference/uvm/docs_1.1c/html/files/macros/uvm_object_defines-
svh.html
UVM Config DB (uvm_config_db::*)
• A common database to set/get configurations for uvm_component
instances.
• All functions are static Test
Set()
Env

Get()
Instance Field name Value
sequenc
Test.Env EnvInt 8 monitor
er
Test.Env.Agent AgentString “Trial”
Get()
uvm_config_db driver Agent
Agenda
• Overview
• UVM Testbench architecture
• UVM Classes
• UVM Phases
• Factory in short
• UVM factory
• UVM config db
• Developing flow with sample project
Developing flow with sample project
1. Specification
2. Modeling Data Items for
Generation
3. Transaction-Level
Components
4. Creating the Driver
5. Creating the Sequencer
6. Creating the Monitor
7. Instantiating Components
8. Creating the Agent
9. Creating the Environment
10. Enabling Scenario Creation
11. Managing End of Test

Source code: alu.sv

Developing flow with sample project
uvm_sequence_item
1. Specification
2. Modeling Data Items for
Generation
3. Transaction-Level User-defined classes
Components
4. Creating the Driver
5. Creating the Sequencer
6. Creating the Monitor
7. Instantiating Components
8. Creating the Agent Source code: alu_seq_item.sv
9. Creating the Environment
10. Enabling Scenario Creation
11. Managing End of Test
Developing flow with sample project
1. Specification
2. Modeling Data Items for
Generation
3. Transaction-Level
Components
4. Creating the Driver
5. Creating the Sequencer
6. Creating the Monitor
7. Instantiating Components
8. Creating the Agent
9. Creating the Environment
10. Enabling Scenario Creation
11. Managing End of Test
Developing flow with sample project
1. Specification
2. Modeling Data Items for
Generation uvm_driver
3. Transaction-Level
Components
4. Creating the Driver
User-defined classes
5. Creating the Sequencer
6. Creating the Monitor
7. Instantiating Components
8. Creating the Agent
9. Creating the Environment
10. Enabling Scenario Creation
11. Managing End of Test
Source code: alu_driver.sv
Developing flow with sample project
1. Specification
2. Modeling Data Items for uvm_sequencer
Generation
3. Transaction-Level
Components
4. Creating the Driver User-defined classes
5. Creating the Sequencer
6. Creating the Monitor
7. Instantiating Components
8. Creating the Agent
9. Creating the Environment
10. Enabling Scenario Creation
11. Managing End of Test
Source code: alu_seqr.sv
Developing flow with sample project
1. Specification
2. Modeling Data Items for uvm_monitor
Generation
3. Transaction-Level
Components
4. Creating the Driver User-defined classes
5. Creating the Sequencer
6. Creating the Monitor
7. Instantiating Components
8. Creating the Agent
9. Creating the Environment
10. Enabling Scenario Creation
11. Managing End of Test
Source code: alu_monitor.sv
Developing flow with sample project
1. Specification
2. Modeling Data Items for
Generation
3. Transaction-Level
Components uvm_agent
4. Creating the Driver
5. Creating the Sequencer
6. Creating the Monitor User-defined classes
7. Instantiating Components
8. Creating the Agent
9. Creating the Environment
10. Enabling Scenario Creation
11. Managing End of Test Source code: alu_agent.sv
Developing flow with sample project
1. Specification
2. Modeling Data Items for uvm_env
Generation
3. Transaction-Level
Components
4. Creating the Driver User-defined classes
5. Creating the Sequencer
6. Creating the Monitor
7. Instantiating Components
8. Creating the Agent
9. Creating the Environment
10. Enabling Scenario Creation
11. Managing End of Test
Source code: alu_env.sv
Developing flow with sample project
1. Specification
2. Modeling Data Items for
Generation
3. Transaction-Level
Components
4. Creating the Driver
1. Component developers: facilitate the test writing
5. Creating the Sequencer
• Place knobs in data item class to simplify declarative
6. Creating the Monitor test control
7. Instantiating Components • Create library of interesting reusable sequences
8. Creating the Agent 2. Environment users: control the environment-generated
9. Creating the Environment patterns to configure its sequencers
• Define new sequences that:
10. Enabling Scenario Creation • Generate new transactions
11. Managing End of Test • Invoke existing sequences
• Override default knobs on data items to modify driver
and overall environment behavior
• ”Enable” any new behavior/sequences
Developing flow with sample project
1. Specification uvm_sequence
2. Modeling Data Items for
Generation • Set desired sequencer pointer
3. Transaction-Level User-defined if needed
Components class • Override “body” task with
4. Creating the Driver scenario that sequence need
5. Creating the Sequencer to execute. Can execute data
items and other sequences
6. Creating the Monitor
7. Instantiating Components
8. Creating the Agent • Create sequences
9. Creating the Environment • Start sequence
10. Enabling Scenario Creation • Override sequences and sequence items
11. Managing End of Test
Source code: alu_seq.sv
Developing flow with sample project
1. Specification • Manual starting: call “start” task of
2. Modeling Data Items for uvm_test sequence instance at any time
Generation
3. Transaction-Level • Automatically phase-based
Components starting: sequencer will check for the
User-defined base
4. Creating the Driver existence of a resource corresponding to
test class
5. Creating the Sequencer that phase to determine if there is a
sequence to start automatically
6. Creating the Monitor
7. Instantiating Components • Create sequences
• Start sequence Instantiating
8. Creating the Agent environment,
• Override sequences and sequence items
9. Creating the Environment sequences, factory
10. Enabling Scenario Creation controls and
11. Managing End of Test configurations as well
as starting sequences
Source code: alu_test.sv
Developing flow with sample project
1. Specification
2. Modeling Data Items for User base test class
Generation
3. Transaction-Level
Components • Derive classes
4. Creating the Driver Testvector’s test class • Override by factory in testvector’s test class
5. Creating the Sequencer • Reconfigure components in testvector’s test class
6. Creating the Monitor
7. Instantiating Components
8. Creating the Agent • Create sequences
9. Creating the Environment • Start sequence
10. Enabling Scenario Creation • Override sequences and sequence items
11. Managing End of Test
Source code: alu_test0.sv
Developing flow with sample project
1. Specification Test selection:
• In source code:
2. Modeling Data Items for
Generation • Uvm_pkg::run_test (string test_name);
• In command line:
3. Transaction-Level • +UVM_TESTNAME=<test_name>
Components
4. Creating the Driver
5. Creating the Sequencer
6. Creating the Monitor
7. Instantiating Components
8. Creating the Agent
9. Creating the Environment
10. Enabling Scenario Creation
11. Managing End of Test
Source code: alu_top.sv
Developing flow with sample project
1. Specification
• Need a mechanism to guarantee phased execution.
2. Modeling Data Items for
Generation • UVM have built-in phase objection for each phase:
• raise_objection () – start activities that need be done in this phase
3. Transaction-Level
Components • drop_objection () – activities are done, can move to next phase
4. Creating the Driver
5. Creating the Sequencer
6. Creating the Monitor
7. Instantiating Components
8. Creating the Agent
9. Creating the Environment
10. Enabling Scenario Creation
11. Managing End of Test
Source code: alu_test_manual.sv
Scoreboard for sample DUT
• Collect data item to check correctness
• Report correctness

Source code: alu_scoreboard.sv

Scoreboard
Scoreboard
Calc Cmp

Req Ans
FF FF

monitor
Demo
• https://www.edaplayground.com/x/3hLb

• Run different tests:

• In Command Line
• In top module
Extra Topics
• Implementing Checks and Coverage
• UVM Report
• Register package
• Virtual sequencer/sequence
• DPI
• UVM Command Line Interface (CLI)
•…
References
• Universal Verification Methodology – UVM Cookbook, Mentor
• Universal Verification Methodology – UVM User Guide, Accellera
Systems Initiative
• UVM Class Reference
• https://verificationacademy.com/cookbook
• https://github.com/jayantom/sknobs
Thank you!
Appendix 1
• How simulation start

www.chipverify.com