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William Stallings Computer Organization and Architecture 8 Edition Reduced Instruction Set Computers

This chapter discusses the evolution of computer architecture from CISC to RISC designs. It outlines the key characteristics of RISC, including the use of more general purpose registers, a limited and simple instruction set, and an emphasis on optimizing the instruction pipeline. The chapter also analyzes the dynamic execution characteristics of programs to understand which operations and operands are most common, finding that register-based access to local variables should be optimized. While CISC aimed to ease compiler development and support complex languages, RISC designs focused on simplifying hardware through register-register operations and a streamlined instruction format suited for pipelining.

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296 views23 pages

William Stallings Computer Organization and Architecture 8 Edition Reduced Instruction Set Computers

This chapter discusses the evolution of computer architecture from CISC to RISC designs. It outlines the key characteristics of RISC, including the use of more general purpose registers, a limited and simple instruction set, and an emphasis on optimizing the instruction pipeline. The chapter also analyzes the dynamic execution characteristics of programs to understand which operations and operands are most common, finding that register-based access to local variables should be optimized. While CISC aimed to ease compiler development and support complex languages, RISC designs focused on simplifying hardware through register-register operations and a streamlined instruction format suited for pipelining.

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William Stallings

Computer Organization
and Architecture
8th Edition

Chapter 13
Reduced Instruction Set Computers
Major Advances in Computers(1)
• The family concept
—IBM System/360 1964
—DEC PDP-8
—Separates architecture from implementation
• Microprogrammed control unit
—Idea by Wilkes 1951
—Produced by IBM S/360 1964
• Cache memory
—IBM S/360 model 85 1969
Major Advances in Computers(2)
• Solid State RAM
—(See memory notes)
• Microprocessors
—Intel 4004 1971
• Pipelining
—Introduces parallelism into fetch execute cycle
• Multiple processors
The Next Step - RISC
• Reduced Instruction Set Computer

• Key features
—Large number of general purpose registers
—or use of compiler technology to optimize
register use
—Limited and simple instruction set
—Emphasis on optimising the instruction
pipeline
Comparison of processors
Driving force for CISC
• Software costs far exceed hardware costs
• Increasingly complex high level languages
• Semantic gap
• Leads to:
—Large instruction sets
—More addressing modes
—Hardware implementations of HLL statements
– e.g. CASE (switch) on VAX
Intention of CISC
• Ease compiler writing
• Improve execution efficiency
—Complex operations in microcode
• Support more complex HLLs
Execution Characteristics
• Operations performed
• Operands used
• Execution sequencing
• Studies have been done based on
programs written in HLLs
• Dynamic studies are measured during the
execution of the program
Operations
• Assignments
—Movement of data
• Conditional statements (IF, LOOP)
—Sequence control
• Procedure call-return is very time
consuming
• Some HLL instruction lead to many
machine code operations
Weighted Relative Dynamic Frequency of HLL
Operations [PATT82a] (CISC)

Machine-Instruction Memory-Reference
Dynamic Occurrence Weighted Weighted
(Relative frequency of
(Surrogate measures of actual (Surrogate measures of actual
Occurrence)
time spent executing) time spent referencing memory)

Pascal C Pascal C Pascal C

ASSIGN 45% 38% 13% 13% 14% 15%

LOOP 5% 3% 42% 32% 33% 26%

CALL 15% 12% 31% 33% 44% 45%

IF 29% 43% 11% 21% 7% 13%

GOTO — 3% — — — —

OTHER 6% 1% 3% 1% 2% 1%
Operands (Dynamic Percentage of
Operand References)
• Mainly local scalar variables
• Optimisation should concentrate on
accessing local variables

Pascal C Average

Integer Constant 16% 23% 20%

Scalar Variable 58% 53% 55%


(80% Local Variables)

Array/Structure 26% 24% 25%


(+ a reference to an index
or a pointer @ item)
Procedure Calls
• Very time consuming
• Depends on number of parameters passed
• Depends on level of nesting
• Most programs do not do a lot of calls
followed by lots of returns
• Most variables are local
• (c.f. locality of reference)
Implications
• Best support is given by optimising most
used and most time consuming features
• Large number of registers
—Operand referencing
• Careful design of pipelines
—Branch prediction etc.
• Simplified (reduced) instruction set
Registers for Local Variables
• Store local scalar variables in registers
• Reduces memory access
• Every procedure (function) call changes
locality
• Parameters must be passed
• Results must be returned
• Variables from calling programs must be
restored
Registers v Cache
Large Register File Cache

All local scalars Recently-used local scalars

Individual variables Blocks of memory

Compiler-assigned global variables Recently-used global variables

Save/Restore based on procedure nesting depth Save/Restore based on cache replacement


algorithm

Register addressing Memory addressing


Referencing a Scalar -
Window Based Register File
Why CISC (1)?
• Compiler simplification?
—Disputed…
—Complex machine instructions harder to
exploit
—Optimization more difficult
• Smaller programs?
—Program takes up less memory but…
—Memory is now cheap
—May not occupy less bits, just look shorter in
symbolic form
– More instructions require longer op-codes
– Register references require fewer bits
Why CISC (2)?
• Faster programs?
—Bias towards use of simpler instructions
—More complex control unit
—Microprogram control store larger
—thus simple instructions take longer to execute

• It is far from clear that CISC is the


appropriate solution
RISC Characteristics
• One instruction per cycle
• Register to register operations
• Few, simple addressing modes
• Few, simple instruction formats
• Hardwired design (no microcode)
• Fixed instruction format
• More compile time/effort
RISC v CISC
• Not clear cut
• Many designs borrow from both
philosophies
• e.g. PowerPC and Pentium II
RISC Pipelining
• Most instructions are register to register
• Two phases of execution
—I: Instruction fetch
—E: Execute
– ALU operation with register input and output
• For load and store
—I: Instruction fetch
—E: Execute
– Calculate memory address
—D: Memory
– Register to memory or memory to register operation
Controversy
• Quantitative
—compare program sizes and execution speeds
• Qualitative
—examine issues of high level language support
and use of VLSI real estate
• Problems
—No pair of RISC and CISC that are directly
comparable
—No definitive set of test programs
—Difficult to separate hardware effects from
complier effects
—Most commercial devices are a mixture
Required Reading
• Stallings chapter 13
• Manufacturer web sites

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