Design and performance analysis of 2:1 multiplexer

using multiple logic families at 180 nm technology

INTRODUCTION
o MUX is a data selector that selects one of several analog or digital input signals and forwards the
selected input into a single output line.
o A multiplexer of 2n inputs has n select lines, which are used to select which input line to send to the
output.
o It has two input lines D0 and D1, one select line S and one output line Y.
o The truth table of 2:1 MUX is given below:
 • Complementary metal oxide semi-conductor devices are chips in which
both P-channel and N-channel enhancement MOSFETs are connected
in push-pull arrangement.[1]
• The basic connections of CMOS is shown below:

WHAT IS
CMOS?
 In this circuit, two MOSFETs (P-channel MOSFET and N-channel-MOSFET) are
connected in series
 The source of P-channel device is connected to a positive voltage supply + VDD and the
source of N-channel device is connected to the ground.
 Gates of both the devices are connected as a common input and drain terminals of both
the devices are connected together as a common output.[1]

 Advantage of CMOS:
The power dissipation level is very small(50nW)[1]
There are two types of CMOS logic families:-
 Static CMOS circuits.
 Dynamic CMOS circuits.

Static CMOS Circuit:

 These are designed with complementary nMOS Pull-Down Network (PDN) and pMOS Pull-Up
Networks (PUN).
 They have simple design; hence they are insensitive to variations, good noise margins, fast operating
speed and low power.
 The circuit for Static CMOS is shown below:
Dynamic CMOS circuit:
 This uses simple sequential circuits along with memory functions.
 It is dependent on temporary storage of charges in parasitic node capacitance.
 Dynamic circuits require less silicon area and have superior performance over conventional Static Logic
circuits.
 It also uses a sequence of Precharge and Evaluation Phases governed by the clock to recognize complex
logic functions.

 Precharge Phase
When clock signal (Φ) = 0, the output node Out is precharged to VDD by the PMOS transistor Mp and the
evaluate NMOS transistor remains off, so that the pull-down path is disabled.
 Evaluation Phase
In the PDN when clock signal (Φ) = 1, the pre-charge transistor Mp is OFF, and the evaluation transistor Me
is turned ON.
WHAT DO PULL-UP NETWORK AND PULL-DOWN
NETWORK MEAN IN CMOS?
• Consider a CMOS inverter
• When input is low, as a result the upper PMOS is ON but
lower NMOS is OFF. Hence the output voltage is same as
source voltage. The PMOS here is called a "pull-up" transistor
i.e., the output is pulled up to source voltage.[2]
• When input is high, as a result the upper PMOS is OFF and
lower NMOS is ON. Hence the output voltage is shorted to
ground. The NMOS here is called a "pull-down" transistor.[2]
DESIGN OF EFFICIENT MUX
In this work, the 2:1 multiplexer has been designed using various logic families such as Static CMOS logic,
Pseudo NMOS logic, Domino logic and Dual Rail Domino logic

Static CMOS Logic

 This is constructed with the help of a PUN and a PDN.

 The function of the PDN is to provide a connection between the output and VDD when the output of the logic
gate is supposed to be 1.
 Similarly, the PDN connects the output to ground when the output is expected to be 0.
 The PUN and PDN networks are constructed in a mutually exclusive manner such that either PDN or PUN is
conducting in steady state.

 Advantage:
They have zero quiescent power dissipation, where for any applied input state either the PUN or the PDN
remains off.
 Disadvantage:
The problem with this type of implementation is that more area is required in implementing logics. This has an
impact on the capacitance and thus the speed of the gate [1].
The circuit diagram for Static CMOS Logic:
 Pseudo NMOS Logic

 In this circuit , the PDN is like that of an ordinary static gate, but the PUN has been replaced with a single
pMOS transistor that is grounded so it is always ON.
 The pMOS transistor widths are selected to be about 1/4 the strength (i.e. 1/2 the effective width) of the
nMOS PDN as a compromise between noise margin and speed; this best size is process-dependent.

 Advantage:
The area required to implement logics have been reduced which in turn increases the speed.

 Disadvantages:
o Slow rising transitions.
o Contention on the falling transitions.
o Static power dissipation.
The circuit diagram for Pseudo NMOS Logic:
Dynamic Logics
This circumvent the drawbacks of Pseudo NMOS by using a clocked PUN rather than a pMOS that is
always ON. But the main issue in Dynamic logic compared to Static CMOS logic, is the monotonicity
requirement. During an evaluation phase of dynamic gate the inputs must be monotonically raising for the
dynamic gate to compute the correct function.
To overcome this monotonicity problem Domino logic was used.

Domino Logic:

 This was introduced to overcome the monotonicity problem faced the Dynamic logic circuits. The monotonicity
problem can be solved by placing a static CMOS inverter between dynamic gates.
 This converts the monotonically falling output into a monotonically rising signal suitable for the next gate.

 Advantages:
o It runs 1.5-2 times faster than the static logic circuits.
o It permits high speed operation.
o It enables implementation of complex functions.
o
 Disadvantage:
o Cannot compute non-inverting logic functions.
The circuit diagram for Domino Logic:
Dual-Rail Domino
 Advantage:
It can compute all inverting and non-inverting logic function which is a drawback in
Domino Logic as it can implement only inverting logic.
 Disadvantage:
It requires more area, wiring, and power.

The circuit diagram for Dual-Rail Domino logic is given below:

 TRANSISTOR SIZING FOR 2:1 MUX

LOGIC FAMILIES NUMBER OF TRANSISTORS AREA WIDTH(m)

Static CMOS 12 4.32p

Pseudo NMOS 7 2.52p

Domino 7 2.52p

Dual-rail Domino 14 5.04p

SIMULATION RESULTS AND DISCUSSION
 PERFORMANCE METRICS

 Average Power
It is the power consumed by the circuit so as to give the output.
Unit: watt (W).
AVERAGE POWER=STATIC POWER + DYNAMIC POWER.

 Propagation Delay
It is the time required for a digital signal to travel from the input of a logic gate to the output switch. Unit:
seconds (s)
DELAY=(T(rf)+T(fr))/2
Where T(rf) is the rise time and t(fr) is the fall time
 Area
It is the product of length , width and number of transistors used to implement a circuit.
Unit: square meter (m*2)
AREA=L*W*(number of transistors)
Where L is the length and W is the width.

 Power Delay Product(PDP)

It is the product of the average power and the delay of the circuit.
Unit: joules (J)
PDP=Average power *Delay
 Static CMOS Logic

 The static CMOS based 2:1 MUX has been designed using a PUN consisting of 4 pMOS and a PDN
consisting of 4 nMOS.
 The PUN is constructed using two parallel pMOS circuits connected in series.
 The PDN is constructed using two series nMOS circuits connected in parallel.
 The output of the Static CMOS logic is connected to an inverter to obtain the correct output.
 VDD is connected to the pull-up circuit to provide power supply and the ground is connected to the pull-
down circuit. The inputs to the circuit is provided with the help of Vpulse which is set according the truth
table of 2:1 MUX.

 Pseudo NMOS Logic

 The design of 2:1 MUX using Pseudo NMOS logic is similar to Static CMOS logic except that the entire
PUN is replaced by a single pMOS transistor and grounded permanently to reduce the transistor count.
 The output of the Pseudo NMOS is connected to an inverter to obtain the correct.
 The power supply is provided through VDD connected to the pullup circuit and the circuit inputs are given
with the help of Vpulse as per the truth table of 2:1 MUX.
 Domino Logic

 The construction of 2:1 MUX using Domino logic is just as same as that of the Pseudo NMOS logic.
 The only difference is that the PUN that has been grounded is supplied with a high clock skew which is
provided by the Vpulse.
 The output is connected to a CMOS inverter to overcome monotonicity problem and to improve the circuit
performance.
 VDD is used to provide the power supply to the circuit connected to the pull-up circuit and the other inputs
provided through Vpulse.

 Dual-Rail Domino Logic

 The 2:1 MUX using Dual Rail Domino logic is designed by connecting complimentary domino logic with the
actual domino logic.
 All the other working principles remain same as that of the Domino logic.
 Average
Number of Power Delay Area(m*2)
Name of the logic power(W) Delay(s)
transistors Product(PDP)

Static CMOS 12 55.33µ 4.573n 0.253 4.32p

Pseudo NMOS
7 411.5µ 4.561n 1.87 2.52p

Domino Logic 7 126.2µ 4.5505n 0.574 2.52p

Dual-Rail Domino 14 248.8µ 4.5515n 1.13 5.04p

 CONCLUSION

• Thus a 2:1 MUX is implemented using various CMOS logic families and it’s performance metrics are
analyzed.
• It is seen that, 2:1 MUX designed using domino logic is the most efficient design because the reduction in
average power consumption is 20.06% and in PDP is 20.1% compared to all the other logic families
and the propagation delay is also lesser.

• But there are trade-off between Domino logic and Static CMOS logic which can be neglected on
considering the overall performance.
 REFERENCES

1) CIRCUITS TODAY.
2) Electronics-Tutorial.