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    Static CMOS and Dynamic Circuits

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    Abhijna Maiya
    This document discusses static CMOS circuits. It describes combinational and sequential circuits, static and dynamic circuits, and static CMOS design principles. Static CMOS circuits have no static power dissipation and provide robustness due to low sensitivity to noise. They implement logic gates using complementary CMOS, with mutually exclusive pull-up and pull-down networks. While static CMOS uses more transistors than alternative designs, it has good performance and low power consumption. The document also notes some drawbacks of static CMOS and discusses ratioed logic and pseudo-NMOS as alternative static logic styles with fewer transistors. Finally, it introduces dynamic CMOS logic circuits and some associated signal integrity issues to consider in dynamic design like charge leakage, charge sharing

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    Static CMOS and Dynamic Circuits

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    Abhijna Maiya
    283 views19 pages
    This document discusses static CMOS circuits. It describes combinational and sequential circuits, static and dynamic circuits, and static CMOS design principles. Static CMOS circuits have no static power dissipation and provide robustness due to low sensitivity to noise. They implement logic gates using complementary CMOS, with mutually exclusive pull-up and pull-down networks. While static CMOS uses more transistors than alternative designs, it has good performance and low power consumption. The document also notes some drawbacks of static CMOS and discusses ratioed logic and pseudo-NMOS as alternative static logic styles with fewer transistors. Finally, it introduces dynamic CMOS logic circuits and some associated signal integrity issues to consider in dynamic design like charge leakage, charge sharing

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    This document discusses static CMOS circuits. It describes combinational and sequential circuits, static and dynamic circuits, and static CMOS design principles. Static CMOS circuits have no static power dissipation and provide robustness due to low sensitivity to noise. They implement logic gates using complementary CMOS, with mutually exclusive pull-up and pull-down networks. While static CMOS uses more transistors than alternative designs, it has good performance and low power consumption. The document also notes some drawbacks of static CMOS and discusses ratioed logic and pseudo-NMOS as alternative static logic styles with fewer transistors. Finally, it introduces dynamic CMOS logic circuits and some associated signal integrity issues to consider in dynamic design like charge leakage, charge sharing

    Copyright:

    © All Rights Reserved
    Download as PPTX, PDF, TXT or read online from Scribd
    Download as pptx, pdf, or txt
    283 views19 pages

    Static CMOS and Dynamic Circuits

    Uploaded by

    Abhijna Maiya
    This document discusses static CMOS circuits. It describes combinational and sequential circuits, static and dynamic circuits, and static CMOS design principles. Static CMOS circuits have no static power dissipation and provide robustness due to low sensitivity to noise. They implement logic gates using complementary CMOS, with mutually exclusive pull-up and pull-down networks. While static CMOS uses more transistors than alternative designs, it has good performance and low power consumption. The document also notes some drawbacks of static CMOS and discusses ratioed logic and pseudo-NMOS as alternative static logic styles with fewer transistors. Finally, it introduces dynamic CMOS logic circuits and some associated signal integrity issues to consider in dynamic design like charge leakage, charge sharing

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    Static CMOS Circuits

    Combinational and Sequential circuits


    • Combinational: Circuits that have the property that at any point in time,
    the output of the circuit is related to its current input signals by some
    Boolean expression. No intentional connection between outputs and
    inputs is present.
    • Sequential: The output is not only a function of the current input data,
    but also of previous values of the input signals.
    – This is accomplished by connecting one or more outputs intentionally back to some
    inputs.
    – Consequently, the circuit “remembers” past events and has a sense of history.
    • Thus, a sequential circuit includes a combinational logic portion and a
    module that holds the state.
    Static and Dynamic Circuits

    Static circuits:
    • Circuits in which at every point in time (except during the
    switching transients), each gate output is connected to
    either VDD or Vss via a low-resistance path.
    • Also, the outputs of the gates assume at all times the value
    of the Boolean function implemented by the circuit.
    Dynamic circuits:
    • Circuits which rely on temporary storage of signal values on
    the capacitance of high-impedance circuit nodes.
    • This approach has the advantage that the resulting gate is
    simpler and faster.
    Static CMOS Design
    • The static CMOS style is an extension of the static
    CMOS inverter to multiple inputs.
    • The primary advantages of the CMOS structure are:
    – robustness (i.e, low sensitivity to noise),
    – good performance, and
    – low power consumption with no static power dissipation
    – Implementation of logic gates is simple.
    • The complementary CMOS circuit style falls under a
    broad class of logic circuits called static circuits.
    Complementary CMOS

    Note: The PUN and PDN networks are constructed in a mutually exclusive fashion such
    that one and only one of the networks is conducting in steady state.
    Static Properties of CMOS gates
    • Rail to rail swing with VOH = VDD and VOL =
    GND.
    • No static power dissipation, since the circuits
    are designed such that the pull-down and pull-
    up networks are mutually exclusive
    • Noise margins and the propagation delay
    depends on the data input patterns applied to
    gate.
    Drawbacks of CMOS

    • The number of transistors required to implement an ‘N’ fan-in


    gate is 2N. This can result in significant implementation area.
    • The propagation delay of a complementary CMOS gate
    deteriorates rapidly as a function of the fan-in.
    • Large number of transistors (2N) increases the overall
    capacitance of the gate.
    • Series connections of transistors either in PUN or PDN causes
    an additional slowdown.
    • The fan-out has a large impact on the delay of complementary
    CMOS logic as well. Each input to a CMOS gate connects to
    both an NMOS and a PMOS device, and presents a load to the
    driving gate equal to the sum of the gate capacitances.
    Ratioed Logic
    • It is an attempt to reduce
    the number of transistors
    • In ratioed logic, the entire
    PUN is replaced with a
    single unconditional load
    device that pulls up the
    output for a high output.
    • Instead of a combination
    of active pull-down and
    pull-up networks, such a
    gate consists of an NMOS
    pull-down network that
    realizes the logic function,
    and a simple load device.
    Pseudo-NMOS
    • Reduced number of
    transistors (N+1 vs 2N for
    CMOS)
    • The nominal high output
    voltage (VOH) for this gate is
    VDD.
    • nominal low output voltage is
    not 0 V.
    • This results in low noise
    margins
    • Results in static power
    dissipation. (a factor that may
    limit the use of this style)
    DYNAMIC CMOS DESIGN
    Dynamic CMOS Logic Circuits
    Refer to class notes for this

    ADVANTAGES OF DYNAMIC LOGIC


    CIRCUITS
    Signal Integrity Issues in Dynamic Design

    • Several important considerations that must be


    taken into account if a dynamic circuit has to
    function properly:
    – Charge Leakage
    – Charge Sharing
    – Capacitive Coupling
    – Clock-feedthrough
    Charge Leakage
    Charge Sharing
    Please study advantages and disadvantages
    for domino logic as well
    The next dynamic circuit is MODL
    circuit; for which you need to refer
    the adders ppt.

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