Heaven’s Light is Our Guide

Department of Computer Science & Engineering

Rajshahi University of Engineering & Technology, Bangladesh

Course Code: CSE 2203

Course Title: Digital Techniques

Presented by,
Md. Zahirul Islam
 Combinational Logic Circuit
from Logic Function
• Consider function F = A’ + B•C’ + A’•B’
• A combinational logic circuit can be constructed to implement F, by
appropriately connecting input signals and logic gates:
– Circuit input signals  from function variables (A, B, C)
– Circuit output signal  function output (F)
– Logic gates  from logic operations

A F

B
 Combinational Logic Circuit
from Logic Function (cont.)
• In order to design a cost-effective and
A B C F G
efficient circuit, we must minimize the
0 0 0 1 1
circuit’s size (area) and propagation
delay (time required for an input signal 0 0 1 1 1
change to be observed at the output 0 1 0 1 1
line) 0 1 1 1 1
• Observe the truth table of F=A’ + B•C’ 1 0 0 0 0
+ A’•B’ and G=A’ + B•C’ 1 0 1 0 0
• Truth tables for F and G are identical 1 1 0 1 1
 same function
1 1 1 0 0
• Use G to implement the logic circuit
(less components)
Combinational Logic Circuit
from Logic Function (cont.)
C

A F

C
B
A G
 Boolean expressions-NOT unique

• Unlike truth tables, expressions x y z F G

representing a Boolean function are 0 0 0 1 1
NOT unique.
0 0 1 0 0
• Example:
– F(x,y,z) = x’•y’•z’ + x’•y•z’ + x•y•z’ 0 1 0 1 1
– G(x,y,z) = x’•y’•z’ + y•z’ 0 1 1 0 0
• The corresponding truth tables for F()
1 0 0 0 0
and G() are to the right. They are
identical. 1 0 1 0 0
• Thus, F() = G() 1 1 0 1 1
1 1 1 0 0
 Algebraic Manipulation
• Boolean algebra is a useful tool for
simplifying digital circuits.
• Why do it? Simpler can mean cheaper,
smaller, faster.
• Example: Simplify F = x’yz + x’yz’ + xz.
F = x’yz + x’yz’ + xz
= x’y(z+z’) + xz
= x’y•1 + xz
= x’y + xz
 Algebraic Manipulation (cont.)
• Example: Prove
x’y’z’ + x’yz’ + xyz’ = x’z’ + yz’
• Proof:
x’y’z’+ x’yz’+ xyz’
= x’y’z’ + x’yz’ + x’yz’ + xyz’
= x’z’(y’+y) + yz’(x’+x)
= x’z’•1 + yz’•1
= x’z’ + yz’
 Complement of a Function
• The complement of a function is derived
by interchanging (• and +), and (1 and 0),
and complementing each variable.
• Otherwise, interchange 1s to 0s in the
truth table column showing F.
• The complement of a function IS NOT
THE SAME as the dual of a function.
 Complementation: Example
• Find G(x,y,z), the complement of
F(x,y,z) = xy’z’ + x’yz
• G = F’ = (xy’z’ + x’yz)’
= (xy’z’)’ • (x’yz)’ DeMorgan
= (x’+y+z) • (x+y’+z’) DeMorgan again
• Note: The complement of a function can also be
derived by finding the function’s dual, and then
complementing all of the literals
 Canonical and Standard Forms
• We need to consider formal techniques for
the simplification of Boolean functions.
– Identical functions will have exactly the same
canonical form.
– Minterms and Maxterms
– Sum-of-Minterms and Product-of- Maxterms
– Product and Sum terms
– Sum-of-Products (SOP) and Product-of-Sums
(POS)
 Definitions
• Literal: A variable or its complement
• Product term: literals connected by •
• Sum term: literals connected by +
• Minterm: a product term in which all the
variables appear exactly once, either
complemented or uncomplemented
• Maxterm: a sum term in which all the variables
appear exactly once, either complemented or
uncomplemented
 Minterm
• Represents exactly one combination in the truth
table.
• Denoted by mj, where j is the decimal equivalent
of the minterm’s corresponding binary
combination (bj).
• A variable in mj is complemented if its value in bj
is 0, otherwise is uncomplemented.
• Example: Assume 3 variables (A,B,C), and j=3.
Then, bj = 011 and its corresponding minterm is
denoted by mj = A’BC
 Maxterm
• Represents exactly one combination in the truth
table.
• Denoted by Mj, where j is the decimal equivalent
of the maxterm’s corresponding binary
combination (bj).
• A variable in Mj is complemented if its value in bj
is 1, otherwise is uncomplemented.
• Example: Assume 3 variables (A,B,C), and j=3.
Then, bj = 011 and its corresponding maxterm is
denoted by Mj = A+B’+C’
 Truth Table notation for Minterms
and Maxterms
• Minterms and x y z Minterm Maxterm
Maxterms are 0 0 0 x’y’z’ = m0 x+y+z = M0
easy to denote
0 0 1 x’y’z = m1 x+y+z’ = M1
using a truth
table. 0 1 0 x’yz’ = m2 x+y’+z = M2

• Example: 0 1 1 x’yz = m3 x+y’+z’= M3

Assume 3 1 0 0 xy’z’ = m4 x’+y+z = M4
variables x,y,z 1 0 1 xy’z = m5 x’+y+z’ = M5
(order is fixed) 1 1 0 xyz’ = m6 x’+y’+z = M6
1 1 1 xyz = m7 x’+y’+z’ = M7
 Canonical Forms (Unique)
• Any Boolean function F( ) can be
expressed as a unique sum of minterms
and a unique product of maxterms (under
a fixed variable ordering).
• In other words, every function F() has two
canonical forms:
– Canonical Sum-Of-Products (sum of
minterms)
– Canonical Product-Of-Sums (product of
maxterms)
 Canonical Forms (cont.)
• Canonical Sum-Of-Products:
The minterms included are those mj such that
F( ) = 1 in row j of the truth table for F( ).
• Canonical Product-Of-Sums:
The maxterms included are those Mj such
that F( ) = 0 in row j of the truth table for F( ).
 Example
• Truth table for f1(a,b,c) at right
a b c f1
• The canonical sum-of-products form
for f1 is 0 0 0 0
f1(a,b,c) = m1 + m2 + m4 + m6 0 0 1 1
= a’b’c + a’bc’ + ab’c’ + abc’
• The canonical product-of-sums form 0 1 0 1
for f1 is 0 1 1 0
f1(a,b,c) = M0 • M3 • M5 • M7 1 0 0 1
= (a+b+c)•(a+b’+c’)•
(a’+b+c’)•(a’+b’+c’). 1 0 1 0
• Observe that: mj = Mj’ 1 1 0 1
1 1 1 0
 Shorthand: ∑ and ∏
• f1(a,b,c) = ∑ m(1,2,4,6), where ∑ indicates that
this is a sum-of-products form, and m(1,2,4,6)
indicates that the minterms to be included are
m1, m2, m4, and m6.
• f1(a,b,c) = ∏ M(0,3,5,7), where ∏ indicates that
this is a product-of-sums form, and M(0,3,5,7)
indicates that the maxterms to be included are
M0, M3, M5, and M7.
• Since mj = Mj’ for any j,
∑ m(1,2,4,6) = ∏ M(0,3,5,7) = f1(a,b,c)
Conversion Between Canonical Forms

• Replace ∑ with ∏ (or vice versa) and replace those j’s

that appeared in the original form with those that do not.
• Example:
f1(a,b,c) = a’b’c + a’bc’ + ab’c’ + abc’
= m1 + m2 + m 4 + m 6
= ∑(1,2,4,6)
= ∏(0,3,5,7)
= (a+b+c)•(a+b’+c’)•(a’+b+c’)•(a’+b’+c’)
 Standard Forms (NOT Unique)
• Standard forms are “like” canonical forms,
except that not all variables need appear
in the individual product (SOP) or sum
(POS) terms.
• Example:
f1(a,b,c) = a’b’c + bc’ + ac’
is a standard sum-of-products form
• f1(a,b,c) = (a+b+c)•(b’+c’)•(a’+c’)
is a standard product-of-sums form.
 Conversion of SOP from standard
to canonical form
• Expand non-canonical terms by inserting
equivalent of 1 in each missing variable x:
(x + x’) = 1
• Remove duplicate minterms
• f1(a,b,c) = a’b’c + bc’ + ac’
= a’b’c + (a+a’)bc’ + a(b+b’)c’
= a’b’c + abc’ + a’bc’ + abc’ + ab’c’
= a’b’c + abc’ + a’bc + ab’c’
 Conversion of POS from standard
to canonical form
• Expand noncanonical terms by adding 0 in terms
of missing variables (e.g., xx’ = 0) and using the
distributive law
• Remove duplicate maxterms
• f1(a,b,c) = (a+b+c)•(b’+c’)•(a’+c’)
= (a+b+c)•(aa’+b’+c’)•(a’+bb’+c’)
= (a+b+c)•(a+b’+c’)•(a’+b’+c’)•
(a’+b+c’)•(a’+b’+c’)
= (a+b+c)•(a+b’+c’)•(a’+b’+c’)•(a’+b+c’)
 Karnaugh Maps
• Karnaugh maps (K-maps) are graphical
representations of boolean functions.
• One map cell corresponds to a row in the
truth table.
• Also, one map cell corresponds to a minterm
or a maxterm in the boolean expression
• Multiple-cell areas of the map correspond to
standard terms.
 Two-Variable Map
x2 x1
x1 0 1 x2 0 1
0 1 0 2
0 m0 m1
OR 0 m0 m2
2 3 1 3
1 m2 m3 1 m1 m3

NOTE: ordering of variables is IMPORTANT

for f(x1,x2), x1 is the row, x2 is the column.
Cell 0 represents x1’x2’; Cell 1 represents x1’x2;
etc. If a minterm is present in the function, then
a 1 is placed in the corresponding cell.
 Two-Variable Map (cont.)
• Any two adjacent cells in the map differ by
ONLY one variable, which appears
complemented in one cell and
uncomplemented in the other.
• Example:
m0 (=x1’x2’) is adjacent to m1 (=x1’x2) and m2
(=x1x2’) but NOT m3 (=x1x2)
 2-Variable Map -- Example
• f(x1,x2) = x1’x2’+ x1’x2 + x1x2’
= m 0 + m1 + m2
= x 1’ + x2’
• 1s placed in K-map for x2
specified minterms m0, m1, m2 x1 0 1
• Grouping (ORing) of 1s allows 0 1
simplification
• What (simpler) function is 0 1 1
represented by each dashed
rectangle? 2 3
– x1’ = m0 + m1
– x2’ = m0 + m2 1 1 0
• Note m0 covered twice
 Minimization as SOP using K-map
• Enter 1s in the K-map for each product term
in the function
• Group adjacent K-map cells containing 1s to
obtain a product with fewer variables. Group
size must be in power of 2 (2, 4, 8, …)
• Handle “boundary wrap” for K-maps of 3 or
more variables.
• Realize that answer may not be unique
 Three-Variable Map
yz
x 00 01 11 10
0 1 3 2

0 m0 m1 m3 m2
4 5 7 6

1 m4 m5 m7 m6

-Note: variable ordering is (x,y,z); yz specifies column,

x specifies row.
-Each cell is adjacent to three other cells (left or right
or top or bottom or edge wrap)
 Three-Variable Map (cont.)
minterm

The types of structures that

are either minterms or are
generated by repeated
application of the minimization
theorem on a three variable
map are shown at right.
Groups of 1, 2, 4, 8 are
possible.
group of 2 terms

group of 4 terms
 Simplification
• Enter minterms of the Boolean function into
the map, then group terms
• Example: f(a,b,c) = a’c + abc + bc’
• Result: f(a,b,c) = a’c+ b
abc
1 1 1
1 1
1 1 1
1 1
 More Examples
yz
X 00 01 11 10

• f1(x, y, z) = ∑ m(2,3,5,7) 0 1 1
1 1 1
 f1(x, y, z) = x’y + xz

• f2(x, y, z) = ∑ m (0,1,2,3,6)
1 1 1 1
f2(x, y, z) = x’+yz’
1
 Four-Variable Maps
YZ

00 01 11 10
WX

00 m0 m1 m3 m2

01 m4 m5 m7 m6

11 m12 m13 m15 m14

10 m8 m9 m11 m10

• Top cells are adjacent to bottom cells. Left-edge

cells are adjacent to right-edge cells.
• Note variable ordering (WXYZ).
Four-variable Map Simplification
• One square represents a minterm of 4 literals.
• A rectangle of 2 adjacent squares represents a
product term of 3 literals.
• A rectangle of 4 squares represents a product
term of 2 literals.
• A rectangle of 8 squares represents a product
term of 1 literal.
• A rectangle of 16 squares produces a function
that is equal to logic 1.
 Example
• Simplify the following Boolean function
(A,B,C,D) = ∑m(0,1,2,4,5,7,8,9,10,12,13).
• First put the function g( ) into the map, and then
group as many 1s as possible.
ab cd
1 1 1 1 1 1

1 1 1 1 1 1

1 1 1 1

1 1 1 1 1 1

g(A,B,C,D) = c’+b’d’+a’bd
 Don't Care Conditions
• There may be a combination of input values which
– will never occur
– if they do occur, the output is of no concern.
• The function value for such combinations is called a
don't care.
• They are denoted with x or –. Each x may be
arbitrarily assigned the value 0 or 1 in an
implementation.
• Don’t cares can be used to further simplify a function
 cd
ab 00 01 11 10
Example 00 0 1 0 1
01 1 1 0 1
• Simplify the function f(a,b,c,d) 11 0 0 x x
10 1 1 x x

whose K-map is shown at the 0 1 0 1

right. 1 1 0 1
• f = a’c’d+ab’+cd’+a’bc’ 0 0 x x
1 1 x x
or
• f = a’c’d+ab’+cd’+a’bd’ 0 1 0 1
1 1 0 1
0 0 x x
1 1 x x
 cd
Another Example ab
x 1 0 0
1 x 0 x
• Simplify the function 1 x x 1

g(a,b,c,d) whose K-map 0 x x 0

is shown at right. x 1 0 0
• g = a’c’+ ab 1 x 0 x
1 x x 1
or 0 x x 0
• g = a’c’+b’d
x 1 0 0
1 x 0 x
1 x x 1
0 x x 0
 AND-OR (SOP) Emulation
Using NANDs

Two-level implementations

a) Original SOP
b) Implementation with NANDs
 AND-OR (SOP) Emulation
Using NANDs (cont.)

Verify:
(a) G = WXY + YZ

(b) G = ( (WXY)’ • (YZ)’ )’

= (WXY)’’ + (YZ)’’ = WXY + YZ
 SOP with NAND

(a) Original SOP

(b) Double inversion and grouping AND-NOT
(c) Replacement with NANDs
NOT-OR
 Two-Level NAND Gate
Implementation - Example
F (X,Y,Z) = m(0,6)
1. Express F in SOP form:
F = X’Y’Z’ + XYZ’
2. Obtain the AND-OR implementation for
F.
3. Add bubbles and inverters to transform
AND-OR to NAND-NAND gates.
 Example (cont.)

Two-level implementation with NANDs

F = X’Y’Z’ + XYZ’
 Multilevel NAND Circuits
Starting from a multilevel circuit:
1. Convert all AND gates to NAND gates with AND-
NOT graphic symbols.
2. Convert all OR gates to NAND gates with NOT-OR
graphic symbols.
3. Check all the bubbles in the diagram. For every
bubble that is not counteracted by another bubble
along the same line, insert a NOT gate or
complement the input literal from its original
appearance.
 Example
Use NAND gates
and NOT gates to
implement
Z=E’F(AB+C’+D’)+GH
AB
AB+C’+D’
E’F(AB+C’+D’)
E’F(AB+C’+D’)+GH

Boolean Algebra PJF - 44

Yet Another Example!
 Two-Level NOR Gate
Implementation - Example
F(X,Y,Z) = m(0,6)
1. Express F’ in SOP form:
1. F’ = m(1,2,3,4,5,7)
= X’Y’Z + X’YZ’ + X’YZ + XY’Z’ + XY’Z + XYZ
2. F’ = XY’ + X’Y + Z
2. Take the complement of F’ to get F in the POS form: F
= (F’)' = (X'+Y)(X+Y')Z'
3. Obtain the OR-AND implementation for F.
4. Add bubbles and inverters to transform OR-AND
implementation to NOR-NOR implementation.
 Example (cont.)

Two-level implementation with NORs

F = (F’)' = (X'+Y)(X+Y')Z'
 Simplifying Logic Circuits (Practice)
• The circuits shown provide the same output
– Circuit (b) is clearly less complex.

Logic circuits can be simplified using

Boolean algebra and Karnaugh mapping.
 Algebraic Simplification
Simplify the logic circuit shown.

The first step is to determine the expression for the output: z = ABC + AB • (A C)

Once the expression

is determined, break
down large inverter
signs by DeMorgan’s
theorems & multiply
out all terms.
 Algebraic Simplification
Simplify the logic circuit shown.

Factoring—the first & third terms above have

AC in common, which can be factored out:

Since B + B = 1, then…

Factor out A, which results in…

Algebraic Simplification
Simplifed logic circuit.

z = A(C + B)
Designing Combinational Logic Circuits
• To solve any logic design problem:
– Interpret the problem and set up its truth table.
– Write the AND (product) term for each case where output = 1.
– Combine the terms in SOP form.
– Simplify the output expression if possible.
– Implement the circuit for the final, simplified expression.

Circuit that
produces a 1
output only for
the A = 0, B = 1
condition.
Designing Combinational Logic Circuits
An AND gate with appropriate inputs can be used to
produce a HIGH output for a specific set of input levels.
Designing Combinational Logic Circuits
Each set of input conditions that is to produce a
1 output is implemented by a separate AND gate.
The AND outputs are ORed
OR to produce the final output.
Designing Combinational Logic Circuits

Truth table for a 3-input circuit.

AND terms for each
case where output is 1.
Designing Combinational Logic Circuits
Design a logic circuit with three inputs, A, B, and C.
Output to be HIGH only when a majority inputs are HIGH.
AND terms for each
Truth table. case where output is 1.

SOP expression for the output:

Designing Combinational Logic Circuits
Design a logic circuit with three inputs, A, B, and C.
Output to be HIGH only when a majority inputs are HIGH.
Simplified output expression:

Implementing the
circuit after factoring:

Since the expression is in SOP form, the circuit is a

group of AND gates, working into a single OR gate,
Exclusive OR and Exclusive NOR
Circuits

Truth table and circuit

for detecting equality of
two-bit binary numbers.
Exclusive OR and Exclusive NOR
Circuits

How an XNOR gate may

be used to simplify circuit
implementation.
Thank You