05 Combinational Logic Building Blocks

Second year Class 2019- 2020
BME Department
College of Engineering
University of Dohuk
Combinational Logic Building Blocks
https://sites.google.com/a/uod.ac/digital-systems/lectures
Prof Ahmed Khorsheed Al-Sulaifanie

January 2020
Textbook References
Stephen Brown and Zvonko Vranesic, “Fundamentals of Digital Logic with VHDL Design”, 3rd Edition, 2009, McGraw-Hill
Companies, Inc.
Chapter 6: Combinational-Circuit Building Blocks page 317

Multiplexers
log2n selection inputs
n inputs 1 output
• multiplexer
– n binary inputs (binary input = 1-bit input)
– log2n binary selection inputs
– 1 binary output
– Function: one of n inputs is placed onto output
– Called n-to-1 multiplexer
2-to-1 Multiplexer
One selection input =log22=1
s
s f
w0 0 w0
2 inputs f 0
w1 1 1 w1
(a) Graphical symbol (b) Truth table
w0
s f
w1
(c) Sum-of-products circuit
Source: Brown and Vranesic

4-to-1 Multiplexer
s0
s1 s1 s0 f
w0 00 0 0 w0
w1 01 w1
f 0 1
w2 10 w2
1 0
w3 11
1 1 w3
(a) Graphic symbol (b) Truth table
s0
w0
s1
w1
w2
w3
Source: Brown and Vranesic (c) Circuit

Decoders
wn-1 y2n – 1
n
inputs 2n
w0 outputs
Enable y0
En
• Decoder
– n binary inputs
– 2n binary outputs
– Function: decode encoded information
• If enable=1, one output is asserted high, the other outputs are asserted low
• If enable=0, all outputs asserted low
– Often, enable pin is not needed (i.e. the decoder is always enabled)
– Called n-to-2n decoder
• Can consider n binary inputs as a single n-bit input
• Can consider 2n binary outputs as a single 2n-bit output
– Decoders are often used for RAM/ROM addressing
En w1 w0
2-to-4 Decoder
y3 y 2 y1 y0
w1 y3
1 0 0 0 0 0 1
w0 y2
1 0 1 0 0 1 0
y1
1 1 0 0 1 0 0
En y0
1 1 1 1 0 0 0
0 - - 0 0 0 0
(a) Truth table (b) Graphical symbol
w0
y0
w1
y1
One or more enable

y2
input control line En
may be used to
control the operation
y3
of decoder
En
Source: Brown and Vranesic
(c) Logic circuit
Demultiplexers
log2n selection inputs
1 input n outputs
• Demultiplexer
– 1 binary input
– n binary outputs
– log2n binary selection inputs
– Function: places input onto one of n outputs, with the remaining outputs asserted
low
– Called 1-to-n demultiplexer
• Closely related to decoder
– Can build 1-to-n demultiplexer from log2n-to-n decoder by using the decoder's
enable signal as the demultiplexer's input signal, and using decoder's input signals
as the demultiplexer's selection input signals.
1-to-4 Demultiplexer
Encoders
w2 n – 1
yn – 1
2n n
inputs outputs
y0
w0
• Encoder
– 2n binary inputs
– Function: encodes information into an n-bit code
– Called 2n-to-n encoder
• Can consider 2n binary inputs as a single 2n-bit input
• Can consider n binary output as a single n-bit output
• Encoders only work when exactly one binary input is equal to 1
4-to-2 Encoder
w3 w2 w1 w0 y1 y0
0 0 0 1 0 0
0 0 1 0 0 1
0 1 0 0 1 0
1 0 0 0 1 1
(a) Truth table
w0
w1
y0
w2
y1
w3
(b) Circuit
Priority Encoders
w2n – 1
yn – 1
2n n
inputs outputs
y0
w0 z "valid" output
• Priority Encoder
– 2n binary inputs
– 1 binary "valid" output
– Function: encodes information into an n-bit code based on priority of inputs
– Called 2n-to-n priority encoder
• Priority encoder allows for multiple inputs to have a value of '1', as it encodes the
input with the highest priority (MSB = highest priority, LSB = lowest priority)
– "valid" output indicates when priority encoder output is valid
– Priority encoder is more common than an encoder
4-to-2 Priority Encoder
This Priority encoder consists of 4 inputs and three outputs. Although an encoder has 2 n inputs and n
outputs, it has a third output ‘V’ which is a valid bit indicator and is set to one when one or more
inputs are active or equal to 1.
This valid bit is zero when all the inputs are zero which indicates that there is no valid input. On this
condition, other outputs are considered as don’t care conditions and are not inspected when V is zero.
In the truth table, D3 has the highest priority and D0 has lowest priority. When D3 is active or 1, then
regardless of other inputs, the output is 11.
The next higher priority is D2 after D3. Y1 = ∑ m (1, 2, 3, 5, 6, 7, 9, 10, 11, 13, 14, 15)
Y0 = ∑ m (1, 3, 4, 5, 7, 9, 11, 12, 13, 15)
Then from the below K-maps we obtain the outputs as

Y1 = D3 + D2
Y0 = D3 + D2’ D1
Application: Positional Encoders
As one common application is in magnetic positional control as used on ships navigation or for robotic
arm positioning etc. Here for example, the angular or rotary position of a compass is converted into a
digital code by a 74LS148 chip. This chip convert 8-to-3 line priority encoder and input to the systems
computer to provide navigational data and an example of a simple 8 position to 3-bit output compass
encoder is shown below. Magnets and reed switches could be used at each compass point to indicate
the needles angular position.
Binary Output
Compass Direction
Q0 Q1 Q2
North 0 0 0
North-East 0 0 1
East 0 1 0
South-East 0 1 1
South 1 0 0
South-West 1 0 1
West 1 1 0
North-West 1 1 1
Tri-state Buffer
Three state gates are digital circuits that exhibit three states. Two of the states are signals
equivalent to logic 0 and logic 1 as in the conventional gate. The third state is a high
impedance state, in which the logic behaves like an open circuit.
e
x f
e x f
(a) A tri-state buffer 0 0 Z

0 1 Z
1 0 0
e=0 1 1 1
x f
(c) Truth table
e=1
x f
(b) Equivalent circuit

MUX with Three State Gates
It is possible to connect the output of three state gates to
common line without causing loading effect.
Home work
(Q1) Design 3X8 decoder using two 2X4 decoders with Enable inputs.
(Q2) Design 4X1 Multiplexer using 2X1 Multiplexers.

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Second year Class 2019- 2020

Combinational Logic Building Blocks

Prof Ahmed Khorsheed Al-Sulaifanie

Chapter 6: Combinational-Circuit Building Blocks page 317

log2n selection inputs

(a) Graphical symbol (b) Truth table

(c) Sum-of-products circuit

Source: Brown and Vranesic

(a) Graphic symbol (b) Truth table

Source: Brown and Vranesic (c) Circuit

One or more enable

(a) Truth table

Then from the below K-maps we obtain the outputs as

(a) A tri-state buffer 0 0 Z

(b) Equivalent circuit

(Q2) Design 4X1 Multiplexer using 2X1 Multiplexers.

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