Computer Organization &

Architecture
Chapter 1
Introduction to COA

By Bhushan Inje
 Outline
• Course Objective
• Course Outcomes
• Prescribed Text
• Evaluation
• Syllabus Structure
• Introduction to Computer Organization and Architecture
 Course Objective
• To impart knowledge of the Basic Principles of Organization,
Operation.
• To impart knowledge of Performance of modern day computer
system and the underlying integrated circuit technology used to
construct computer components.
• To make students aware of Parallel organization concepts
 Course Outcomes
• After successfully completion of this course, students will be
able to:
• Compare and contrast computer architecture and computer organization.

• Describe the operation memory and system bus.

• Describe various components of CPU and its functionalities.

• Discuss various operations and flynn’s classification.

 Prescribed Text
S.No. Title Author Publisher
1. Computer Organization and William Stallings Prentice Hall,
Architecture: Design for
performance

References:
S.No Title Author Publisher
1. Computer Architecture and John Hayes McGraw Hill
Organization

2. Computer Organization Tanenbaum PHI

3. Digital Logic & Computer Design Moris Mano Pearson Education
 Evaluation
End Term Exam There will be one end term exam after the 50
completion of all the sessions.

Quizzes and Spread throughout. They will be given at a particular 50

assignments interval in the class

Internal Test Theory and application exercises.

 Syllabus Structure
• Chapter 1: Introduction to Computer Organization and Architecture
• Chapter 2: System Buses (A TOP-LEVEL VIEW OF COMPUTER FUNCTION AND INTERCONNECTION)
• Chapter 3 : Memory Organization
• Chapter 4: Data Path Design
• Chapter 5: Control unit
• Chapter 6: Input Output Unit
• Chapter 7: I/O Channels and Processors
• Chapter 8: Multiprocessor Organizations
 Architecture & Organization
• Architecture
• Architectural attributes include the instruction set, the number of bits used to represent various data
types (e.g., numbers, characters), I/O mechanisms, and techniques for addressing memory.
• e.g. Architectural design issue whether a computer have a multiply instruction?

• Organization is how features are implemented

• Control signals, interfaces, memory technology.

• Organizational attributes include those hardware details transparent to the programmer, such as
control signals; interfaces between the computer and peripherals; and the memory technology used.
• e.g. Is there a hardware multiply unit or is it done by repeated addition?
 Architecture & Organization Cont..
• All Intel x86 family share the same basic architecture.
• The IBM System/370 family share the same basic architecture
• This gives code compatibility
• At least backwards
• Organization differs between different versions.
• Organization changing with changing technology.

Changes in technology not only influence organization but also result in the introduction of more powerful and more
complex architectures.
 Structure & Function
• The behaviour at each level depends only on a simplified, abstracted
characterization of the system at the next lower level.
• At each level, the designer is concerned with structure and function:

• Structure : The way in which components relate to each other.

• Function : The operation of individual components as part of the structure.
 Function
• The computer system will be described from the top down.
• We begin with the major components of a computer, describing their
structure and function, and proceed to successively lower layers of
the hierarchy.
 Functional view

• All computer functions are:

• Data processing
• Data storage
• Data movement
• Control
 Operations (1) Data movement

• The computer can function as a data movement device

(Figure a), simply transferring data from one
peripheral or communication line to another.
 Operations (2) Storage

• It can also function as a data storage device (Figure b.), with data
transferred from the external environment to computer storage (read)
and vice versa (write).
Operation (3) Processing from/to storage
Operation (4) Processing from storage to I/O
Structure
 Structure - Top Level
• There are four main structural components:
• Central processing unit (CPU): Controls the operation of the
computer and performs its data processing functions; often
simply referred to as processor.
• Main memory: Stores data.
• I/O: Moves data between the computer and its external
environment.
• System interconnection: Some mechanism that provides for
communication among CPU, main memory, and I/O. A common
example of system interconnection is by means of a system bus,
consisting of a number of conducting wires to which all the
other components attach.
 Structure - Top Level
• Central processing unit (CPU):
Controls the operation of the
computer and performs its data Peripherals Computer
processing functions; often simply
referred to as processor. Central
• Main memory: Stores data. Main
Processing Memory
• I/O: Moves data between the Unit
computer and its external
environment. Computer Systems
• System interconnection: Some Interconnection
mechanism that provides for
communication among CPU, main
memory, and I/O. A common Input
example of system Output
interconnection is by means of a Communication
system bus, consisting of a lines
number of conducting wires to
which all the other components
attach.
 Structure - The CPU
• Control unit: Controls the operation
of the CPU and hence the computer.
CPU

• Arithmetic and logic unit (ALU): Computer Arithmetic

Registers and
Performs the computer’s data I/O
Login Unit
processing functions. System CPU
Bus
• Registers: Provides storage internal to Internal CPU
Memory Interconnection
the CPU.
• CPU interconnection: Some
Control
mechanism that provides for Unit

communication among the control unit,

ALU, and registers.
Structure - The Control Unit

Control Unit

CPU Sequencing
ALU Logic
Control
Internal
Unit
Bus Control Unit
Registers
Registers and
Decoders

Control
Memory
Computer Evolution and Performance
Computer Evolution and Performance
Computer Evolution and Performance
• The First Generation: Vacuum Tubes
• ENIAC – background
• Electronic Numerical Integrator And Computer
• Eckert and Mauchly
• University of Pennsylvania
• The world’s First general purpose electronic digital
comp.
• Army’s Ballistics Research Lab(BRL)
• Trajectory tables for weapons
• Started 1943
• Finished 1946
• Too late for war effort
• Used until 1955
ENIAC - details
• Decimal (not binary)
• 20 accumulators (10 digits decimal each)
• Programmed manually by switches
• Ring of 10 vacuum tubes represented
each digit.
• 18,000 vacuum tubes
• 30 tons
• 15,000 square feet
• 140 kW power consumption
• 5,000 additions per second
• its first task was to perform a series of
complex calculations that were used to
help determine the feasibility of the
hydrogen bomb.
 Moore’s Law
• Increased density of components on chip
• Gordon Moore - cofounder of Intel
• Number of transistors on a chip will double
every year
• Since 1970’s development has slowed a little
• Number of transistors doubles every 18 months
• Cost of a chip has remained almost unchanged
• Higher packing density means shorter electrical
paths, giving higher performance
• Smaller size gives increased flexibility
• Reduced power and cooling requirements
• Fewer interconnections increases reliability
 Von Neumann / Turing
• Stored Program concept.
• EDVAC – Electronic Discrete Variable Computer.
• Main memory storing programs and data.
• ALU operating on binary data.
• Control unit interpreting instructions from memory and executing.
• Input and output equipment operated by control unit.
• Princeton Institute for Advanced Studies.
• IAS
• Completed 1952.
• Used the term “organ” to describe devices.
• it will have to perform the elementary operations of arithmetic most frequently.
 Structure of von Neumann machine (IAS Comp)

Stores both data

and instruction
I/O equipment
operated by the
control unit

Interprets the instructions in memory and causes

them to be executed
 Von Neumann Machine
• Features
• The memory of the IAS consists of 1000 storage locations, called words, of
40 binary digits (bits) each.
• Both data and instructions are stored there.
• Numbers are represented in binary form, and each instruction is a binary
code.
 IAS - details
• 1000 x 40 bit words
• Binary number
• 2 x 20 bit instructions
 IAS - details
• Set of registers (storage in CPU)
• Memory Buffer Register (MBR):- Contains a word to be stored in memory
or sent to I/O unit, or is used to receive a word from memory or from the
I/O unit.
• Memory Address Register (MAR):- Specifies the address in memory of the
word to be written from or read into the MBR.
• Instruction Register (IR):- Content the 8-bit opcode instruction being
executed.
• Instruction Buffer Register (IBR):- Employed to hold temporarily the right
hand instruction from a word in memory.
• Program Counter (PC):- Contains the address of the next instruction-pair to
be fetched from memory.
• Accumulator (AC) , Multiplier Quotient (MQ) :Employed to hold temporarily
operands and results of ALU operations.
Structure of IAS
–
detail
Also see Figure 2.4 that illustrates Fetch cycle
and Execution cycle, which taken together is the
Instruction cycle.
• The IAS operates by repetitively
performing an instruction cycle.
• Each instruction cycle is divide in two
subcycle.
• During Fetch cycle the opcode of the
next instruction is loaded into the IR
and the address portion is loaded into
the MAR.
• This instruction maybe taken from the
IBR. or it can be loaded from the
memory by loading a word into the
MBR, then down to the IBR,IR,MAR.
• Once the opcode is in IR the execution
cycle is performed.
IAS Instruction Set
• IAS has total 21 Instruction.
Internet Resources
• http://www.intel.com/
• Search for the Intel Museum
• http://www.ibm.com
• http://www.dec.com
• Charles Babbage Institute
• PowerPC
• Intel Developer Home