Chapter 1b: BJT Bias Design BJT Bias Design

Chapter 1b
BJT
BJTBias
BiasDesign
Design
EN564 Analogue Electronics

EUE3233 Analogueand Instrumentation
Electronics
A BJT amplifier circuit should be designed to
 ensure that the BJT operates in the active mode,
 allow the desired level of DC current to flow, and
 couple to a small-signal input source and to an
output “load”.
Proper “DC biasing” is required!
When symmetrical sinusoidal signal applied to the
input of an amplifier, the output generated is also a
symmetrical sinusoidal signal
AC load line is used to determine maximum output
symmetrical swing
⧕ If output is out of limit, portion of the output signal will
be
clipped & signal distortion will occur
DC Load Line
The
intersection points on the and the

[in previous figure as both and becomes open-circuit for dc
voltages]
AC Load Line
The
intersection points on the and the

[in previous figure as is shorted by ]
EXAMPLE
R1 = 56 kΩ
R2 = 8 kΩ
RC = 2.2 kΩ
RE = 680 Ω
β = 150
ICQ = 2.28 mA
VCEQ = 11.43 V
DC Load Line:
IC(sat) = 6.25 mA
AC
Load Line: VCE(off) = 18 V

IC (mA)
7.48
Notice that the difference
6.25 between DC cutoff voltage and
the ac cutoff voltage is given by
ICQ 1.55 V
2.2
8
VCE (V)
VCEQ 16.45 18
11.43
IC (mA)
7.48 The symmetrical swing of the

output without clipping for this
6.25 example is shown by:
ICQ
2.2
8
VCE VCE (V)

𝑉
𝐶𝐸𝑄 16.45 18
IC (mA)
7.48
To design for MSS: We are to
6.25 set the Q point at the middle of
the load line (after minus VE)
1.55 V
VCE (V)
VCEQ 16.45 18
(max
allowed swing beyond mid-point)
IC (mA)
7.48
6.25
The output is now at MSS
VCE (V)
V𝑉
CE𝐶𝐸𝑄 16.45 18
Steps to design a BJT amplifier for MSS:
⧕ Write DC load line equation (relates of ICQ & VCEQ)
⧕ Generally, ic = ICQ – IC(min), where IC(min) = 0 or some
other specified min collector current
⧕ Generally, vce = VCEQ – VCE(min), where VCE(min) is
some specified min C-E voltage (normally named VCE(sat)
which typical value is 0.2 V)
⧕ Combination of the above equations produce optimum
ICQ & VCEQ values to obtain maximum symmetrical
swing in output signal
“1/3, 1/3, 1/3 Rule” Bias
Procedure:
 Bias so that VCC is split equally
across RC, VCE and RE.
 Specify the desired collector
current
 Assume IE = IC to determine
RC
and RE
 Add 0.7 V to VRE to find VB

𝐼 𝐶 ′
𝐼 𝐶
𝐼 𝐵
𝐼 𝐸
 For
dc analysis, coupling capacitors will have infinite impedance
(from , when ) and can therefore be omitted for dc circuit
analysis. The output is taken from the transistor collector.
• As we want the Q-point to be at mid-point of the
load line, apply the 50:50 rule in working out the
voltage drop between to , and .
• The equations to calculate and can be derived to
the following:

(assuming )
 A bias circuit is required to bias a transistor to half the
supply voltage.
 A BC107A transistor with hFE of 200 is used and supply
voltage, VCC is 20 volts.
 The collector current is to be 1mA. The resistor values
are:

This is the most widely used biasing scheme in
general electronics.
For a single stage best
amplifier this in
circuit offers the
resilience
The disadvantage tois that a couple of extra resistors
temperature
are required, but this is outweighed by the
changes and stability.
advantage of excellent
variation device
characteristics.
“Rule of Thumb” BJT Bias Design

 IRB is only 10% (or less)

compared to IRC

 RB is only 10% (or less)

compared to βRE
1. Bias so that VCC is split equally across RC, VCE and RE.
2. Specify
the desired collector current
3. Assume IE = IC to determine RC and RE.
4. Add 0.7 V to VE to find VB.
5. Choose RB approximately
6. Finally compute R1 and R2.
Design
a potential divider biased common emitter
amplifier where:
and
Assume .
Ignore VCE(Sat), design for MSS, VCC = 12V, IC=1mA, VE =

VCC/3. Solve using Thevenin’s equivalent circuit method,
where
𝛽 𝑅 𝐸
𝑅 𝐵𝐵 =
10
Design a potential divider bias BJT amplifier to establish
a current IE = 1 mA using a power supply VCC = 10 V.
The transistor is specified to have a nominal β value of
100.

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Chapter 1b

EN564 Analogue Electronics

7.48 The symmetrical swing of the

VCE VCE (V)

The output is now at MSS

 IRB is only 10% (or less)

 RB is only 10% (or less)

Ignore VCE(Sat), design for MSS, VCC = 12V, IC=1mA, VE =

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