Computer interfacing
Lecture 4
Interfacing Pins
Interfacing Pins
R D active low line–
active when the processor reads data from the memory
of any input device.
WR active low line–
active when the processor writes data to the memory of
any output device.
M/IO
0 processor (writs/reads) with I/O device
1 processor (writs/reads) with memory
Generating the control lines
R D W R M / IO
MEMR 0 1 1
MEMW 1 0 1
IO R 0 1 0
IO W 1 0 0
Generating the control lines
R D W R M / IO
M EM R
MEMW
IO W
IO R
Generating the control lines
R D W R M / IO
0 1 1
1
1 M EM R
1
MEMW
0
0
0
IO W
0 IO R
1
Generating the control lines
R D W R M / IO
1 0 1
0
0 M EM R
1 MEMW
1
0
1 IO W
0
0 IO R
Generating the control lines
R D W R M / IO
1 0 0
0
0 M EM R
0
MEMW
1
1
1 IO W
1
0 IO R
Generating the control lines
R D W R M / IO
0 1 0
0
1 M EM R
0
MEMW
0
1
0 IO W
1
1 IO R
Computer interfacing techniques
1. Memory mapped I/O
2. Isolated I/O
Memory mapped I/O
• Memory-mapped I/O uses the same memory
addresses to address both memory and I/O
devices.
• The device is connected directly to certain
main memory locations.
Memory mapped I/O
• Makes programming simpler.
• Do not have special commands to access I/O
devices.
• Takes some memory locations
– Very few compared to the size of main memory.
Memory mapped I/O
• Memory-mapped I/O uses special memory locations
in the normal address space of the CPU to
communicate with real-world devices.
• The memory map of the used computer should be
investigated in order to know which locations are
reserved for the operating system, which locations are
reserved for the monitor, and the free locations.
Memory mapped I/O
Memory mapped I/O
Interfacing with output devices
• Output devices are usually slow.
• Also, the output is usually expected to
continue appearing on the output device for a
long period of time.
• Given that the data will only be present on the
data lines for a very short period
(microseconds), it has to be latched externally.
Interfacing with output devices
• To do this, the external latch should be
enabled when the port’s address is present on
the address bus, and the MEMW is activated.
• The resulting signal would be active when the
output device is being accessed by the
processor.
Interfacing with output devices
Outputted data
---------
Ao
. Address
Latch
. decoding
An
MEMW
D0 D8
Interfacing of Input Devices
• The basic concepts are similar to interfacing of
output devices.
• The address lines are decoded to generate a
signal that is active when the particular port is
being accessed.
• An MEMR signal is activated.
Interfacing of Input Devices
• A tri-state buffer is used to connect the input
device to the data bus.
• The control (Enable) for these buffers is
connected to the result of combining the
address signal and the signal MEMR.
Interfacing of Input Devices
Inputted data
---------
Ao
. Address
Buffer
. decoding
An
M EM R
D0 D8
Isolated input output
• It treats them separately from memory.
– Isolated I/O uses separate memory space.
– The user in this case would access these
devices using the IN and OUT instructions
only.
Memory mapped IO Vs Isolated input output
Memory Mapped IO Isolated input output
IO is treated as memory. IO is treated IO.
32-bit addressing. 16- bit addressing.
More Decoder Hardware. Less Decoder Hardware.
Memory mapped IO Vs Isolated input
output
Memory Mapped IO Isolated input output
Less memory is available. Whole memory address
Memory Instructions are space is available.
used. Special Instructions are
Memory control signals used like IN, OUT.
are used. Special control signals
are used.
