Isolation

ISOLATION TECHNOLOGIES
• Technology to electrically isolate

devices from one another in a
VLSI chip.
Leakage Paths and Design Rules
1.Two neighbouring devices.

2. Junction to well.
3. Latch up Triggering
ISOLATION TECHNIQUES
• Diffusion Isolation
• Oxide Isolation
• LOCOS
• Trench Isolation
Diffusion Isolation
• Historically used for Bipolar

• Currently used to isolate NMOS from PMOS through a well
OXIDE ISOLATION
• Used in early days of MOS

•Field can,t be implanted for parasitic transistor Vt Control
•Step height is too much
Local Oxidation of Silicon : LOCOS
• Main method used today in a variety of forms

Trench Isolation
• Cutting edge technology today

2D Effects in Thermal Oxidation
• Variety of shaped
structures including
cylinder.
•The oxide is thinner on

both concave and
convex corners than in
flat regions
• Several physical mechanisms seem to be
1.1
important:
1200 ÞC • Crystal orientation
1.0
• 2D oxidant diffusion
1100 ÞC
0.9 • Stress due to volume expansion
• To model the stress effects, Kao et. al.
Normalized Oxide Thickness
0.8
1000 ÞC suggested modifying the Deal Grove
0.7
. parameters.
1100 ÞC
0.6 900 ÞC
  V    V 
0.5 1000 ÞC 800 ÞC k S (stress)  k S exp n R exp t T  (20)
900 ÞC  kT   kT 
0.4
 PVD 
0.3 Convex Radii
D(stress)  Dexp  (21)
Concave Radii  kT 
0.2 
0.1  PVS 
1 µm 0.2 µm 0.125 µm C (stress)  C exp
* *
 (22)
 kT 
2 3 5 
where  n and  t are the normal and
0 1 4 6 7 8
1/r µm-1
(Kao et.al)
tangential stresses at the interface.
VR, VT and VS are reaction volumes and

 are fitting
 parameters.
12
Idealized LOCOS Structure
Recessed LOCOS process in which the silicon is etched prior to

LOCOS to produce a final planar structure. The “ Bird’s Beak”
produced at the boundaries of such structure is not illustrated
here.
LOCOS : Different Approaches
• Illustration of the difference in shape and topography in a semi and fully

recessed LOCOS structure obtained by etching silicon prior to oxidation
Simulation Result using ATHENA
Recessed LOCOS Isolation Structure

LOCOS Structure: Process Parameter
Dependence
Parameters describing the bird”s beak in a semi –recessed

LOCOS and the bird’s beak and bird’s head in a fully LOCOS
structure .
Bird’s beak length dependence on nitride and pad oxide
thickness in a semi-recessed LOCOS. The field oxide was
grown at 1000C to a thickness of approximately 600nm.
Bird’s beak height dependence on nitride and pad oxide thickness in
a semi-recessed LOCOS. The field oxide was grown at 1000C to a
thickness of approximately 600nm.
Problems in scaling of LOCOS type isolation structures
The Kooi or White Ribbon effect is due to the nitridation of the Si

surface under the nitride mask edge. This can result in local thinning
of gate oxide. The local nitride can be removed by additional
oxidation and etch.
Field Oxide Thinning
Relative amount of field oxide thinning for a conventional

LOCOS structure and a PBL structure.Field oxidation was
done in a steam ambient at 1000C for 70min.
Forces in Local Oxidation of Silicon
Schematic representation of forces acting on the silicon in a

LOCOS structure. F1: Intrinsic film stress F2: Bending stress
F3: Field oxide growth F4: Thermal stress
Average compressive stress for different LOCOS
isolation structure
Edge region
along 111
•Stress increases as nitride thickness increases

: recess thickness increases
: as pad oxide thickness decreases
:as oxidation temperature decreases
Oxidation Simulation Results Using ATHENA
Oxidation simulation showing the effects of including stress effects

in oxidation .A 20nm SiO2 pad oxide is first grown and a 150nm Si3N4
layer is then deposited. A 90min 100C H2O oxidation was then
performed.
Left: No stress dependent parameter
Right: With stress dependent parameter
Pad oxide punchthrough and end-of-line
encroachment
SEM photograph of LOCOS structures after nitride removal

and pad oxide etch showing the silicon substrate (black
area) and the extent of the bird’s beak in the length and
width direction of the mask.
Advanced LOCOS techniques
To minimize the problems of the conventional LOCOS techniques

several advanced techniques have been developed. Schematic
representation of the POLY BUFFERED LOCOS isolation structure,
before and after field oxidation.
Advanced LOCOS Techniques
Schematic representation of nitride or poly spacer LOCOS (a)

and Nitride- clad (b) before field oxidation.
Side Wall Mask Isolation (SWAMI)
Sealed Nitride Plug Poly –Buffered
LOCOS (Sealed-NPPBL)
Sealed NPPBL With and Without Nitridation
Shallow Trench Isolation: Fabrication Sequence
• Poor gap fill (Key Hole)
• Anisotropic properties of SiO2
• Needs high T anneal to improve properties
• High T anneal increases stress.
•Excellent gap fill (no key hole)
•Isotropic excellent properties of SiO2
•No anneal needed
Chemical-Mechanical Polishing
(CMP) for Planarization
Effect of Post Thermal Processing
•Stress due to anneal

Compressive stress in Si mesa Vs Active area length
•Compressive stress in the Si mesa as a function of active area

length Lsi oxide thickness (5,10,15,20nm) and oxidation
temperature. The STI length LSio2 was 0.18um in all cases.
Compressive Stress Vs Active area & STI length
• Constant Oxide thickness of 10nm grown at 1000C

Effect of high temperature oxidation
• Higher temperature thermal oxidation reduces the stress

and gives more rounded corners. Both these effects
reduce leakage.

Isolation

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ISOLATION TECHNOLOGIES

• Technology to electrically isolate

1.Two neighbouring devices.

• Historically used for Bipolar

• Used in early days of MOS

• Main method used today in a variety of forms

• Cutting edge technology today

•The oxide is thinner on

Recessed LOCOS process in which the silicon is etched prior to

• Illustration of the difference in shape and topography in a semi and fully

Recessed LOCOS Isolation Structure

Parameters describing the bird”s beak in a semi –recessed

The Kooi or White Ribbon effect is due to the nitridation of the Si

Relative amount of field oxide thinning for a conventional

Schematic representation of forces acting on the silicon in a

•Stress increases as nitride thickness increases

Oxidation simulation showing the effects of including stress effects

SEM photograph of LOCOS structures after nitride removal

To minimize the problems of the conventional LOCOS techniques

Schematic representation of nitride or poly spacer LOCOS (a)

•Stress due to anneal

•Compressive stress in the Si mesa as a function of active area

• Constant Oxide thickness of 10nm grown at 1000C

• Higher temperature thermal oxidation reduces the stress

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