Microprocessor Systems and

Interfacing
EEE 342

Dr. Naeem Shehzad

Objectives

 Operation of basic I/O operations

 Decode 8 and 16 bit addresses for enabling I/O

ports

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Motivation

 Microprocessor is great at doing calculations

but is not effective if it cannot be interfaced
with outer world

 Hence basic I/O operations and relevant

instructions must be observed

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Isolated vs. Memory Mapped
 There are two different methods to interface I/O to
the microprocessor:
 Isolated I/O: uses the dedicated I/O instructions
(IN, OUT and INS, OUTS) and has its own address
space for I/O ports (0000H-FFFFH)- isolated from
the memory address space
 The addresses for isolated I/O devices are called ports and
are separate from memory
 Memory mapped I/O: uses memory reference
instructions , e.g. MOV, and a region of the memory
address map. So address space is shared between
memory and I/O (used by only one of them)
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Isolated vs. Memory Mapped
 Both techniques can be used with Intel processors But
most Intel-based systems e.g. the PC, use isolated I/O

 Some other processors do not have dedicated I/O

instructions and therefore use only memory-mapped
I/O addressing, e.g. the PowerPC microprocessor
(Macintosh computers)

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 I/O Port specified
Memory and I/O address Memory:
Memory:
Maps for the 8086/8088 MOV
in DX, either
MOV explicitly or implicitly
I/O:
a. Isolated I/O I/O:
IN

Using dedicated I/O IN

64 K
instructions e.g. IN, OUT 00FF
00FF
I/O bytes

Port specified immediately

as a byte in the
I/O instruction
MOV
MOV
b. Memory-mapped I/O RangeRange
of memory addresses
of memory addresses
Using ordinary memory assigned for for
assigned I/OI/Otransfers
transfers
transfer instructions
e.g. MOV Memory
Memory

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 What is port?
 As with memory, I/O devices have I/O addresses
(addresses for the I/O port)

 Up to 64K I/O bytes can be addressed. 0000H-FFFFH

 Whenever data are transferred by using the IN or OUT

instructions, the I/O address, often called a port
number (or simply port), appears on the address bus.

 The external I/O interface decodes the port number in

the same manner that it decodes a memory address
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 I/O Address
 Two ways to specify an I/O port address:
- An 8-bit immediate (fixed) address (specified as a byte in the
instruction): e.g. IN AX, p8 ; Reads a word from port p8
0000H-00FFH (can only see the first 256 addresses)

- A 16-bit address located in register DX (can be easily varied): e.g.

OUT DX, AL; outputs the byte in AL to the port whose address is
in DX
0000H-FFFFH (up to 16K addresses).
i.e. high port addresses are accessible only
through DX addressing D
00FF
X
Immediate
Isolated I/O
 Advantage. Since the addresses for Isolated I/O
devices (ports) are separate from Memory, the user
can expand the memory to its full size without using
any of memory space for I/O devices.

 Disadvantage. Separate control signals for the I/O

space are developed (using and M/IO-bar and W/R-
bar ), which indicate an I/O read or an I/O write
operation

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 Memory Mapped I/O
 It uses any instruction that transfers data between the
microprocessor and memory. A memory-mapped I/O
device is treated as memory location in the memory
map.
 Advantage. The main advantage of memory-mapped I/O
is that any memory transfer instruction can be used to
access the I/O device.

 Disadvantage. The main disadvantage is that a portion

of the memory system is used as the I/O map. This
reduces the amount of memory available to applications.

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I/O Instructions
Two type of instructions are used

 IN & OUT for transfer of data between I/O and

Accumulator register (AL, AX, EAX)

 INS & OUTS for transfer string data between

memory and I/O device. These instructions
found in all microprocessor versions except
8088/8086

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IN & OUT I/O Instructions
 When we use 8 bit fixed port address, the address
appears on A7-A0 while A15-A8 remains 0. The A19-
A16 are undefined.
 For 16 bits the address A15-A0 appears on
address bus.

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IN & OUT I/O Instructions

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I/O Data widths
 As with memory, I/O ports are also organized as bytes
 A port can be 1, 2, or 4 bytes wide (not 8 bytes wide on
the Pentium)

00F3H
Port is 4 bytes wide

00F2H
EAXPort is 2 bytes wide
00F1H
AX Port is 1 byte wide
Port Address p8 00F0H LS byte AL
IN & OUT I/O Instructions
 OUT It (I/O Write): Copies the contents of the
accumulator out to an external I/O device

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 The PC I/O
The PC I/O space
Address Space
Processor communicates
with and controls these
peripherals through writing
into/reading from their
control registers accessed
as I/O locations 03FF
Must use 16-bit variable
I/O address in register DX

Reserved for use by

system components
and ISA bus 0100
00FF
On Board Devices

Can Use either:

- Fixed (immediate) 8-bit
I/O address in instruction, p8
- Variable 16-bit
I/O address in register DX
0000 0000 16
 The PC I/O space
 I/O space between ports 0000H and 03FFH is normally
reserved for the computer system and the ISA bus

 Modern components appear at I/O locations above

0400H. The I/O ports located at 0400H–FFFFH are
generally available for user applications, main-board
functions, and the PCI bus.

17
Basic input port( for I/O read)
 The basic input port connects an external set of
bits to the mP data bus whenever the mP executes
the correct IN instruction with the correct I/O
port address
 External device puts data on the mP data bus
 Must include a 3-state (Tri-State) buffer to
limit access to the processor data bus to the
duration of executing the I/O instruction only

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74LS244 Tri-state buffer
I0 O0

I1 O1

I2 O2

I3 O3
74LS244
I4 O4

I5 O5

I6 O6

I7 E1 E2 O7

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Tri-state buffer ?
 If the "enable" inputs signal is true, the tri-
state buffer behaves like a normal buffer.
 If the "enable“ or “control” input signal is
0, the tri-state buffer passes a high
impedance (or hi-Z) signal, which
effectively disconnects its output from the
circuit.

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Tri-state buffer ?

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Interfacing an Input Port
74LS244

D0 O0 I0

8088 Data Bus

. . .
. . .
. . .

8088 Address and Control Lines

A0 D7 07 I7
A1
E1 E2
A2
A3
A4
A5
A6
A7

RD’
WR’
IO/M’

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 Basic 8-bit Input Interface:
Fundamentals
Reads the status of 8 toggle
Switches (a byte read)
Pull-up
Resistors To mP
Gate

0 1
Toggle switches
Outputs:
3-state buffer
The SEL signal is generated (active low) Normally Hi-Z
By decoding: Unless device is
- The address for the I/O port Selected
- The
1/20/23I/O READ operation
(both G1 and G2
23
low
Basic Output port( for I/O read)
 The basic output port writes data from the mP
data bus to an output port whenever the mP
executes the correct OUT instruction with the
correct I/O port address
 Must latch the processor data put on the bus
during the I/O instruction to make it available
indefinitely for the port
 No need for 3-state (Tri-State) buffers as the data
bus is at the input side of the latch

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74LS374 8-bit parallel register
D0 O0

D1 O1

D2 O2

D3 O3
74LS374
D4 O4

D5 O5

D6 O6

D7 CLK OE O7

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Interfacing an Output Port
74LS374

D0 D0 O0

8088 Data Bus

. . .
. . .
. . .

8088 Address and Control Lines

A0 D7 D7 07
A1 CLK OE
A2
A3
A4
A5
A6
A7

RD’
WR’
IO/M’

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Basic 8-bit Output Interface:
Basic Output port( for I/O read)
Controls 8 LEDs (1: OFF, 0: ON)

Data is latched and remains here until the next

OUT instruction to this port is executed
The SEL is generated (for + ive edge triggering) by decoding:
- The address for the I/O port
- The I/O WRITE operation
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Interfacing Bidirectional I/O Port

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I/O Port interfacing
 Most embedded systems use only fixed I/O addressing:
- i.e. Only the least significant eight address bits A7-A0
are decoded. Limits number of I/O ports to 256 (enough)

 PC systems used fixed/variable I/O addressing:

 All 16-bits of the I/O address A15-A0 are decoded,
allowing the use of up to 64K ports

 Decoding is simpler than for memory- smaller # of

address lines

 Isolated I/O transfers are activated using (depending

on processor and mode): IO/#M = 1, M/#IO = 0,
#IORC, #IOWC, #RD, #WR, W/#R

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 Address Decoding for 8 I/O Ports: F0 to F7
Using a Decoder IC for the 8088 using 8-bit I/O address
Decoder O/Ps
LS part Decoder I/Ps
X
X
(Select port X
X
on decoder) X
X

0
1 To ‘Enable’
1
0 Inputs on the
8 I/O ports
S part
nable decoder)
1
1 3-to-8 A7 …....A0
1
1
1 Decode 11110 000 = F0 1st
1 r 11110 001 = F1 2nd
Address from mP …………………….
11110 111 = F7 7th
Note: #IO/M decoding should be added

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Hand Shaking
 The parallel port is an example of interfacing
slow devices, e.g. a printer, to the processor

 A printer can print say 100’s of characters per

sec (CPS), but the processor can output as
many as 1000’s of CPS

 To achieve ‘flow control’ and proper operation

we use a technique called handshaking

 Handshaking regulates the flow of data from the

processor to a slower peripheral device to
ensure correct operation
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 Parallel Port
- Computer (parallel port) has
a 25-pin DB25 connector

- Printer has a 36-pin Centronics

Printer side
connector
Computer side

Strobe Data
nto Printer

Data

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Parallel Port
Processor polls
‘Busy’ to see if
If (BUSY == 0) (printer not busy), so processor can send
the data for next character
Else
Poll again

The process of interrogating printer or any other

asynchronous device is called handshaking

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