8051 MICROCONTOLLER

Prepared by
A. Gokul Raj, M.E.,
Assistant Professor,
Department of Electrical and Electronics Engineering,
Muthayammal Engineering College (Autonomous),
Rasipuram – 637 408.
 Unit – II 8051 Microcontroller
Microcontroller
1. 8051Microcontroller is an 8-bit microcontroller created in 1981. It is most popular and
commonly used microcontroller.
2. An 8-bit microcontroller has an 8-bit data bus and 16- bit address bus.
3. It is an integrated chip designed under very large scale integration techniques .
4. It consist of a processor with other peripheral devices like memory, I/O ports and timer.
A microcontroller contain all these component in a single chip
5. A microcontroller does not require much additional interfacing ICs for operation and it
functions
6. A microcontroller clock speed is limited only to a few tens of MHz
Classification of microcontrollers
Intel 4004 4 bit (2300 PMOS trans, 108 kHz) 1971

Intel 8048 8 bit 1976

Intel 8031 8 bit (ROM-less) .

Intel 8051 8 bit (Mask ROM) 1980

Microchip PIC16C64 8 bit 1985

Motorola 68HC11 8 bit (on chip ADC) .

Intel 80C196 16 bit 1982

Atmel AT89C51 8 bit (Flash memory) .

Microchip PIC 16F877 8 bit (Flash memory + ADC) .

Various features of 8051 microcontroller
• 8-bit CPU
• 16-bit Program Counter
• 8-bit Processor Status Word (PSW)
• 8-bit Stack Pointer
• Internal RAM of 128bytes
• Special Function Registers (SFRs) of 128 bytes
• 32 I/O pins arranged as four 8-bit ports (P0 - P3)
• Two 16-bit timer/counters : T0 and T1
• Two external and three internal vectored interrupts
• One full duplex serial I/O
ARCHITECTURE OF 8051 MICROCONTROLLER:
ALU:
• It is 8 bit unit
• It performs arithmetic operation as addition, subtraction, multiplication,
division, increment and decrement.
• It performs logical operations like AND, OR and EX-OR. It manipulates 8 bit and 16 bit
data
• It calculates address of jump locations in relative branch instruction.
• It performs compare, rotate and compliment operations
• 8051 micro controller contains 34 general purpose registers or working registers
Accumulator(A-reg):
It is 8 bit register
It is bit and byte accessible
Result of arithmetic & logic operations performed by ALU is accumulated by this register.
Therefore it is called accumulator register
It is used to store 8 bit data and to hold one of operand of ALU units during arithmetical and
logical operations
Most of the instructions are carried out on accumulator data.
B-register
It is special 8 bit math register. It is bit and byte accessible.
It is used in conjunction with A register as I/P operand for ALU. It is used as general
purpose register to store 8 bit data.
PSW
It is 8 bit register.
Its address is D0H and It is bit and byte accessible.
It has 4 conditional flags or math flags which sets or resets according to condition of result.
It has 3 control flags, by setting or resetting bit required operation or function
can be achieved.
FLAG:
Carry Flag(CY): During addition and subtraction any carry or borrow is generated then
carry flag is set otherwise carry flag resets.
It is used in arithmetic, logical, jump, rotate and Boolean operations.
Auxiliary carry flag(AC): If during addition and subtraction any carry or borrow is
generated from lower 4 bit to higher 4 bit then AC sets else it resets.
It is used in BCD arithmetic operations.
Overflow flag(OV): If in signed arithmetic operations result exceeds more than 7 bit than
OV flag sets else resets.
It is used in signed arithmetic operations only.
Parity flag(P): If in result, even no. Of ones "1" are present than it is called even parity
and
parity flag sets.
In result odd no. Of ones "1"are present than it is called odd parity and parity flag resets.
CONTROL FLAGS:
FO: It is user defined flag. The user defines the function of this flag. The user can set test
and clear this flag through software.
RS1 and RS0: These flags are used to select bank of register by resetting those flags
Program counter (PC):
 The Program Counter (PC) is a 2-byte address which tells the 8051 where the next
instruction to execute is found in memory.
It is used to hold 16 bit address of internal RAM, external RAM or external ROM
locations.
It is important to note that PC isn’t always incremented by one and never decremented.
Data pointer register (DTPR): It is a 16-bit register used to hold address of external or
internal RAM where data is stored or result is to be stored.
It is used to store 16 bit data.
Each register can be used as general purpose register to store 8 bit data and can also be used
as memory location.
DPTR does not have single internal address.
It functions as Base register in base relative addressing mode and in-direct jump.
Stack pointer (SP):
It is 8-bit register. It is byte addressable.
Its address is 81H.
It is used to hold the internal RAM memory location addresses which are used as stack
memory.
When the data is to be placed on stack by push instruction, the content of stack pointer is
incremented by 1, and when data is retrieved from stack, content of stack of stack pointer is
decremented by 1.
Special function Registers(SFR):
The 8051 microcontroller has 11 SFR divided in 4 groups:
Timer/Counter register
8051 microcontroller has 2-16 bit Timer/counter registers called Timer-reg-T0 And
Timer/counter Reg-T1.
Each register is 16 bit register divide into lower and higher byte register
These register are used to hold initial no. of count.
All of the 4 register are byte addressable.
Timer control register
8051 microcontroller has two 8-bit timer control register i.e. TMOD and TCON register.
TMOD Register:
It is 8-bit register.
Its address is 89H.
It is byte addressable.
It used to select mode and control operation of time by writing control word.
TCON register:
It is 8-bit register. Its address is 88H.
It is byte addressable.
Its MSB 4- bit are used to control operation of timer/ counter and LSB 4-bit are used for
external interrupt control.
Serial data register:
8051 micro controller has 2 serial data register viz. SBUF and SCON.
Serial buffer register (SBUF):
It is 8-bit register.
It is byte addressable .
Its address is 99H.
It is used to hold data which is to be transferred serially.
Serial control register (SCON):
It is 8-bit register.
It is bit/byte addressable.
Its address is 98H.
The 8-bit loaded into this register controls the operation of serial communication.
Interrupt register: 8051 µC has 2 8-bit interrupt register.
Interrupt enable register (IE): It is 8-bit register.
It is bit/byte addressable.
Its address is A8H.
It is used to enable and disable function of interrupt.
 Interrupt priority register (IP):
It is 8-bit register.
It is bit/byte addressable.
Its address is B8H.
It is used to select low or high level priority of each individual interrupts.
Power control register (PCON):
It is 8-bit register.
It is byte addressable .
Its address is 87H.
Its bits are used to control mode of power saving circuit, either idle or power down mode and
also one bit is used to modify baud rate of serial communication.
PIN DIAGRAM
Pinout Description
Pins 1-8 PORT 1. Each of these pins can be configured as an input or an output.
Pin 9 RESET. A logic one on this pin disables the microcontroller and clears the
contents of most registers. In other words, the positive voltage on this pin
resets the microcontroller. By applying logic zero to this pin, the program
starts execution from the beginning.
Pins10-17 PORT 3. Similar to port 1, each of these pins can serve as general input or
output. Besides, all of them have alternative functions

Pin 10 RXD. Serial asynchronous communication input or Serial synchronous

communication output.

Pin 11 TXD. Serial asynchronous communication output or Serial

synchronous communication clock output.
Pin 12 INT0.External Interrupt 0 input
Pin 13 INT1. External Interrupt 1 input
Pin 14 T0. Counter 0 clock input
Pin 15 T1. Counter 1 clock input
Pin 16 WR. Write to external (additional) RAM
Pin 17 RD. Read from external RAM
Pin 18, 19 XTAL2, XTAL1. Internal oscillator input and output. A quartz crystal which
specifies operating frequency is usually connected to these pins.
Pin 20 GND. Ground.
Pin 21-28 Port 2. If there is no intention to use external memory then these port pins are
configured as general inputs/outputs. In case external memory is used, the
higher address byte, i.e. addresses A8-A15 will appear on this port. Even
though memory with capacity of 64Kb is not used, which means that not all
eight port bits are used for its addressing, the rest of them are not available as
inputs/outputs.
Pin 29 PSEN. If external ROM is used for storing program then a logic zero (0)
appears on it every time the microcontroller reads a byte from memory.
Pin 31 EA. By applying logic zero to this pin, P2 and P3 are used for data and
address transmission with no regard to whether there is internal memory or
not. It means that even there is a program written to the microcontroller, it
will not be executed. Instead, the program written to external ROM will be
executed. By applying logic one to the EA pin, the microcontroller will use
both memories, first internal then external (if exists).
Pin 32-39 PORT 0. Similar to P2, if external memory is not used, these pins can be used as
general inputs/outputs. Otherwise, P0 is configured as address output (A0-A7)
when the ALE pin is driven high (1) or as data output (Data Bus) when the ALE
pin is driven low (0).
Pin 40 VCC. +5V power supply.
IO Port Usage in 8051
The four 8-bit I/O ports P0, P1, P2 and P3 each uses 8 pins.
All the ports upon RESET are configured as input, ready to be used as input ports.
When the first 0 is written to a port, it becomes an output port.
To reconfigure it as an input, 1 must be sent to the port.
To use any of these ports as an input port, it must be programmed.
It can be used for input or output, each pin must be connected externally to a 10K ohm pull-
up resistor.
This is due to the fact that P0 is an open drain, unlike P1, P2, and P3.
Open drain is a term used for MOS chips in the same way that open collector is used for
TTL chips.
Port 0 with Pull up registers
The following code will continuously send out to port 0 the alternating value 55H and AAH
BACK: MOV A,#55H
• MOV P0,A
• ACALL DELAY
• MOV A,#0AAH
• MOV P0,A
• ACALL DELAY
• SJMP BACK
• Port 0 as input
• In order to make port 0 an input, the port must be programmed by writing 1
to all the bits.
Port 0 is configured first as an input port by writing 1s to it, and then data is received from
that port and sent to P1
• MOV A,#0FFH ;A=FF hex
• MOV P0,A ;make P0 an i/p port ;by writing it all 1s
• BACK: MOV A,P0 ;get data from P0
• MOV P1,A ;send it to port 1 SJMP BACK
Dual role of Port 0
Port 0 is also designated as AD0-AD7, allowing it to be used for both address and data.
When connecting an 8051/31 to an external memory, port 0 provides both address and
data.
Port 1 can be used as input or output
In contrast to port 0, this port does not need any pull-up resistors since it
already has pull-up resistors internally.
Upon reset, port 1 is configured as an input port.
The following code will continuously send out to port 0 the alternating value 55H and AAH
MOV A,#55H
• BACK: MOV P1,A
• ACALL DELAY CPL A
• SJMP BACK
To make port 1 an input port, it must be programmed as such by writing 1to all its bits.
Port 1 is configured first as an input port by writing 1s to it, then data is received from that
port and saved in R7 and R5
• MOV A,#0FFH ;A=FF hex
• MOV P1,A ;make P1 an input port ;by writing it all 1s
• MOV A,P1 ;get data from P1
• MOV R7,A ;save it to in reg R7
• ACALL DELAY ;wait
• MOV A,P1 ;another data from P1
• MOV R5,A ;save it to in reg R5
Port 2 can be used as input or output
• Just like P1, port 2 does not need any pullup resistors since it already has pull-up
resistors internally.
• Upon reset, port 2 is configured as an input port.
• To make port 2 an input port, it must be programmed as such by writing 1 to all its bits.
• In many 8051-based systems, P2 is used as simple I/O.
• In 8031-based systems, port 2 must be used along with P0 to provide the 16-bit address
for the external memory.
• Port 2 is also designated as A8 – A15, indicating its dual function.
• Port 0 provides the lower 8 bits via A0 – A7.
Port 3 can be used as input or output
Port 3 does not need any pull-up resistors. Port 3 is configured as an input port upon reset.
Port 3 has the additional function of providing some extremely important signals

Port 3 alternate functions

INSTRUCTION SET.
Instruction Timings
T-state, Machine cycle and Instruction cycle are terms used in instruction
timings.
T-state is defined as one subdivision of the operation performed in one clock
period. The terms 'T- state' and 'clock period' are often used synonymously
Machine cycle is defined as 12 oscillator periods. A machine cycle consists of
six states and each state lasts for two oscillator periods. An instruction takes
one to four machine cycles to execute an instruction.
Instruction cycle is defined as the time required for completing the execution
of an instruction. The 8051 instruction cycle consists of one to four machine
cycles
8051 Instructions
The instructions of 8051 can be broadly classified under the following headings.
• Data transfer instructions
• Arithmetic instructions
• Logical instructions
• Branch instructions
• Subroutine instructions
• Bit manipulation instructions
Data transfer instructions.
In this group, the instructions perform data transfer operations of the following types.
Move the contents of a register Rn to A
• MOV A,R2
• MOV A,R7
Move the contents of a register A to Rn
• MOV R4,A
• MOV R1,A
 Move an immediate 8 bit data to register A or to Rn or to a memory location(direct
or indirect)
MOV A, #45H
MOV R6, #51H
Move the contents of a memory location to A or A to a memory location using direct and
indirect addressing
MOV A, 65H
MOV 45H, A
Move the contents of a memory location to Rn or Rn to a memory location using direct
addressing
MOV R3, 65H
MOV 45H, R2
Move the contents of memory location to another memory location using direct and
indirect addressing
MOV 47H, 65H
Push and Pop instructions
MOV R6, #25H
MOV R1, #12H
PUSH 6 [SP]=08 [08]=[06]=25H //CONTENT OF 08 IS 25H
PUSH 1 [SP]=09 [09]=[01]=12H //CONTENT OF 09 IS 12H
PUSH 4 [SP]=0A [0A]=[04]=F3H //CONTENT OF 0A IS F3H
Exchange instructions
The content of source ie., register, direct memory or indirect memory will be exchanged
with the contents of destination ie., accumulator.
XCH A,R3
XCH A,@R1
XCH A,54h
Arithmetic instructions.
The 8051 can perform addition, subtraction. Multiplication and division
operations on 8 bit numbers.
Addition
In this group, we have instructions to
Add the contents of A with immediate data with or without carry.
ADD A, #45H
Add the contents of A with register Rn with or without carry.
ADD A, R5
ADDC A, R2
Add the contents of A with contents of memory with or without carry using direct and
indirect addressing
ADD A, 51H
ADDC A, 75H
Subtraction
In this group, we have instructions to
Subtract the contents of A with immediate data with or without carry.
SUBB A, #45H
Subtract the contents of A with register Rn with or without carry.
SUBB A, R5
SUBB A, R2
Subtract the contents of A with contents of memory with or without carry using direct
and indirect addressing
SUBB A, 51H
SUBB A, 75H
Multiplication
MUL AB. This instruction multiplies two 8 bit unsigned numbers which are stored in A and
B register. After multiplication the lower byte of the result will be stored in accumulator
and higher byte of result will be stored in B register.
Eg. MOV A,#45H ; [A]=45H
MOV B,#0F5H ;[B]=F5H
MUL AB ;[A] x [B] = 45 x F5 = 4209
;[A]=09H, [B]=42H
DIV AB. This instruction divides the 8 bit unsigned number which is stored in A by
the 8 bit unsigned number which is stored in B register. After division the result will
be stored in accumulator and remainder will be stored in B register.
• Eg.MOV A,#45H ;[A]=0E8H
• MOV B,#0F5H ;[B]=1BH
• DIV AB ;[A] / [B] = E8 /1B = 08 H with remainder 10H
;[A] = 08H, [B]=10H
DA A (Decimal Adjust After Addition).
When two BCD numbers are added, the answer is a non-BCD number. To get the result in
BCD, we use DA A instruction after the addition
Eg 1: MOV A,#23H
MOV R1,#55H
ADD A,R1 // [A]=78
DA A // [A]=78 no changes in the accumulator after da a
 Eg 2: MOV A,#53H
MOV R1,#58H
ADD A,R1 // [A]=ABh
DA A // [A]=11, C=1 . ANSWER IS 111. Accumulator data is changed after
DA A
Increment
Increments the operand by one.
INC increments the value of source by 1
If the initial value of register is FFh, incrementing the value will cause it to reset
to 0.
Decrement
Decrements the operand by one.
DEC decrements the value of source by 1. If the initial value of is 0,
decrementing the value will cause it to reset to FFh.
Logical Instructions
Logical AND
ANL destination, source:
ANL does a bitwise "AND" operation between source and destination, leaving
the resulting value in destination
The value in source is not affected
"AND" instruction logically AND the bits of source and destination.
ANL A,#DATA
ANL A, Rn
Logical OR
ORL destination, source
ORL does a bitwise "OR" operation between source and destination, leaving
the resulting value in destination.
The value in source is not affected. " OR " instruction logically OR the bits of
source and destination.
ORL A,#DATA
ORL A, Rn
Logical Ex-OR
XRL destination, source
XRL does a bitwise "EX-OR" operation between source and destination,
leaving the resulting value in destination.
The value in source is not affected. " XRL " instruction logically EX-OR the
bits of source and destination.
XRL A,#DATA
XRL A,Rn
Rotate Instructions RR A
This instruction is rotate right the accumulator.
Each bit is shifted one location to the right, with bit 0 going to bit 7.

RL A
Rotate left the accumulator. Each bit is shifted one location to the left, with bit
7 going to bit 0
RRC A
Rotate right through the carry.
Each bit is shifted one location to the right, with bit 0 going into the carry bit in
the PSW, while the carry was at goes into bit 7

RLC A
Rotate left through the carry. Each bit is shifted one location to the left, with bit
7 going into the carry bit in the PSW, while the carry goes into bit 0.
Branch (JUMP) Instructions
Jump and Call Program Range
There are 3 types of jump instructions. They are:-
• Relative Jump
• Short Absolute Jump
• Long Absolute Jump
Relative Jump
Jump that replaces the PC (program counter) content with a new address that is
greater than or less than is called a relative jump.
The advantages of the relative jump are
Only 1 byte of jump address needs to be specified in the 2's complement form
• Specifying only one byte reduces the size of the instruction and speeds up
program execution.
• The program with relative jumps can be relocated without reassembling to
generate absolute jump addresses.
Instructions that use Relative Jump
SJMP <relative address>; this is unconditional jump
The remaining relative jumps are conditional jumps
• JC <relative address>
• JNC <relative address>
• JB bit, <relative address>
• JNB bit, <relative address>
• JBC bit, <relative address>
• CJNE <destination byte>, <source byte>, <relative address>
• DJNZ <byte>, <relative address>
• JZ <relative address>
• JNZ <relative address>
Short Absolute Jump
In this case only 11bits of the absolute jump address are needed.
In 8051, 64 Kbyte of program memory space is divided into 32 pages of 2
kbyte each. The instruction length becomes 2 bytes.
Long Absolute Jump/Call
The entire program memory from 0000H to FFFFH use long absolute jump.
The absolute address has to be specified in the op-code, the instruction length
is 3 bytes
Another classification of jump instructions is
• Unconditional Jump
• Conditional Jump
The unconditional jump is a jump in which control is transferred
unconditionally to the target location.
LJMP (long jump). This is a 3-byte instruction.
First byte is the op-code and second and third bytes represent the 16-bit target
Address which is any memory location from 0000 to FFFFH.
AJMP(Absolute jump)this causes unconditional branch to the indicated
address, by loading the 11 bit address to 0 -10 bits of the program counter.
SJMP (short jump). This is a 2-byte instruction. First byte is the op-code and
second byte is the relative target address, 00 to FFH
To calculate the target address of a short jump, the second byte is added to the
PC value
Conditional Jump instructions.
JBC Jump if bit ＝ 1 and clear bit JNB Jump if bit ＝ 0
JB Jump if bit ＝ 1
JNC Jump if CY ＝ 0
JC Jump if CY ＝ 1
CJNE reg,#data Jump if byte ≠ #data
CJNE A,byte Jump if A ≠ byte
DJNZ Decrement and Jump if A ≠ 0
JNZ Jump if A ≠ 0
JZ Jump if A ＝ 0
All conditional jumps are short jumps
Bit level jump instructions:
Bit level JUMP instructions will check the conditions of the bit and if condition
is true, it jumps to the address specified in the instruction. All the bit jumps are
relative jumps.
Subroutine CALL And RETURN Instructions
Subroutines are handled by CALL and RET instructions
There are two types of CALL instructions
LCALL address(16 bit)
This is long call instruction which unconditionally calls the subroutine located
at the indicated 16 bit address.
This is a 3 byte instruction.
ACALL address(11 bit)
This is absolute call instruction which unconditionally calls the subroutine
located at the indicated 11 bit address. This is a 2 byte instruction.
RET instruction
RET instruction pops top two contents from the stack and load it to PC.
Bit manipulation instructions.
8051 has 128 bit addressable memory.
Bit addressable SFRs and bit addressable PORT pins.
It is possible to perform following bit wise operations for these bit addressable
locations.
LOGICAL AND
ANL C,BIT(BIT ADDRESS)
ANL C, /BIT;
LOGICAL OR
• ORL C,BIT(BIT ADDRESS)
• ORL C, /BIT
CLR bit
• CLR bit
• CLR C
CPL bit
• CPL bit
• CPL C
 ADDRESSING MODES
Various methods of accessing the data are called addressing modes. 8051
addressing modes are classified as follows.
Immediate addressing
Register addressing.
Direct addressing.
Indirect addressing.
Indexed addressing
Relative addressing.
Absolute addressing.
Long addressing.
Bit inherent addressing.
Bit direct addressing.
Immediate addressing.
In this addressing mode the data is provided as a part of instruction itself. In
other words data immediately follows the instruction.
Eg. MOV A,#30H
ADD A, #83
Register addressing.
In this addressing mode the register will hold the data. One of the eight
general registers (R0 to R7) can be used and specified as the operand.
MOV A,R0
ADD A,R6
Direct addressing
There are two ways to access the internal memory. Using direct address and
indirect address.
Using direct addressing mode we can not only address the internal memory but
SFRs also.
In direct addressing, an 8 bit internal data memory address is specified as part
of the instruction
In this addressing mode, data is obtained directly from the memory.
MOV A,60h
ADD A,30h
Indirect addressing
The indirect addressing mode uses a register to hold the actual address that
will be used in data movement.
Registers R0 and R1 and DPTR are the only registers that can be used as data
pointers.
Indirect addressing cannot be used to refer to SFR registers.
Both R0 and R1 can hold 8 bit address
MOV A,R0
ADD A,R1
Indexed addressing.
In indexed addressing, either the program counter (PC), or the data pointer
(DTPR)—is used to hold the base address, and the A is used to hold the offset
address
Indexed addressing is used with JMP or MOVC instructions
MOVC A, @A+DPTR // copies the contents of memory location pointed by
the sum of the accumulator A and the DPTR into accumulator A.
MOVC A, @A+PC // copies the contents of memory location pointed by
the sum of the accumulator A and the program counter into accumulator A.
Relative Addressing
Relative addressing is used only with conditional jump instructions.
The relative address is an 8 bit signed number, which is automatically added to
the PC to make the address of the next instruction.
The advantage of relative addressing is that the program code is easy to
relocate and the address is relative to position in the memory.
SJMP
LOOP1 JC
BACK
Absolute addressing
Absolute addressing is used only by the AJMP (Absolute Jump) and ACALL
(Absolute Call) instructions.
These are 2 bytes instructions
The absolute addressing mode specifies the lowest 11 bit of the memory
address as part of the instruction.
AJMP LOOP1
ACALL
LOOP2
Long Addressing
The long addressing mode is used with the instructions LJMP and LCALL
These are 3 byte instructions. The address specifies a full 16 bit destination
address so that a jump or a call can be made to a location within a 64 Kbyte
code memory space.
Eg.LJMP FINISH
LCALL
DELAY
Bit Inherent Addressing
In this addressing, the address of the flag which contains the operand, is
implied in the opcode of the instruction.
Eg. CLR C ;
Bit Direct Addressing
In this addressing mode the direct address of the bit is specified in the
instruction.
The RAM space 20H to 2FH and most of the special function registers are bit
addressable.
Bit address values are between 00H to 7FH.
Eg. CLR 07h ; Clears the bit 7 of 20h RAM space
SETB 07H ; Sets the bit 7 of 20H RAM space.
 Timing diagram
The timing diagram provides the information about the various condition of the
signal in which the machine cycle is executed
Machine cycle
It consist of a sequence of 6 states numbered S1 through S6.Each state time
lasts for two oscillator period.
The machine cycle take 12 oscillator period or 1microsecond if the oscillator
frequency is 12MHz.
Each phase divided into Phase1 half and a Phase 2 half.
OSC S1 S2 S3 S4 S5 S6 S1 S2 S3 S4 S5 S6 S1 S2 S3 S4

ALE
Read next opcode
Read opcode Read next opcode
S1 S2 S3 S4 S5 S6
1 byte 1 cycle instruction ex INC A
S1 S2 S3 S4 S5 S6
2 byte 1 cycle instruction ex ADD A
S1 S2 S3 S4 S5 S6 S1 S2 S3 S4 S5 S6
1 byte 2 cycle instruction ex INC DPTR
Normally two programs are fetch are generated during each machine cycle ,
even if the instruction is executed.
If the instruction is executed it does not need more code bytes.
CPU simply the extra fetch and the program counter not incremented
Execution of one cycle instruction begins during State 1 of machine cycle
when the opcode is latched into the instruction register
The second fetch occur during S4 of the same machine cycle
Execution is complete at the end of state 6 of this machine cycle
The MOVX instruction take two machine cycle to execute.
No program fetch is generated during the second cycle of a MOVX instruction
To fetch or execute the sequence of MOVX instruction
To fetch or execute the sequence are same whether the program memory is
internal or external to the chip
Execution time does not depend on the whether the program memory is
internal or external
S1 S2 S3 S4 S5 S6 S1 S2 S3 S4 S5 S6
ALE
PSEN

RD
P2

WITHOUT A MOVX
The signals and timing involved in program fetch when memory program is
external
If program memory is external then the program memory read
PSEN is normally activated twice per machine cycle
S1 S2 S3 S4 S5 S6 S1 S2 S3 S4 S5 S6
ALE
PSEN

RD
P2

WITH A MOVX
If an access to external data memory two PSEN is skipped because the
address and data bus is mainly used for data memory access
Data memory bus cycle takes twice as much time as Program memory bus
cycle
ALE is used to latch the low address byte from P0 into the address latch
PSEN is not activated and program address are not emitted
ALE continuous to activate twice per machine cycle and is available as an
clock output signal
One ALE skipped during the execution of the MOVX instruction