MODULE I Architecture of Microcontrollers

1.1.1 To introduce 8051 micro controller.

A microcontroller is a computer with most of the necessary support chips onboard. A
microcontroller may take an input from the device it is controlling and controls the device by
sending signals to different components in the device. A microcontroller is often small and
low cost. The components may be chosen to minimize size and to be as inexpensive as
possible

1.1.2 To describe feature of 8051

Eight bit CPU

On chip clock oscillator

4Kbytes of internal program memory (code memory) [ROM]

128 bytes of internal data memory [RAM]

64 Kbytes of external program memory address space.

64 Kbytes of external data memory address space.

32 bi directional I/O lines (can be used as four 8 bit ports or 32 individually addressable I/O
lines)

Two 16 Bit Timer/Counter :T0, T1

Full Duplex serial data receiver/transmitter

Four Register banks with 8 registers in each bank.

Sixteen bit Program counter (PC) and a data pointer (DPTR)

8 Bit Program Status Word (PSW)

8 Bit Stack Pointer

Five vector interrupt structure (RESET not considered as an interrupt.)

8051 CPU consists of 8 bit ALU with associated registers like accumulator ‘A’ , B register,
PSW, SP, 16 bit program counter, stack pointer.

ALU can perform arithmetic and logic functions on 8 bit variables.

8051 has 128 bytes of internal RAM which is divided into

o- Working registers [00 – 1F]

o-- Bit addressable memory area [20 – 2F]

o- General purpose memory area (Scratch pad memory) [30-7F]

1.1.3 To describe block diagram of 8051.

The 8051 Microcontroller is an 8 – bit Microcontroller i.e. it can read, write and process 8 –
bit Data. There are a bunch of manufacturers like Atmel, NXP, TI, who manufacture their own
versions of 8051 Microcontroller.

8051 has 4 K Bytes of internal ROM. The address space is from 0000 to 0FFFh. If the program
size is more than 4 K Bytes 8051 will fetch the code automatically from external memory.

1.1.4 To explain register structure of 8051

Accumulator is an 8 bit register widely used for all arithmetic and logical operations.
Accumulator is also used to transfer data between external memory. B register is used along
with Accumulator for multiplication and division. A and B registers together is also called
MATH registers.

PSW (Program Status Word). This is an 8 bit register which contains the arithmetic status of
ALU and the bank select bits of register banks .
CY - carry flag

AC - auxiliary carry flag

F0 - available to the user for general purpose

RS1,RS0 - register bank select bits

OV - overflow

P - parity

Stack Pointer (SP) – it contains the address of the data item on the top of the stack. Stack
may reside anywhere on the internal RAM. On reset, SP is initialized to 07 so that the default
stack will start from address 08 onwards.

Data Pointer (DPTR) – DPH (Data pointer higher byte), DPL (Data pointer lower byte). This
is a 16 bit register which is used to furnish address information for internal and external
program memory and for external data memory.

Program Counter (PC) – 16 bit PC contains the address of next instruction to be executed.
On reset PC will set to 0000. After fetching every instruction PC will increment by one.

1.1.7 To describe internal & external memory of 8051.

Register Banks: 00h to 1Fh. The 8051 uses 8 general-purpose registers R0 through R7
(R0, R1, R2, R3, R4, R5, R6, and R7). There are four such register banks. Selection of
register bank can be done through RS1,RS0 bits of PSW. On reset, the default Register
Bank 0 will be selected.
Bit Addressable RAM: 20h to 2Fh . The 8051 supports a special feature which allows
access to bit variables. This is where individual memory bits in Internal RAM can be
set or cleared. In all there are 128 bits numbered 00h to 7Fh. Being bit variables any
one variable can have a value 0 or 1. A bit variable can be set with a command such as
SETB and cleared with a command such as CLR.
Example instructions are:
SETB 25h ; sets the bit 25h (becomes 1)
CLR 25h ; clears bit 25h (becomes 0)
Note, bit 25h is actually bit 5 of Internal RAM location 24h.
The Bit Addressable area of the RAM is just 16 bytes of Internal RAM located between
20h and 2Fh.
General Purpose RAM: 30h to 7Fh. Even if 80 bytes of Internal RAM memory are
available for general-purpose data storage, user should take care while using the
memory location from 00 -2Fh since these locations are also the default register space,
stack space, and bit addressable space. It is a good practice to use general purpose
memory from 30 – 7Fh. The general purpose RAM can be accessed using direct or
indirect addressing modes.
1.1.8 To describe pin details of 8051.

Pins 1-8 --- PORT 1. Each of these pins can be configured as an input or an output

Pin 9 --RESET. A logic one on this pin disables the microcontroller and clears the contents of
most registers. In other words, the positive voltage on this pin resets the microcontroller. By
applying logic zero to this pin, the program starts execution from the beginning.

Pins10-17--PORT 3. Similar to port 1, each of these pins can serve as general input or output.

Pin 10--RXD. Serial asynchronous communication input or Serial synchronous communication

output.

Pin 11--TXD. Serial asynchronous communication output or Serial synchronous

communication clock output.

Pin 12 INT0.External Interrupt 0 input

Pin 13 INT1. External Interrupt 1 input

Pin 14 -T0. Counter 0 clock input

Pin 15- T1. Counter 1 clock input

Pin 16-WR. Write to external (additional) RAM

Pin 17-RD. Read from external RAM

Pin 18, 19-XTAL2, XTAL1. Internal oscillator input and output. A quartz crystal which specifies
operating frequency is usually connected to these pins.

Pin 20-GND. Ground.

Pin 21-28-Port 2. If there is no intention to use external memory then these port pins are
configured as general inputs/outputs. In case external memory is used, the higher address
byte, i.e. addresses A8-A15 will appear on this port. Even though memory with capacity of
64Kb is not used, which means that not all eight port bits are used for its addressing, the rest
of them are not available as inputs/outputs.

Pin 29-PSEN. If external ROM is used for storing program then a logic zero (0) appears on it
every time the microcontroller reads a byte from memory.

Pin 30-ALE. Prior to reading from external memory, the microcontroller puts the lower
address byte (A0-A7) on P0 and activates the ALE output. After receiving signal from the ALE
pin, the external latch latches the state of P0 and uses it as a memory chip address.
Immediately after that, the ALE pin is returned its previous logic state and P0 is now used as
a Data Bus.

Pin 31-EA. By applying logic zero to this pin, P2 and P3 are used for data and address
transmission with no regard to whether there is internal memory or not. It means that even
there is a program written to the microcontroller, it will not be executed. Instead, the program
written to external ROM will be executed. By applying logic one to the EA pin, the
microcontroller will use both memories, first internal then external (if exists).

Pin 32-39-PORT 0. Similar to P2, if external memory is not used, these pins can be used as
general inputs/outputs. Otherwise, P0 is configured as address output (A0-A7) when the ALE
pin is driven high (1) or as data output (Data Bus) when the ALE pin is driven low (0).

Pin 40-VCC. +5V power supply.

1.2.1 To explain counters& timers in 8051 and associated registers-

TMOD,TCON.
TCON REGISTER

1.2.2 To describe modes of operation of timers / counters.

TIMER MODES
Timers can operate in four different modes. They are as follows

Timer Mode-0: In this mode, the timer is used as a 13-bit UP counter as follows.
The lower 5 bits of TLX and 8 bits of THX are used for the 13 bit count.Upper 3 bits of TLX are
ignored. When the counter rolls over from all 0's to all 1's, TFX flag is set and an interrupt is
generated. The input pulse is obtained from the previous stage. If TR1/0 bit is 1 and Gate bit
is 0, the counter continues counting up. If TR1/0 bit is 1 and Gate bit is 1, then the operation
of the counter is controlled by input. This mode is useful to measure the width of a given pulse
fed to input.

Timer Mode-1: This mode is similar to mode-0 except for the fact that the Timer operates in
16-bit mode

Timer Mode-2: (Auto-Reload Mode): This is a 8 bit counter/timer operation. Counting is

performed in TLX while THX stores a constant value. In this mode when the timer overflows
i.e. TLX becomes FFH, it is fed with the value stored in THX. For example if we load THX with
50H then the timer in mode 2 will count from 50H to FFH. After that 50H is again reloaded.
This mode is useful in applications like fixed time sampling.

Timer Mode-3: Timer 1 in mode-3 simply holds its count. The effect is same as setting TR1=0.
Timer0 in mode-3 establishes TL0 and TH0 as two separate counters.
Control bits TR1 and TF1 are used by Timer-0 (higher 8 bits) (TH0) in Mode-3 while TR0 and
TF0 are available to Timer-0 lower 8 bits(TL0).

1.2.3 To explain serial input/output of 8051 and associated registers-

SCON,SBUF.
The 8051 supports a full duplex serial port.

Three special function registers support serial communication.

1. SBUF Register: Serial Buffer (SBUF) register is an 8-bit register. It has separate SBUF
registers for data transmission and for data reception. For a byte of data to be transferred via
the TXD line, it must be placed in SBUF register. Similarly, SBUF holds the 8-bit data received
by the RXD pin and read to accept the received data.

2. SCON register: The contents of the Serial Control (SCON) register are shown below. This
register contains mode selection bits, serial port interrupt bit (TI and RI) and also the ninth
data bit for transmission and reception (TB8 and RB8).
1.2.4 To Explain interrupts in 8051 and associated registers-IP,IE.
8051 makes use of two registers to deal with interrupts.

1. IE Register

This is an 8 bit register used for enabling or disabling the interrupts. The structure of IE register
is shown below.

2. IP Register.

This is an 8 bit register used for setting the priority of the interrupts.
 MODULE II Programming and Application of Microcontroller

2.1.1 To explain addressing modes of 8051.

8051 addressing modes are classified as follows.

1. Immediate addressing.

2. Register addressing.

3. Direct addressing.

4. Indirect addressing.

5. Relative addressing.

6. Absolute addressing.

7. Long addressing.

8. Indexed addressing.

9. Bit inherent addressing.

10. Bit direct addressing.

1. Immediate addressing.

In this addressing mode the data is provided as a part of instruction itself. In other words data
immediately follows the instruction.
Eg. MOV A,#30H

ADD A, #83 # Symbol indicates the data is immediate

2. Register addressing.

In this addressing mode the register will hold the data. One of the eight general registers (R0
to R7) can be used and specified as the operand.

Eg. MOV A,R0

ADD A,R6

R0 – R7 will be selected from the current selection of register bank. The default register bank
will be bank 0.

3. Direct addressing

There are two ways to access the internal memory. Using direct address and indirect address.
Using direct addressing mode we can not only address the internal memory but SFRs also. In
direct addressing, an 8 bit internal data memory address is specified as part of the instruction
and hence, it can specify the address only in the range of 00H to FFH. In this addressing mode,
data is obtained directly from the memory.

Eg. MOV A,60h

ADD A,30h

4. Indirect addressing

The indirect addressing mode uses a register to hold the actual address that will be used in
data movement. Registers R0 and R1 and DPTR are the only registers that can be used as data
pointers. Indirect addressing cannot be used to refer to SFR registers. Both R0 and R1 can hold
8 bit address and DPTR can hold 16 bit address.

Eg. MOV A,@R0

ADD A,@R1

MOVX A,@DPTR

5. Indexed addressing.

In indexed addressing, either the program counter (PC), or the data pointer (DTPR)—is used
to hold the base address, and the A is used to hold the offset address. Adding the value of the
base address to the value of the offset address forms the effective address. Indexed
addressing is used with JMP or MOVC instructions. Look up tables are easily implemented
with the help of index addressing.
Eg. MOVC A, @A+DPTR // copies the contents of memory location pointed by the sum of the
accumulator A and the DPTR into accumulator A.

MOVC A, @A+PC // copies the contents of memory location pointed by the sum of the
accumulator A and the program counter into accumulator A.

6. Relative Addressing. Relative addressing is used only with conditional jump instructions.
The relative address (offset), is an 8 bit signed number, which is automatically added to the
PC to make the address of the next instruction. The 8 bit signed offset value gives an address
range of +127 to —128 locations. The jump destination is usually specified using a label and
the assembler calculates the jump offset accordingly. The advantage of relative addressing is
that the program code is easy to relocate and the address is relative to position in the
memory.

Eg. SJMP LOOP1

JC BACK

7. Absolute addressing

Absolute addressing is used only by the AJMP (Absolute Jump) and ACALL (Absolute Call)
instructions. These are 2 bytes instructions. The absolute addressing mode specifies the
lowest 11 bit of the memory address as part of the instruction. The upper 5 bit of the
destination address are the upper 5 bit of the current program counter. Hence, absolute
addressing allows branching only within the current 2 Kbyte page of the program memory.

Eg. AJMP LOOP1

ACALL LOOP2

2.1.2 To describe instruction set of 8051.

1. Instruction Timings
The 8051 internal operations and external read/write operations are controlled by the
oscillator clock.

T-state, Machine cycle and Instruction cycle are terms used in instruction timings.

T-state is defined as one subdivision of the operation performed in one clock period. The
terms 'T-state' and 'clock period' are often used synonymously.

Machine cycle is defined as 12 oscillator periods. A machine cycle consists of six states and
each state lasts for two oscillator periods. An instruction takes one to four machine cycles to
execute an instruction. Instruction cycle is defined as the time required for completing the
execution of an instruction. The 8051 instruction cycle consists of one to four machine cycles.

2. 8051 Instructions

The instructions of 8051 can be broadly classified under the following headings.

1. Data transfer instructions

2. Arithmetic instructions

3. Logical instructions

4. Branch instructions

5. Subroutine instructions

6. Bit manipulation instructions

2.1.3 To describe logical operations.

Logical Instructions

Logical AND

ANL destination, source: ANL does a bitwise "AND" operation between source and
destination, leaving the resulting value in destination. The value in source is not affected.
"AND" instruction logically AND the bits of source and destination.

ANL A,#DATA ANL A, Rn

ANL A,DIRECT ANL A,@Ri

ANL DIRECT,A ANL DIRECT, #DATA

Logical OR

ORL destination, source: ORL does a bitwise "OR" operation between source and destination,
leaving the resulting value in destination. The value in source is not affected. " OR " instruction
logically OR the bits of source and destination.

ORL A,#DATA ORL A, Rn

ORL A,DIRECT ORL A,@Ri

ORL DIRECT,A ORL DIRECT, #DATA

Logical Ex-OR

XRL destination, source: XRL does a bitwise "EX-OR" operation between source and
destination, leaving the resulting value in destination. The value in source is not affected. "
XRL " instruction logically EX-OR the bits of source and destination.

XRL A,#DATA XRL A,Rn

XRL A,DIRECT XRL A,@Ri

XRL DIRECT,A XRL DIRECT, #DATA

Logical NOT

CPL complements operand, leaving the result in operand. If operand is a single bit then the
state of the bit will be reversed. If operand is the Accumulator then all the bits in the
Accumulator will be reversed.

CPL A, CPL C, C PL bit address

SWAP A – Swap the upper nibble and lower nibble of A.

Rotate Instructions

RR A

This instruction is rotate right the accumulator. Its operation is illustrated below. Each bit is
shifted one location to the right, with bit 0 going to bit 7.

RL A

Rotate left the accumulator. Each bit is shifted one location to the left, with bit 7 going to bit
0
RRC A

Rotate right through the carry. Each bit is shifted one location to the right, with bit 0 going
into the carry bit in the PSW, while the carry was at goes into bit 7

RLC A

Rotate left through the carry. Each bit is shifted one location to the left, with bit 7 going into
the carry bit in the PSW, while the carry goes into bit 0.

2.1.4 To describe arithmetic operations.

Arithmetic instructions.

The 8051 can perform addition, subtraction. Multiplication and division operations on 8 bit
numbers.

Addition

In this group, we have instructions to

i. Add the contents of A with immediate data with or without carry.

i. ADD A, #45H

ii. ADDC A, #OB4H

ii. Add the contents of A with register Rn with or without carry.

i. ADD A, R5

ii. ADDC A, R2

iii. Add the contents of A with contents of memory with or without carry using direct and
indirect addressing

i. ADD A, 51H
 ii. ADDC A, 75H

iii. ADD A, @R1

iv. ADDC A, @R0

Subtraction

In this group, we have instructions to

i. Subtract the contents of A with immediate data with or without carry.

i. SUBB A, #45H

ii. SUBB A, #OB4H

ii. Subtract the contents of A with register Rn with or without carry.

i. SUBB A, R5

ii. SUBB A, R2

iii. Subtract the contents of A with contents of memory with or without carry using direct and
indirect addressing

i. SUBB A, 51H

ii. SUBB A, 75H

iii. SUBB A, @R1

iv. SUBB A, @R0

Multiplication

MUL AB. This instruction multiplies two 8 bit unsigned numbers which are stored in A and B
register. After multiplication the lower byte of the result will be stored in accumulator and
higher byte of result will be stored in B register.

Eg. MOV A,#45H ; [A]=45H

MOV B,#0F5H ; [B]=F5H

MUL AB ;[A] x [B] = 45 x F5 = 4209

;[A]=09H, [B]=42H

Division
DIV AB. This instruction divides the 8 bit unsigned number which is stored in A by the 8 bit
unsigned number which is stored in B register. After division the result will be stored in
accumulator and remainder will be stored in B register.

Eg. MOV A,#45H ; [A]=0E8H

MOV B,#0F5H ; [B]=1BH

DIV AB ;[A] / [B] = E8 /1B = 08 H with remainder 10H

;[A] = 08H, [B]=10H

DA A (Decimal Adjust After Addition).

When two BCD numbers are added, the answer is a non-BCD number. To get the result in
BCD, we use DA A instruction after the addition. DA A works as follows.

If lower nibble is greater than 9 or auxiliary carry is 1, 6 is added to lower nibble.

If upper nibble is greater than 9 or carry is 1, 6 is added to upper nibble.

Eg 1: MOV A,#23H

MOV R1,#55H

ADD A,R1 // [A]=78

DA A // [A]=78 no changes in the accumulator after da a

Eg 2: MOV A,#53H

MOV R1,#58H

ADD A,R1 // [A]=ABh

DA A // [A]=11, C=1 . ANSWER IS 111. Accumulator data is changed after DA A

Increment: increments the operand by one.

INC A INC Rn INC DIRECT INC @Ri INC DPTR

INC increments the value of source by 1. If the initial value of register is FFh, incrementing the
value will cause it to reset to 0. The Carry Flag is not set when the value "rolls over" from 255
to 0.

In the case of "INC DPTR", the value two-byte unsigned integer value of DPTR is incremented.
If the initial value of DPTR is FFFFh, incrementing the value will cause it to reset to 0.

Decrement: decrements the operand by one.

DEC A DEC Rn DEC DIRECT DEC @Ri

DEC decrements the value of source by 1. If the initial value of is 0, decrementing the value
will cause it to reset to FFh. The Carry Flag is not set when the value "rolls over" from 0 to FFh.

2.1.5 To describe jump and call instructions.

Branch (JUMP) Instructions

There are 3 types of jump instructions. They are:-

1. Relative Jump

2. Short Absolute Jump

3. Long Absolute Jump

Relative Jump

Jump that replaces the PC (program counter) content with a new address that is greater than
(the address following the jump instruction by 127 or less) or less than (the address following
the jump by 128 or less) is called a relative jump.

Instructions that use Relative Jump are

JC <relative address>

JNC <relative address>

JB bit, <relative address>

JNB bit, <relative address>

JBC bit, <relative address>

CJNE <destination byte>, <source byte>, <relative address>

DJNZ <byte>, <relative address>

JZ <relative address>

JNZ <relative address>

Subroutine CALL And RETURN Instructions

There are two types of CALL instructions

1. LCALL address(16 bit)

This is long call instruction which unconditionally calls the subroutine located at the indicated
16 bit address. This is a 3 byte instruction. The LCALL instruction works as follows.

a. During execution of LCALL, [PC] = [PC]+3; (if address where LCALL resides is say, 0x3254;
during execution of this instruction [PC] = 3254h + 3h = 3257h

b. [SP]=[SP]+1; (if SP contains default value 07, then SP increments and [SP]=08

c. [[SP]] = [PC7-0]; (lower byte of PC content ie., 57 will be stored in memory location 08.

d. [SP]=[SP]+1; (SP increments again and [SP]=09)

e. [[SP]] = [PC15-8]; (higher byte of PC content ie., 32 will be stored in memory location 09.

With these the address (0x3254) which was in PC is stored in stack.

f. [PC]= address (16 bit); the new address of subroutine is loaded to PC. No flags are affected.

2. ACALL address(11 bit)

This is absolute call instruction which unconditionally calls the subroutine located at the
indicated 11 bit address. This is a 2 byte instruction. The SCALL instruction works as follows.

a. During execution of SCALL, [PC] = [PC]+2; (if address where LCALL resides is say, 0x8549;
during execution of this instruction [PC] = 8549h + 2h = 854Bh

b. [SP]=[SP]+1; (if SP contains default value 07, then SP increments and [SP]=08

c. [[SP]] = [PC7-0]; (lower byte of PC content ie., 4B will be stored in memory location 08.

d. [SP]=[SP]+1; (SP increments again and [SP]=09)

e. [[SP]] = [PC15-8]; (higher byte of PC content ie., 85 will be stored in memory location 09.

2.1.6 To describe timing & delay subroutines

In computer programming, a subroutine is a sequence of program instructions that performs
a specific task, packaged as a unit. This unit can then be used in programs wherever that
particular task should be performed. Subroutines may be defined within programs, or
separately in libraries that can be used by many programs. In different programming
languages, a subroutine may be called a procedure, a function, a routine, a method, or a
subprogram. The generic term callable unit is sometimes used. When a subroutine is called,
program control is transferred from the main program to the subroutine. When the
subroutine finishes executing, control is returned to the main program. The stack provides
the means of connecting the subroutines to the main program.

When the delay subroutine is executed, the microprocessor does not

execute other tasks. For the delay we are using the instruction execution times. executing
some instructions in a loop, the delay is generated. There are some methods of generating
delays. set of Instructions which are used repeatedly in a program can be referred to as
Subroutine. Only one copy of this Instruction is stored in the memory. When a Subroutine is
required it can be called many times during the Execution of a Particular program. A call
Subroutine Instruction calls the Subroutine. Care should be taken while returning a
Subroutine as Subroutine can be called from a different place from the memory.

MODULE III Advanced Microcontroller and Interfacing.

3.1.0 To describe the basics of serial communication.

SERIAL COMMUNICATION

DATA COMMUNICATION

The 8051 microcontroller is parallel device that transfers eight bits of data simultaneously
over eight data lines to parallel I/O devices. Parallel data transfer over a long is very expensive.
Hence, a serial communication is widely used in long distance communication. In serial data
communication, 8-bit data is converted to serial bits using a parallel in serial out shift register
and then it is transmitted over a single data line. The data byte is always transmitted with
least significant bit first.

BASICS OF SERIAL DATA COMMUNICATION

 1. Simplex communication link: In simplex transmission, the line is dedicated for
transmission. The transmitter sends and the receiver receives the data.
2. Half duplex communication link: In half duplex, the communication link can be used
for either transmission or reception. Data is transmitted in only one direction at a time
3. Full duplex communication link: If the data is transmitted in both ways at the same
time, it is a full duplex i.e. transmission and reception can proceed simultaneously.
This communication link requires two wires for data, one for transmission and one for
reception.
3.1.1 To describe the asynchronous serial communication and data
framing.
Asynchronous Serial data transmission: In this, different clock sources are used for transmitter
and receiver. In this mode, data is transmitted with start and stop bits. A transmission begins
with start bit, followed by data and then stop bit. For error checking purpose parity bit is
included just prior to stop bit. In Asynchronous serial data communication a single byte is
transmitted at a time.

Baud rate: The rate at which the data is transmitted is called baud or transfer rate. The baud
rate is the reciprocal of the time to send one bit. In asynchronous transmission, baud rate is
not equal to number of bits per second. This is because; each byte is preceded by a start bit
and followed by parity and stop bit. For example, in synchronous transmission, if data is
transmitted with 9600 baud, it means that 9600 bits are transmitted in one second. For bit
transmission time = 1 second/ 9600 = 0.104 ms.

3.1.2 To explain serial communication between PC and 8051.

The 8051 supports a full duplex serial port.

Three special function registers support serial communication.

1. SBUF Register: Serial Buffer (SBUF) register is an 8-bit register. It has separate SBUF
registers for data transmission and for data reception. For a byte of data to be transferred via
the TXD line, it must be placed in SBUF register. Similarly, SBUF holds the 8-bit data received
by the RXD pin and read to accept the received data.

2. SCON register: The contents of the Serial Control (SCON) register are shown below. This
register contains mode selection bits, serial port interrupt bit (TI and RI) and also the ninth
data bit for transmission and reception (TB8 and RB8).
SERIAL COMMUNICATION MODES

1.Mode 0

In this mode serial port runs in synchronous mode. The data is transmitted and received
through RXD pin and TXD is used for clock output. In this mode the baud rate is 1/12 of clock
frequency.

2. Mode 1

In this mode SBUF becomes a 10 bit full duplex transceiver. The ten bits are 1 start bit, 8 data
bit and 1 stop bit. The interrupt flag TI/RI will be set once transmission or reception is over.
In this mode the baud rate is variable and is determined by the timer 1 overflow rate.

Baud rate = [2smod/32] x Timer 1 overflow Rate

= [2smod/32] x [Oscillator Clock Frequency] / [12 x [256 – [TH1]]]

3. Mode 2

This is similar to mode 1 except 11 bits are transmitted or received. The 11 bits are, 1 start
bit, 8 data bit, a programmable 9th data bit, 1 stop bit.
Baud rate = [2smod/64] x Oscillator Clock Freq

4. Mode 3

This is similar to mode 2 except baud rate is calculated as in mode 1

3.1.2 To describe 8255 programmable peripheral interface

8255A PROGRAMMABLE PERIPHERAL INTERFACE

The 8255A programmable peripheral interface (PPI) implements a general-purpose I/O

interface to connect peripheral equipment to a microcomputer system bus.

Features

• Three 8-bit Peripheral Ports - Ports A, B, and C

• Three programming modes for Peripheral Ports: Mode 0 (Basic Input/Output), Mode 1
(Strobed Input/Output), and Mode 2 (Bidirectional)

• Total of 24 programmable I/O lines

• 8-bit bidirectional system data bus with standard microprocessor interface controls

ARCHITECTURE OF 8255A
Read/Write Control Logic has six connections.
Read, Write: This control signal enables the Read/Write operation. When the signal is
low, the controller reads/writes data from/to a selected I/O Port of the 8255.
RESET: This is an active high signal; it clears the control register and sets all ports in
the input mode.
CS, A0 and A1: Theses are device select signals. Chip Select is connected to a decoded
address, and A0 and A1 are generally connected to MPU address lines A0 and A1
respectively

Control register is an 8 bit register. The contents of this register called control word.
This register can be accessed to write a control word when A0 and A1 are at logic 1.
This control register is not accessible for a read operation.
Bit D7 of the control register specifies either I/O function or the Bit Set/Reset function.
If bit D7=1, bits D6-D0 determines I/O functions in various modes. If bit D7=0, Port C
 operates in the Bit Set/Reset (BSR) mode. The BSR control word does not affect the
functions of Port A and Port B.

3.1.3 To demonstrate controlling of a stepper motor with μC 8051.

A motor used for moving things in small increments is called a stepper motor. A stepper
motor rotates from one fixed position to the next position rather than continuous
rotation in the case of other AC or DC motors. A stepper motor is used to rotate one step
at a time. The figure shows the interfacing of 8051 with the stepper motor. A stepper
motor needs to cyclically gie the current to an adjacent coil out of its 4 coilsC1, C2, C3 and
C4. First the C1 current is switched ON. Then C2 current is switched on. Then C3 is
switched on. Then C4, then C1.A change in current into adjacent coil causes motor to
move one step. A step angle may be 1.8 degree in a typical design. The 7406 buffers are
inverting so a high on an output pin turns on current to a winding. The table below shows
switching sequence to step a motor clockwise or anticlockwise.
The purpose of the clamp diodes across each winding is to save transistors from inductive
kick. Resistors R1 and R2 are current limiting resistors. Suppose that SW1 and SW2 are
turned ON. Turning OFF SW2 and turning on SW4 cause the motor to rotate one step of
1.8 degree clockwise. Changing SW4 and SW3 ON will cause the motor to rotate 1.8
degree clockwise another. Changing SW3 and SW2 ON will cause another step. This step
can be repeated till the motor has rotated as many steps

3.1.4 To describe how to interface a relay with μC 8051

Electromechanical relays are frequently used in industrial and control applications. The
relay coil operating at 5V has a coil resistance of 50 ohm and operates at a current of
normally 100Ma.

There are two types of relays normally open(NO) and normally closed type (NC)

When energized the NO type relay is closed while the NC type of relay becomes open to
connect or disconnect the device. For example to start or stop a 230-250V AC motor using
a micro controllers , a relay is used. This simple connection of aa relay with 8051 can be
used. In this a relay is connected at pin 1.0 of 8051

3.2.0 To explain the features of PIC 18.

1. It is 8-bit Microcontroller
2. It has 16-bit Instruction sets

3. 256 byte of EPROM.

 4. 2 KB SRAM

5. 32 KB Flash Memory

6. It Operates at 40 MHz Crystal

7. It has 10-bit A/D Converter.

8. It supports Instruction Pipelining

9. It is implemented with nano watt Technology (low power consumption ).

3.2.0 To explain the features of AVR.

AVR Microcontroller was established by Atmel. Atmel Corporation was founded in 1984 for
designing and manufacturing semiconductors. A microcontroller is a control device integrated
with a microprocessor contains memory, I/O Peripherals, etc.

Three Categories of AVR Microcontroller

TinyAVR: Smaller in size and Less memory.

MegaAVR: Popular, memory up to 256 kb, several quantities of inbuilt peripherals, complex
application.

XmegaAVR: Large Memory, High Speed, and complex applications

Key Features

• High Performance

• Low Power

• Large address space

• Efficient

• Low Expensive

• RISC Architecture like ARM Microcontroller

3.2.1 To explain the block diagram of AT tiny 25.

The ATtiny25/45/85 is a low-power CMOS 8-bit microcontroller based on the AVR enhanced
RISC architecture. By executing powerful instructions in a single clock cycle, the
ATtiny25/45/85 achieves throughputs approaching 1MIPS per MHz allowing the system
designer to optimize power consumption versus processing speed. The AVR core combines a
rich instruction set with 32 general purpose working registers. All 32 registers are directly
connected to the Arithmetic Logic Unit (ALU), allowing two independent registers to be
accessed in one single instruction executed in one clock cycle. The resulting architecture is
more code efficient while achieving throughputs up to ten times faster than conventional CISC
microcontrollers.

The ATtiny25/45/85 provides the following features: 2/4/8K bytes of In-System

Programmable Flash, 128/256/512 bytes EEPROM, 128/256/256 bytes SRAM, 6 general
purpose I/O lines, 32 general purpose working registers, one 8-bit Timer/Counter with
compare modes, one 8-bit high speed Timer/Counter, Universal Serial Interface, Internal and
External Interrupts, a 4-channel, 10-bit ADC, a programmable Watchdog Timer with internal
Oscillator, and three software selectable power saving modes. Idle mode stops the CPU while
allowing the SRAM, Timer/Counter, ADC, Analog Comparator, and Interrupt system to
continue functioning. Power-down mode saves the register contents, disabling all chip
functions until the next Interrupt or Hardware Reset. ADC Noise Reduction mode stops the
CPU and all I/O modules except ADC, to minimize switching noise during ADC conversions.

The device is manufactured using Atmel’s high density non-volatile memory technology. The
On-chip ISP Flash allows the Program memory to be re-programmed In-System through an
SPI serial interface, by a conventional non-volatile memory programmer or by an On-chip
boot code running on the AVR core.

The ATtiny25/45/85 AVR is supported with a full suite of program and system development
tools including: C Compilers, Macro Assemblers, Program Debugger/Simulators and
Evaluation kits.

3.2.2 To explain the block diagram of AT mega 32.

It belongs to Atmel’s AVR series micro controller family. Atmega32 has got 40 pins. Two for
Power (pin no.10: +5v, pin no. 11: ground), two for oscillator (pin 12, 13), one for reset (pin
9), three for providing necessary power and reference voltage to its internal ADC, and 32 (4×8)
I/O pins.

About I/O pins: ATmega32 is capable of handling analogue inputs. Port A can be used as either
DIGITAL I/O Lines or each individual pin can be used as a single input channel to the internal
ADC of ATmega32, plus a pair of pins AREF, AVCC & GND together can make an ADC channel.
No pins can perform and serve for two purposes (for an example: Port A pins cannot work as
a Digital I/O pin while the Internal ADC is activated) at the same time.

Digital I/O pins: ATmega32 has 32 pins (4portsx8pins) configurable as Digital I/O pins.

Timers: 3 Inbuilt timer/counters, two 8 bit (timer0, timer2) and one 16 bit (timer1).
ADC: It has one successive approximation type ADC in which total 8 single channels are
selectable. They can also be used as 7 (for TQFP packages) or 2 (for DIP packages) differential
channels. Reference is selectable, either an external reference can be used or the internal
2.56V reference can be brought into action. There external reference can be connected to
the AREF pin.

Communication Options: ATmega32 has three data transfer modules embedded in it. They
are

1. Two Wire Interface

2. USART

3. Serial Peripheral Interface

Analog comparator: On-chip analog comparator is available. An interrupt is assigned for
different comparison result obtained from the inputs.

External Interrupt: 3External interrupt is accepted. Interrupt sense is configurable.

Memory: It has 32Kbytes of In-System Self-programmable Flash program memory, 1024

Bytes EEPROM, 2Kbytes Internal SRAM. Write/Erase Cycles: 10,000 Flash / 100,000 EEPROM.

Clock: It can run at a frequency from 1 to 16 MHz. Frequency can be obtained from external
Quartz Crystal, Ceramic crystal or an R-C network. Internal calibrated RC oscillator can also be
used.

More Features: Up to 16 MIPS throughput at 16MHz. Most of the instruction executes in a

single cycle. Two cycle on-chip multiplication. 32 × 8 General Purpose Working Registers

Debug: JTAG boundary scan facilitates on chip debug.

Programming: Atmega32 can be programmed either by In-System Programming via Serial

peripheral interface or by Parallel programming. Programming via JTAG interface is also
possible. Programmer must ensure that SPI programming and JTAG are not be disabled using
fuse bits; if the programming is supposed to be done using SPI or JTAG.

1.2.1 To explain the block diagrams of ;

a) PIC18.

b) PIC 16.
PIC18FXX2 series consists of four devices. PIC18F2X2 microcontrollers are 28-pin devices,
while PIC18F4X2 microcontrollers are 40-pin devices.

The architectures of the two groups are almost identical except that the larger devices have

more input-output ports and more A/D converter channels. In this section we shall be looking

at the architecture of the PIC18F452 microcontroller in detail. The architectures of other

standard PIC18F-series microcontrollers are similar, and the knowledge gained in this section

should be enough to understand the operation of other PIC18F-series microcontrollers.

shows the internal block diagram of the PIC18F452 microcontroller. TheCPU is at the center
of the diagram and consists of an 8-bit ALU, an 8-bit working accumulator register (WREG),
and an 8 8 hardware multiplier. The higher byte and the lower byte of a multiplication are
stored in two 8-bit registers called PRODH and PRODL respectively.

The program counter and program memory are shown in the upper left portion of the
diagram. Program memory addresses consist of 21 bits, capable of accessing 2Mbytes of
program memory locations. The PIC18F452 has only 32Kbytes of program memory, which
requires only 15 bits. The remaining 6 address bits are redundant and not used. A table
pointer provides access to tables and to the data stored in program memory. The program
memory contains a 31-level stack which is normally used to store the interrupt and subroutine
return addresses.
The data memory can be seen at the top center of the diagram. The data memory bus is 12
bits wide, capable of accessing 4Kbytes of data memory locations., the data memory consists
of special function registers (SFR) and general purpose registers, all organized in banks.

The bottom portion of the diagram shows the timers/counters, capture/compare/PWM

registers, USART, A/D converter, and EEPROM data memory. The PIC18F452

consists of:

4 timers/counters

2 capture/compare/PWM modules

2 serial communication modules

8 10-bit A/D converter channels

256 bytes EEPROM

The oscillator circuit, located at the left side of the diagram, consists of:

Power-up timer

Oscillator start-up timer

Power-on reset

Watchdog timer

Brown-out reset

Low-voltage programming

In-circuit debugger

PLL circuit

Timing generation circuit

The PLL circuit is new to the PIC18F series and provides the option of multiplying up the
oscillator frequency to speed up the overall operation. The watchdog timer can be used to
force a restart of the microcontroller in the event of a program crash. The in-circuit debugger
is useful during program development and can be used to return diagnostic data, including
the register values, as the microcontroller is executing a program.

The input-output ports are located at the right side of the diagram. The PIC18F452 has five
parallel ports named PORTA, PORTB, PORTC, PORTD, and PORTE. Most port pins have multiple
functions. For example, PORTA pins can be used as parallel inputs-outputs or analog inputs.
PORTB pins can be used as parallel inputs-outputs or as interrupt inputs.

PIC16

The PIC microcontroller architecture comprises of CPU, I/O ports, memory

organization, A/D converter, timers/counters, interrupts, serial communication,
oscillator and CCP module which are discussed in detailed below.

CPU (Central Processing Unit)

It is not different from other microcontrollers CPU and the PIC microcontroller CPU
consists of the ALU, CU, MU and accumulator, etc. Arithmetic logic unit is mainly used
for arithmetic operations and to take logical decisions. Memory is used for storing the
instructions after processing. To control the internal and external peripherals, control
unit is used which are connected to the CPU and the accumulator is used for storing
the results and further process.

Memory Organization
The memory module in the PIC microcontroller architecture consists of RAM (Random
Access Memory), ROM (Read Only Memory) and STACK.

Random Access Memory (RAM)

RAM is an unstable memory which is used to store the data temporarily in its registers.
The RAM memory is classified into two banks, and each bank consists of so many
registers. The RAM registers are classified into two types: Special Function Registers
(SFR) and General Purpose Registers (GPR).

General Purpose Registers (GPR)

These registers are used for general purpose only as the name implies. For example,
if we want to multiply two numbers by using the PIC microcontroller. Generally, we
use registers for multiplying and storing the numbers in other registers. So these
registers don’t have any special function,- CPU can easily access the data in the
registers.
General Purpose Registers (GPR)
These registers are used for general purpose only as the name implies. For example,
if we want to multiply two numbers by using the PIC microcontroller. Generally, we
use registers for multiplying and storing the numbers in other registers. So these
registers don’t have any special function,- CPU can easily access the data in the
registers.

Special Function Registers

These registers are used for special purposes only as the name SFR implies. These
registers will perform according to the functions assigned to them , and they cannot
be used as normal registers. For example, if you cannot use the STATUS register for
storing the data, these registers are used for showing the operation or status of the
program. So, user cannot change the function of the SFR; the function is given by the
retailer at the time of manufacturing.
Read Only Memory (ROM)
Read only memory is a stable memory which is used to store the data permanently. In
PIC microcontroller architecture, the architecture ROM stores the instructions or
program, according to the program the microcontroller acts. The ROM is also called as
program memory, wherein the user will write the program for microcontroller and
saves it permanently, and finally the program is executed by the CPU. The
microcontrollers performance depends on the instruction, which is executed by the
CPU.
Electrically Erasable Programmable Read Only Memory (EEPROM)
In the normal ROM, we can write the program for only once we cannot use again the
microcontroller for multiple times. But, in the EEPROM, we can program the ROM
multiple times.

Flash Memory
Flash memory is also programmable read only memory (PROM) in which we can read,
write and erase the program thousands of times. Generally, the PIC microcontroller
uses this type of ROM.

Stack
When an interrupt occurs, first the PIC microcontroller has to execute the interrupt
and the existing process address. Then that is being executed is stored in the stack.
After completing the execution of the interrupt, the microcontroller calls the process
with the help of address, which is stored in the stack and get executes the process.

I/O Ports
The series of PIC16 consists of five ports such as Port A, Port B, Port C, Port D & Port
E.
Port A is an 16-bit port that can be used as input or output port based on the status of
the TRISA (Tradoc Intelligence Support Activity) register.
Port B is an 8- bit port that can be used as both input and output port.
Port C is an 8-bit and the input of output operation is decided by the status of the
TRISC register.
Port D is an 8-bit port acts as a slave port for connection to the microprocessor BUS.
Port E is a 3-bit port which serves the additional function of the control signals to the
analog to digital converter.
BUS
BUS is used to transfer and receive the data from one peripheral to another. It is
classified into two types such as data bus and address.