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    The Intel Pentium

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    mani_vlsi
    The document summarizes the key features and innovations of the first Intel Pentium processor introduced in 1993. It had a superscalar architecture, dynamic branch prediction, and pipelined integer and floating-point units. It supported features of previous Intel processors while adding enhancements such as dual instruction pipelines, separate code and data caches, and a 64-bit data bus. The Pentium was compatible with existing software but offered faster performance through these architectural improvements.

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    The Intel Pentium

    Uploaded by

    mani_vlsi
    176 views10 pages
    The document summarizes the key features and innovations of the first Intel Pentium processor introduced in 1993. It had a superscalar architecture, dynamic branch prediction, and pipelined integer and floating-point units. It supported features of previous Intel processors while adding enhancements such as dual instruction pipelines, separate code and data caches, and a 64-bit data bus. The Pentium was compatible with existing software but offered faster performance through these architectural improvements.

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    The document summarizes the key features and innovations of the first Intel Pentium processor introduced in 1993. It had a superscalar architecture, dynamic branch prediction, and pipelined integer and floating-point units. It supported features of previous Intel processors while adding enhancements such as dual instruction pipelines, separate code and data caches, and a 64-bit data bus. The Pentium was compatible with existing software but offered faster performance through these architectural improvements.

    Copyright:

    Attribution Non-Commercial (BY-NC)
    Download as PPT, PDF, TXT or read online from Scribd
    Download as ppt, pdf, or txt
    176 views10 pages

    The Intel Pentium

    Uploaded by

    mani_vlsi
    The document summarizes the key features and innovations of the first Intel Pentium processor introduced in 1993. It had a superscalar architecture, dynamic branch prediction, and pipelined integer and floating-point units. It supported features of previous Intel processors while adding enhancements such as dual instruction pipelines, separate code and data caches, and a 64-bit data bus. The Pentium was compatible with existing software but offered faster performance through these architectural improvements.

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    Attribution Non-Commercial (BY-NC)
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    The first Intel Pentium

    Introduced to market on March 22, 1993 with a CPU clock cycle of 66 Mhz With its coming, it hosted many innovations, the most notable being:

    Superscalar architecture Dynamic Branch Prediction Pipelined Integer Unit Pipelined Floating-Point Unit These features made the newly introduced chip a very popular choice for desktop, although it was later found that the processor had some notorious implementation errors.

    PROCESSOR FEATURES
    The Pentium processor supports the features of previous Intel Architecture processors and provides significant enhancements including the following: Superscalar Architecture Dynamic Branch Prediction Pipelined Floating-Point Unit Improved Instruction Execution Time Separate Code and Data Caches 1 . Writeback MESI Protocol in the Data Cache 64-Bit Data Bus Bus Cycle Pipelining Address Parity Internal Parity Checking Functional Redundancy Checking 2 and Lock Step operation 2 Execution Tracing Performance Monitoring IEEE 1149.1 Boundary Scan System Management Mode

    The Intel Pentium Processor

    Pentium

    Pentium Pro

    Pentium II

    Pentium III

    COMPONENT INTRODUCTION
    The application instruction set of the Pentium processor family includes the complete instruc-tion set of existing Intel Architecture processors to ensure backward compatibility, With extensions to accommodate the additional functionality of the Pentium processor. All application software written for the Intel386 and Intel486 microprocessors will run on the Pentium processor without modification. The on-chip memory management unit (MMU) is completely compatible with the Intel386 and Intel486 CPUs.

    INSTRUCTION PIPELINES
    The two instruction pipelines(Uand V) and the floating-point unit on the Pentium processor are capable of independent operation. Each pipeline issues frequently used instructions in a single clock. Together, the dual pipes can issue two integer instructions in one clock, or one floating-point instruction (under certain circumstances, 2 floating-point instructions) in one clock.

    Branch prediction
    Branch prediction is implemented in the Pentium processor. To support this, the Pentium processor implements two prefetch buffers, one to prefetch code in a linear fashion, and one that prefetches code according to the Branch Target Buffer (BTB) so the needed code is almost always prefetched before it is needed for execution.

    CODE AND DATA CACHES


    The Pentium processor includes separate code and data caches integrated on chip to meet its performance goals. . The caches on the Pentium processor (75/90/100/120/133/150/166/200) are each 8 Kbytes in size and 2-way set-associative. Each cache has a dedicated Translation Lookaside Buffer (TLB) to translate linear addresses to physical addresses. The Pentium processor data cache is configurable to be writeback or writethrough on a line-by-line basis and follows the MESI protocol. The data cache tags are triple ported to support two data transfers and an inquire cycle in the same clock. The code cache is an inherently write protected cache. The code cache tags of the Pentium processor (75/90/100/120/133/150/166/200) are also triple ported to support snooping and split-lineaccesses. code cache tags are dual ported. Individual pages can be configured as cacheable or non-cacheable by software or hardware. The caches can be enabled or disabled by software or hardware.

    BUS UNIT
    The Pentium processor has a 64-bit data bus. Burst read and burst writeback cycles are supported by the Pentium processor. In addition, bus cycle pipelining has been added to allow two bus cycles to be in progress simultaneously.

    DECODE UNIT and CONTROL ROM,FLOATING POINT UNIT


    The decode unit contains two parallel decoders which decode and issue up to the next two sequential instructions into the execution pipeline. The control ROM contains the microcode which controls the sequence of operations performed by the processor. The control unit has direct control over both pipelines. The Pentium processor contains a pipelined floatingpoint unit that provides a significant floating-point performance advantage over previous generations of Intel Architecture-based processors.

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