2023 S1 IT1020 Lecture 03

IT1020 – INTRODUCTION TO COMPUTER SYSTEMS
LECTURE 3:
COMPUTER ARCHITECTURE
LECTURE CONTENT
 This lecture covers:

 Fundamentals of computer organization,
 The heart of a computer system, CPU, its structure and functionality,
 How CPU is seen by programmers and CPU design engineers,
 Instruction set architecture of a processor.
COMPUTER ORGANIZATION
 Different groups of engineers see computer different manner

 Hardware Engineers see how different components work, their
configuration, how they are organized – Computer Organization
 Software Engineers see how computer can be used for different
applications, how their high-level language codes can be executed in
machine, How easily it can be used for programs – Instruction Set
Architecture
Computer organization is
concerned with the way
the hardware components CU
operate and the way they

are connected to form the
computer system.
 CPU: Controls the operation of the

computer and performs its data
processing functions.
 Main Memory: Stores data and
Instructions (Programs)
 I/O: Moves the data between the
computer and its external environment.
 System Interconnections (System
Bus): Mechanism that provides for
communication among CPU, MM, and
I/O.
 ALU: Performs the computer’s

data processing functions
 Registers: Provides storage
internal to the CPU
 Control Unit: A digital circuitry
within the processor that
coordinates the sequence of data
movements into, out of, and
between a processor's sub-units
MODERN COMPUTER
 Address Bus: CPU specify the address of MM or I/O, Uni-directional

 Data Bus: Transfer data/instruction to and from CPU
 Control Bus: Carries commands from CPU and status signals to CPU
8086 ARCHITECTURE
8086 REGISTERS
They are grouped into several categories as follows:

 Four general-purpose registers, AX, BX, CX, and DX.
 Four special-purpose registers, SP, BP, SI, and DI.
 Four segment registers, CS, DS, ES, and SS.
 The Program Counter/Instruction Pointer
 The status flag register, FLAGS
8086 REGISTERS
General Purpose Special Purpose (Addressing registers)
 AX is the accumulator. It is used for  The addressing registers are used in

all input/output operations and some memory addressing operations, such as
arithmetic operations. holding the source address of the
 BX is the base register. It can be used memory and the destination address.
as an address register.  SI is the source index and is used with
 CX is the count register. It is used by extended addressing commands.
instructions which require to count  DI is the destination index and is used
(Ex: Looping) in some addressing modes.
 DX is the data register. It is used for  BP is the base pointer.
some input/output and also when  SP is the stack pointer.
multiplying and dividing.
8086 REGISTERS
 The two status registers have 16 bits and are called the Instruction Pointer
(IP) or Program Counter (PC) and the flag register (F)
 IP is the instruction pointer and contains the address of the next
instruction of the program. This is called as Program Counter (PC)
 Flag register holds a collection of 16 different conditions. (Ex: result is
zero or not, there is a “carry” etc)
8086 REGISTERS
 Segments registers: There are four areas of memory called segments, each
of which are 16 bits and can thus address up to 64KB (from 0000h to
FFFFh).
 Code segment (cs register), where the program code is stored.
 Data segment (ds register), where data from the program is stored
 Stack segment (ss register), where the stack is stored.
 Extra segment (es register), a spare segment
 All addresses are with reference to the segment registers.
INSTRUCTION CYCLE
 The basic function performed by

a computer is execution of a
program
 Program is a well-defined set of
Instructions
 Processing a single instruction is
called instruction cycle
 It has two steps referred as fetch
cycle and execute cycle
INSTRUCTION CYCLE WITH INTERRUPT
 All computers provide a mechanism by which other modules (I/O, Memory) may
interrupt the normal processing of the processor
 Processor engaged in executing other instructions while slow external devices (ex.
I/O module) become ready and send interrupt request to processor
 Processor responds to such interrupt request by running interrupt handler
STATE DIAGRAM OF INSTRUCTION CYCLE WITH INTERRUPT
INSTRUCTION SET ARCHITECTURE (ISA)
 Instruction Set is a part of the computer that pertains to internal (or low
level) programming, which is basically machine language.
 The instruction set provides commands to the processor.
 Instructions instruct (give orders to) the processor what it needs to do.
Consider as “words” in processor’s language.
 User codes, normally written in High Level Languages (closer to Natural
Language) must convert to Machine Language to be run on the processor
 Assembly Language has

rich set of mnemonics to
represent Machine
Language Instructions
 Assembly Language
commands are in a
human readable format.
 Typical ISA defines:

 How to access data in Registers, Memory, and other I/O devices
 Mechanisms to transfer data and instruction to and from processor
 Operations such as additions, subtractions which processor can execute
 Control mechanisms such as branch, jump
 To be effective as a programmer or processor designer, one should know
how ISA works.
INSTRUCTION FORMAT
Opcode: Specifies the operation to be performed (Ex-ADD, SUB).

Operand: One or more inputs/outputs, or their source or destination
Next instruction reference: Tells the processor where to fetch the next instruction once
the execution of this instruction is completed.
INSTRUCTION FORMAT
Machine
Assembly
Language
Language
How it is
kept in
Memory Memory
Address
INSTRUCTION SET
Sample Instructions
 ADD - Add two numbers.
 CMP - Compare numbers.
 IN - Input from port into AL or AX. Second operand is a port number.
 JMP - Unconditional Jump. Transfers control to another part of the program.
 JNE - Short Jump if first operand is Not Equal to second operand.
 LOAD - Load information from RAM to the CPU.
 OUT - Output information to device, e.g. monitor.
 STORE - Store information to RAM.
EXECUTION OF INSTRUCTIONS
Processor
Executes
one
instruction
at a time.
CISC & RISC
CISC:
 Primary goal is to complete a task in as few lines of assembly as
possible
 Processor hardware complex; Needs less RAM to store the code;
Instruction set is high-level, hence Compiler workload is low
 Ex: MULT M1,M2
CISC & RISC
 RISC:
 Simple instructions that can be executed within one clock cycle
 Processor hardware simple; Need more RAM; Instruction set Low-Level, hence
Compiler workload high
 Ex: LOAD A, M1
 LOAD B, M2
 PROD A, B
 STORE M1,A
CISC & RISC
CISC RISC
• Includes multi-clock complex • Single-clock, reduced
instructions instruction only
• Emphasis on hardware • Emphasis on hardware
• Memory-to-memory: "LOAD" • Register to register: "LOAD"
and "STORE" incorporated in and "STORE" are independent
instructions instructions
• Small code sizes, high cycles • Low cycles per second, large
per second code sizes
• Transistors used for storing • Spends more transistors on
complex instructions memory registers
CISC & RISC
CISC RISC
• Intel X86 family, AMD • SPARC and Power PC are
processors are heavily used in used in desktop computers and
desktop, laptop and server game consoles
computers • RISC processors are heavily
used in real-time embedded
systems such as mobile
phones, washing machines,
Routers
• Raspberry pi and Arduino
• IoT drives by RISC processors
THANK YOU
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IT1020 – INTRODUCTION TO COMPUTER SYSTEMS

 This lecture covers:

 Different groups of engineers see computer different manner

operate and the way they

 CPU: Controls the operation of the

 ALU: Performs the computer’s

 Address Bus: CPU specify the address of MM or I/O, Uni-directional

They are grouped into several categories as follows:

 AX is the accumulator. It is used for  The addressing registers are used in

 The basic function performed by

 Assembly Language has

 Typical ISA defines:

Opcode: Specifies the operation to be performed (Ex-ADD, SUB).

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