Scribd
Upload
41 views

Basic Computer OrganizationTiming and Control Unit

The document discusses the timing and control in a basic computer's instruction cycle. It has 4 main steps: 1) Fetch an instruction from memory, 2) Decode the instruction, 3) Read the effective address from memory if indirect, 4) Execute the instruction. A 4-bit sequence counter and decoder generate timing signals to control each step over multiple clock cycles. The control unit translates machine instructions into signals to implement microoperations at each step.

Uploaded by

HARI HARAN REDDY
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PPTX, PDF, TXT or read online on Scribd
41 views

Basic Computer OrganizationTiming and Control Unit

The document discusses the timing and control in a basic computer's instruction cycle. It has 4 main steps: 1) Fetch an instruction from memory, 2) Decode the instruction, 3) Read the effective address from memory if indirect, 4) Execute the instruction. A 4-bit sequence counter and decoder generate timing signals to control each step over multiple clock cycles. The control unit translates machine instructions into signals to implement microoperations at each step.

Uploaded by

HARI HARAN REDDY
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PPTX, PDF, TXT or read online on Scribd
You are on page 1/ 12

Basic Computer Organization

Timing and Control

Computer Organization and Design


Agenda
 Instruction Codes

 Computer Registers

 Common Bus System

 Computer Instructions

 Timing and Control

 Instruction Cycle

 Memory Reference Instructions

 Input-Output and Interrupt

 Complete Computer Description


Control Unit
 Control unit (CU) of a processor translates from machine
instructions to the control signals for the microoperations
that implement them

 Control units are implemented in one of two ways


Hardwired Control
CU is made up of sequential and combinational circuits to generate the
control signals
Microprogrammed Control
A control memory on the processor contains microprograms that
activate the necessary control signals

 We will consider a hardwired implementation of the control


unit for the Basic Computer
Timing and Control
Control unit of Basic Computer

Instruction register (IR)


15 14 13 12 11 - 0 Other inputs

3x8
decoder
7 6543 210
D0
I Combinational
D7 Control Control
signals
logic

T15

T0

15 14 . . . . 2 1 0
4 x 16
decoder

4-bit Increment (INR)


sequence Clear (CLR)
counter
(SC) Clock
Timing Signals
- Generated by 4-bit sequence counter and 416 decoder
- The SC can be incremented or cleared.

- Example: T0, T1, T2, T3, T4, T0, T1, . . .


Assume: At time T4, SC is cleared to 0 if decoder output D3 is active.

D3T4: SC  0
T0 T1 T2 T3 T4 T0
Clock

T0

T1

T2

T3

T4

D3

CLR
SC
Thank You!
Instruction Cycle
 In Basic Computer, a machine instruction is executed in the
following cycle:
1. Fetch an instruction from memory
2. Decode the instruction
3. Read the effective address from memory if the instruction has an indirect
address
4. Execute the instruction

 After an instruction is executed, the cycle starts again at step


1, for the next instruction

Note: Every different processor has its own (different) instruction cycle
Fetch and Decode
Fetch and Decode T0: AR PC (S0S1S2=010, T0=1)
T1: IR  M [AR], PC  PC + 1 (S0S1S2=111, T1=1)
T2: D0, . . . , D7  Decode IR(12-14), AR  IR(0-11), I  IR(15)

T1 S2

T0 S1 Bus

S0
Memory
unit 7
Address
Read

AR 1

LD
PC 2

INR

IR 5

LD Clock
Common bus
Common Bus System
S2
S1 Bus
S0
Memory unit 7
4096 x 16
Address
Write Read
AR 1

LD INR CLR
PC 2

LD INR CLR
DR 3

LD INR CLR
E
ALU AC 4

LD INR CLR

INPR

IR 5
LD
TR 6
LD INR CLR
OUTR
Clock
LD
Flow Chart (Instruction Cycle)
Start
SC <-- 0

T0
AR <-- PC

T1
IR <-- M[AR], PC <-- PC + 1

T2
Decode Opcode in IR(12-14),
AR <-- IR(0-11), I <-- IR(15)

(Register or I/O) = 1 = 0 (Memory-reference)


D7

(I/O) = 1 = 0 (register) (indirect) = 1 = 0 (direct)


I I

T3 T3 T3 T3
Execute Execute AR <-- M[AR] Nothing
input-output register-reference
instruction instruction
SC <-- 0 SC <-- 0 Execute T4
memory-reference
instruction
SC <-- 0
Determining Type of Instruction

D'7IT3: AR M[AR]
D'7I'T3: Nothing
D7I'T3: Execute a register-reference instr.
D7IT3: Execute an input-output instr.

You might also like