EC1002-1: Applied Digital Logic Design

Analysis and design of

Combinational logic
Half adder
Full adder
Full adder using half adder
Sum = A ⊕ B ⊕ C
Carry = AB + (A ⊕ B)C
= AB + (A’B + AB’)C
= AB + A’BC + AB’C
= B (A + A’C) + AB’C
= B [(A + A’)(A + C)] + AB’C
= AB + BC + AB’C
= BC + A(B + B’C)
= BC + A[(B + B’)(B + C)]
= BC + AB + AC
= AB + BC + AC
4-bit ripple carry adder

1 1 0 0 0

1 1 0 1
1 1 0 0
1 1 0 0 1
 4-bit ripple carry adder/Parallel adder

C3 = Cout
Working of Ripple Carry Adder /Parallel adder
• Firstly the Full Adder A adds A0 and B0 along with the carry Cin to
generate the sum S0 (the first bit of the output sum) and the carry
C0 which is connected to the next adder in chain.
• Next, the Full Adder B uses this carry bit C0 to add with the input
bits A1 and B1 to generate the sum S1(the second bit of the
output sum) and the carry C1 which is again further connected to
the next adder in chain and so on.
• The process continues till the last Full Adder D uses the carry bit
C2 to add with its input A3 and B3 to generate the last bit of the
output S3 along with last carry bit C3.
Binary Subtractor
Parallel Subtractor
Working of Parallel Subtractor
• The parallel binary subtractor is formed by combination of all full
adders with subtrahend complement input.
• This operation considers that the addition of minuend along with
the 2’s complement of the subtrahend is equal to their subtraction.
• Firstly the 1’s complement of B is obtained by the NOT gate and 1
can be added through the carry to find out the 2’s complement of
B. This is further added to A to carry out the arithmetic subtraction.
• The process continues till the last full adder uses the carry bit to
add with its input A and 2’s complement of B to generate the last
bit of the output S3 along last carry bit C4.
For Subtraction
For a>b, a=b
• If a carry is generated (C4=1) , then ignore the carry
and result will be the difference between a and b.
For a<b
• If no carry (C4=0), then the difference is 2’s
compliment of the result with negative sign
BCD to Excess-3 Conversion

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The final set of output equations are
W= A + BD + BC
X = B’C + B’D + BC’D’
Y = C’D’ + CD
Z = D’

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Excess-3 to BCD
Excess-3 code is also a Self complementing code
Binary to gray code conversion
Binary to gray code conversion
Gray to Binary code conversion
Gray code is also called unit distance code
1-bit comparator
2- bit comparator
3 to 8 decoder with active high outputs
Truth Table of 3:8 decoder
4x2 Encoder
 8x3 Encoder

outputs
inputs
A2 = Y7 + Y6 + Y5 + Y4
A1 = Y7 + Y6 + Y3 + Y2
A0 = Y7 + Y5 + Y3 + Y1
Binary Multiplier
8x1 mux using 4x1 mux and OR gate
8x1 mux using 4x1 mux and 2x1 mux
Multiplexer as fulladder
Flip Flops and its
application

19EC302: Digital System Design 93

 Course Learning Objectives

After learning this unit the student should be

able to
1. Understand the operation and use of Latches
2. Describe the operation of several types of
pulse and edge-triggered flip-flops, such as the
J-K, D-type, S-R and T-type
19EC302: Digital System Design 94
 Introduction

• The outputs at any instant are dependent not only

upon the inputs present at that instant but also
upon the past history (or sequence) of inputs
– Sequential circuits are said to have memory

– All sequential circuits require the existence of feedback

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 Sequential Circuit Types
• A Synchronous Sequential Circuit is one in which its
behaviour is determined by the values of signals at only
discrete instants of time
• Generally have a master-clock that effectively samples the input data to
determine network behaviour

• An Asynchronous Sequential Circuit is one in which the

network is immediately affected by input signal changes.

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 Basic Bistable element
• Consists of two cross coupled inverters with
two outputs named and
– Assume x=0 initially => Q=y=1 =>= x =0.
– Assume x=1 initially =>Q=y=0 =>= x =1.

• The circuit is stable in both the levels.

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 Bistable Element
• It is used to store binary symbols.

• Stored symbol is referred to as content or state of the

element

• When the device is storing ‘1’ it is said to be ‘set’ or in

‘1-state’. When storing ‘0’ it is said to be ‘reset’ or in ‘0-

state’
19EC302: Digital System Design 98
 Latches
• Latch is an electronic logic circuit with two stable states.

• Latch has a feedback path to retain the information. Hence a

latch can be a memory device.
• Latch can store one bit of information as long as the device is
powered on.
• When enable is asserted, latch immediately changes the stored
information when the input is changed i.e. they are level
triggered devices. It continuously samples the inputs when the
enable signal is on.
19EC302: Digital System Design 99
 Flip-Flop
• The Flip-flop remains in a given state as long as the
power is applied and until input signal applied causes its
output to change.
• Inputs to Flip-flop can be of two types
– Synchronous or gated inputs: Signal change produces
an change in output only when some control signal
occurs
– Asynchronous or direct inputs: Signal change
19EC302: Digital System Design 100
produces an immediate change in output
Difference between Latches and Flip Flops

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 SR Latch
Circuit: HOLD/LATCH Mode
• S = 0, R = 0; This is the
normal resting state of the
circuit and it has no effect
on the output states. Q and
Q’ will remain in whatever
state they were in prior to
the occurrence of this input
condition. It works in HOLD
(no change) mode
operation.
102
 SR Latch
Truth Table: HOLD/LATCH Mode

103
 SR Latch
Circuit: SET Mode
• Consider the input S = 1.
Any time the input of a NOR
gate is 1 the output is 0. So,
the output of the second
NOR gate is 0, i.e. Q’ = 0.
• Q’ = 0 is fed back into the
input of the first NOR gate.
So, with R = 0, the output of
the first NOR gate is 1, i.e.
Q=1.
104
 SR Latch
Truth Table: SET Mode

105
 SR Latch
Circuit: RESET Mode
• Consider the input R = 1.
Any time the input of a
NOR gate is 1 the output is
0. So, the output of the first
NOR gate is 0, i.e. Q = 0.
• Q = 0 is fed back into the
input of the second NOR
gate. So, with S = 0, the
output of the second NOR
gate is 1, i.e. Q’=1.

106
 SR Latch
Truth Table: RESET Mode

107
 SR Latch
Circuit: INVALID Mode

• S = 1, R = 1; This condition
tries to set and reset the
NOR gate latch at the same
time, it produces Q = Q’ =
0. This is an unexpected
condition and is not used.
• The two outputs should be
the inverse of each other.

108
 SR Latch
Circuit: INVALID Mode
• If the inputs are returned
to 1 simultaneously, the
output states are
unpredictable.
• This input condition
should not be used and
when circuits are
constructed, the design
should make this condition
SET=RESET=1 never arises.
109
 SR Latch
Circuit: INVALID Mode

110
 R-S Latch [summary]
• Consists of two cross-coupled NOR gates.
• 2 inputs [R-Reset, S-Set] and 2 outputs []

19EC302: Digital System Design 111

 Quick Revision
NAND gate & Truth Table:

112
 S’R’ Latch
Circuit: INVALID Mode
• The analysis of a SR
Flip Flop NAND:
• S = 0, R = 0; This
condition tries to set
and reset the NAND
gate latch at the
same time.
• It produces Q = Q’ =1
113
 S’R’ Latch
Circuit: INVALID Mode
• This is an unexpected condition,
since the two outputs should be
inverses of each other.
• If the inputs are returned to 1
simultaneously, the output
states are unpredictable.
• This input condition should not
be used and when circuits are
constructed, the designer should
make sure that this condition.
S=R=0 never arises.
It is called INVALID/ PROHIBITED
114
 S’R’ Latch
Circuit: INVALID Mode

115
 Latch
• Consists of two cross-coupled NAND gates.
• 2 active low inputs and 2 outputs []

19EC302: Digital System Design 116

Timing diagram for S’R’ LATCH
FUNCTION OF SEQUENTIAL LOGIC
• Solution:
 SR Latch
• SR with active HIGH input

• S’R’ with active LOW input

 Gated SR Latch
• Constructed by adding two Controller NAND
gates to the

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19EC302: Digital System Design 121
RS flip-flop

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SR flip-flop

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Symbol of SR flip-flop

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 Gated D Latch
• Designed to eliminate the forbidden input
problem
• Single input D and two outputs []

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D flip-flop

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Symbol of D flip-flop

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19EC302: Digital System Design 128
Clocked JK Flip Flop

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Truth Table

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19EC302: Digital System Design 131
Clocked T-Flip Flop

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Truth Table

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Timing diagram

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 Master-Slave Flip-Flops
• Also known as pulse-triggered flip-flops

• Necessary in case where it is necessary to sense current state

while allowing new state information to be entered.

• It consists of two cascaded sections.

• First section is the master and the second is the slave

• Information is entered into the master on one edge or level of

a control signal and is transferred to the slave on the next

edge or level of control signal

19EC302: Digital System Design 135
 Master-Slave JK Flip-Flop

• In this J corresponds to S and K corresponds to R inputs.

• J=K=1 causes the flip-flop to toggle from the current

state.
– If present state is 1 then next state is 0

– If present state is 0 then next state is 1

• In this 2 AND gates are used to sense and steer the

state of the slave [in addition to SR MS flip-flop]
19EC302: Digital System Design 136
Master-Slave JK Flip-Flop

19EC302: Digital System Design 137

Master Slave Flip Flop using NAND gates

19EC302: Digital System Design 138

19EC302: Digital System Design 140
Timing Diagram for JK MS Flip-Flop

19EC302: Digital System Design 141

 Triggering

• Triggering means making the circuit active [allow it to receive

inputs]
• Triggering makes a circuit synchronous
• Triggering is given in the form of clock or gate signal
• Depending on the type of triggering used circuit becomes active at
specific states of clock pulse
– Level Triggering: Circuit becomes active when gating or clock
pulse is at a particular level
– Edge Triggering: Circuit becomes active at the negative edge or
positive edge of the clock signal
19EC302: Digital System Design 142
 Edge Triggered Flip-Flops
• Uses just one of the edges of the control to affect the
reading of information on input lines.
• Designed to use either the positive or negative edge
of the clock.
• Once triggering edge occurs the flip-flop remains
unresponsive to information input changes until the
next triggering edge.
19EC302: Digital System Design 143
 Positive Edge Triggered D Flip-Flop
• Setting or Resetting of the flip-flop is
established by the rising, or positive, edge of
the control signal.

19EC302: Digital System Design 144

• NAND gates 5 and 6 serve as an latch

• Assume C = 0

– Regardless of input at D, the outputs of NAND gates 2 and 3 are 1.

– Assume D = 0. NAND4 output is 1 causing output of NAND1 to be 0.

• If clock goes from 0-to-1 [+ve edge], all three inputs to NAND3 become 1,

causing its output to change to 0.

• NAND2 output is maintained at 1 as NAND1 output is still 0.

• The Flip-Flop is reset.

• As NAND3 output is fedback to input of NAND4, any subsequent change in D

while C=1 has no effect.

19EC302: Digital System Design 145

• Assume C = 0

– Regardless of input at D, the outputs of NAND gates 2 and 3 are 1.

– Assume D = 1. NAND4 output is 0 causing output of NAND1 to be 1.

• If clock goes from 0-to-1 [+ve edge], both inputs to NAND2 become 1,

causing its output to change to 0.

• NAND3 output is maintained at 1 as NAND4 output is still 0.

• The Flip-Flop is set.

• As NAND2 output serves as input of NAND1 and NAND3, any subsequent

change in D while C=1 has no effect.

19EC302: Digital System Design 146

19EC302: Digital System Design 147
Negative Edge Triggered D Flip-Flop
• Falling edge is used to sample the D input .
• Achieved by using an inverter at the control
input of the flip-flop.

19EC302: Digital System Design 148

• NAND gates 5 and 6 serve as an latch

• Assume C = 1

• Regardless of input at D, the outputs of NAND gates 2 and 3 are 1.

• Assume D = 0. NAND4 output is 1 causing output of NAND1 to be 0.

• If clock goes from 1-to-0 [-ve edge], all three inputs to NAND3 become

1, causing its output to change to 0.

• NAND2 output is maintained at 1 as NAND1 output is still 0.

• The Flip-Flop is reset.

• As NAND3 output is fedback to input of NAND4, any subsequent

change in D while C=0 has no effect.

• Assume C = 1

• Regardless of input at D, the outputs of NAND gates 2 and 3 are 1.

• Assume D = 1. NAND4 output is 0 causing output of NAND1 to be 1.

• If clock goes from 1-to-0 [-ve edge], both inputs to NAND2 become

1, causing its output to change to 0.

• NAND3 output is maintained at 1 as NAND4 output is still 0.

• The Flip-Flop is set.

• As NAND2 output serves as input of NAND1 and NAND3, any

subsequent change in D while C=0 has no effect.

Draw the timing diagram for negative edge
triggered D flip flop