5.high Cov

Tessent: Scan and ATPG
Module 5
Achieving High Test

Coverage
Objectives
Upon completion of this module, you will be able to:
 Apply ATPG pattern types to relevant circuits.

 Apply techniques to improve test coverage.
 Use QuestaSim to simulate and verify the following Verilog
testbenches:
 Serial and parallel.
 Chaintest.
 Pattern sample.
 Save patterns in various formats: ASCII, Verilog, and WGL.
 Read in and perform fault simulation on an external pattern.
5-2 • Tessent: Scan and ATPG: Achieving High Test Coverage Copyright © 1999-2009 Mentor Graphics Corporation
ATPG Run
 For initial run, use fault sampling to provide the following:
 Quick estimate of coverage for a large circuit.
 Creates a smaller pattern set for simulation.
– Detects problems early.
 Use The SET FAult Sampling command to specify a
percentage (between 0 and 100) of the total faults you want
processed.
ATPG> SET FAult Sampling 1

ATPG> CREate PAtterns
ATPG> REPort STatistics
ATPG> SAVe PAtterns <FILENAME1.v> -Verilog -Parallel
ATPG> SET PAttern Filtering –SAMple 2
ATPG> SAVe PAtterns <FILENAME2.v> -Verilog -Serial
Using an External Fault List
 Use the LOAd FAults command to place faults from an
external file into the internal fault list.
Retains original faults

in the fault list.
ATPG> LOAd FAults <-FILENAME> -Retain

ATPG> SET FAult Protection ON
ATPG> REPort STatistics //verify initial coverage (optional)
ATPG> CREate PAtterns
ATPG> REPort STatistics //shows total coverage
Adding NOfaults
 Use the ADD NOfault command to place nofault settings on
the following:
 Pin pathnames.
 Pin names of:
– specified instances.
– Modules.
 Issue the ADD NOfaults command in setup mode before
using the ADD FAults command.
 Specified pin pathnames and pins names will not
become fault sites.
 If design was previously flattened, using the ADD NOfault
command will delete the flattened model.
The tool loses all information added after flattening,

such as ATPG functions and constraints.
ATPG Test Pattern Types
 Tessent FastScan and Tessent TestKompress generate the
following test pattern types:
 Basic Scan
– Used on full-scan design circuitry
 Clock Sequential
– Used to propagate values through non-scan latches and DFFs with
limited sequential depth
 RAM Sequential
– Used to propagate values through RAM
 Multi Load
– Used on RAM/ROM designs that contain non-scan cells
 MacroTest
– Used to test the cell array of small embedded memories
 Clock PO
– Used on circuitry where a clock signal passes through combinational
logic to a primary output
Basic Scan Patterns
 The following apply to basic scan patterns:
 Generated by default.
 Use appropriate test procedures to define control and
observation of scan cells.
 Independent from each other.
 ATPG Expert chooses the best settings for ATPG.
 Use create patterns to use ATPG Expert.
 Analyzes and selects best pattern types for circuit.
Basic Scan Patterns (Cont.)
 Basic scan patterns contain the following events:
1. Load scan chain (many cycles)
2. Force primary inputs (PI)
3. Measure primary outputs (PO) Capture cycle
4. Pulse capture clock

Capture
5. Unload values from scan cells Cycle
– Load next pattern
Measure PO
capture clock
Force PI
Pulse
Load Scan Chain
CLK
….
SE
PIs X
X
PO
Basic Scan Pattern Operation
 Load Initialization procedure first.
LOAD
 Load values into the scan cells. FORCE PI
1. Force SE to “1” (scan enable). MEASURE PO
2. Force SI (scan chain input pin). PULSE CAPTURE
CLK.
3. Pulse shift clock.
4. Repeat steps 2 and 3 until all scan cells are loaded.
1st Shift
1st Shift
A
Y
B SE
SI
CLK
011 1 SO
SI D Q D Q D Q
1
SE 1
CLK
Basic Scan Pattern Operation (Cont.)
 Load values into the scan cells. LOAD
1. Force SE to “1”. FORCE PI
2. Force SI. MEASURE PO
3. Pulse shift clock. PULSE CAPTURE
CLK.
4. Repeat steps 2 and 3 until all scan cells are loaded.
2nd Shift 2nd

1st Shift
Shift
A
Y
B SE
SI
CLK
011 SI
1 D Q
1 D Q D Q SO
1 1
SE 1
CLK
 Load values into the scan cells.
LOAD
1. Force SE to “1”.
FORCE PI
2. Force SI.
MEASURE PO
3. Pulse shift clock. PULSE CAPTURE
4. Repeat steps 2 and 3 until all scan cells are loaded. CLK.
3rd Shift 1st 2nd 3rd
Shift Shift Shift

A
Y
B SE
SI
CLK
011 0 D Q
1 D Q
1 D Q SO
SI
0 1 1 LOAD
SE 1
CLK
 Force primary inputs.
LOAD
 Force normal primary inputs. FORCE PI
 Force SE to “0” (exits shift mode). MEASURE PO
– Now all internal values can be predicted. PULSE CAPTURE
CLK.
1
A 1 1 1 1
1 Y SE
B 1 0 1 1
A
Force PI
D Q SO
SI D Q D Q
0 1 1
SE
0
CLK
 Measure primary outputs.
LOAD
 Measure “1” on Y.
FORCE PI
MEASURE PO
PULSE CAPTURE
CLK.
1
A 1 1 1 1
1 1 Y SE
B 1 0 1 1
A
D Q SO
SI D Q D Q
Y
0 1 1
Measure PO
SE
0
Force PI
CLK
 Pulse Capture Clock.
LOAD
 Loads scan cells with functional inputs
FORCE PI
to observe circuit status. Capture
MEASURE PO
Cycle
PULSE CAPTURE
CLK.
1
A 1 1 1 1 CLK
1 1 Y SE
B 1 0 1 1
A
SO B
SI D Q D Q D Q
1 1 1
Y
Pulse capture
Measure PO
SE
0
Force PI
CLK
CLK
Capture Cycle
 Unload the scan chain. LOAD/UNLOAD
 As new data is being shifted into the scan chain during FORCE PI
load serially, the previous internal circuit state is being shifted out
MEASURE PO
serially shifted out and measured at scan out (SO). PULSE CAPTURE
CLK.
LOAD/
UNLOAD
1st 2nd 3rd
Shift Shift Shift

A
Y
B SE
LOAD
SI
CLK
101 1 D Q
0 D Q
1 D Q 111
SI
SO
1 0 1 SO UNLOAD
SE 1
CLK
Previous internal state Measure_sco
of scan cells measured
at scan out
Clock Sequential Patterns
 ATPG Expert automatically picks which pattern type to use.
 Recommended: let ATPG Expert choose.
– CREate patterns command will apply appropriate pattern type to circuit
 Can also manually select Clock Sequential patterns using SET
PAttern Type
 Command turns off other pattern types and creates clock sequential
patterns only.
 The following apply to Clock Sequential patterns:
 Test through scan-based designs that contain limited non-scan
sequential logic or non-scan latches.
 The tool reports non-scan logic as tie-x by default.
Clock Sequential Patterns (Cont.)
 The following apply to Clock Sequential patterns:
 Two ways to create clock sequential patterns:
– APTG Expert (recommended).
– Using the SET PAttern Type command.
 Use the following commands to generate clock sequential patterns.
– Use in conjunction with the create patterns command in atpg
mode.
SETUP> SET PAttern Type -SEquential 2
 Setting the sequential depth to a number greater than 1 enables
clock sequential patterns.
 “Clock sequential depth” defines the number of non-scan cells
connected in series that Tessent FastScan/Tessent TestKompress
can test through.
 Clock sequential patterns contain the following events:
1. Load scan chains.
2. Apply clock sequential cycle.
a. Force PIs.
b. Pulse clock.
c. Repeat a and b up to “N” times, where N is the “sequential depth -1”.
3. Apply capture cycle.
a. Force PIs.
b. Measure PO.
c. Pulse capture clock.
4. Unload values from scan cells.
Clock sequential
Measure PO
Force PI
Force PI
Capture pulse
A
Y
pulse
B
Non-scan
logic CLK Scan Chain
Load
D Q D Q D Q SO
SI
SE
SE PIs X
CLK
PO X
SETUP> SET PAttern Type -Sequential 2
Clock Sequential Capture Cycle

Clock sequential depth Cycle
 The higher the depth, the more processing time

 Best to let ATPG Expert pick
 Depth > 5 not recommended
Clock Sequential Pattern Operation
 Load values into the scan cells.
Unknown
A Load Scan Chain

Y
B
1st 2nd
CLK
SO
00 SI D Q D Q D Q
0 X 0
1
SE SE
CLK
Initialized Unknown Initialized
Clock Sequential Pattern Operation (Cont.)
 Apply clock sequential cycle.
a. Force primary inputs.
Force PIs
Clock sequential
A0 1
pulse
0 Load Scan Chain
Y
B1
1
Known input 0 CLK

X
1 SE
D Q SO
SI D Q D Q
0 X 0 A X
0 B X
SE
CLK
Clock Sequential
Cycle
 Apply clock sequential cycle.
b. Pulse clock.
c. Repeat a and b up to “N” times, where N
is the sequential depth –1.
Force PIs
Clock sequential
X is clocked out of the
scan chain and placed on
1 1 the input of the OR gate.
A0 0
Y
pulse
B1 Load Scan Chain
1
X CLK
X
1 SO
SI D Q D Q D Q SE
0 1 X
A X
0
SE B X
CLK
Clock Sequential
Clock sequential pulse Cycle
captures data into
non-scan cell.
 Apply capture cycle.
a. Force PI.
X or’d with a 1
resolves to 1
Clock sequential
Measure PO
Force PI
Force PI
Capture pulse
1
1 1 1
A1 1 1 Y
B1
pulse
1 Load Scan Chain
CLK
SO
SI D Q D Q D Q
SE
0 1 X
0 PIs X
SE
CLK
PO X
Cycle
a. Force PI.
b. Measure PO. 1 is measured
on the PO
Clock sequential
Measure PO
Force PI
Force PI
Capture pulse
1
1 1 1
A1 1 1
pulse
Y Load Scan Chain
B1
1
CLK
D Q SO SE
SI D Q D Q
0 1 X
PIs X
0
SE
CLK PO X
Cycle
a. Force PI.
b. Measure PO.
c. Pulse capture clock.
Clock sequential
Measure PO
Force PI
Force PI
Capture pulse
1
1 1 1
A1 1 1 Y
B1
pulse
1 Load Scan Chain
CLK
D Q SO
SI D Q D Q
SE
1 1 1
0 PIs X
SE
CLK
PO X
Cycle
 Unload values from scan cells.
 As new data is being shifted into the scan chain during load, the
previous internal circuit state is being shifted out and measured
at scan out (SO).
A Load Scan Chain

Y
B
1st 2nd
CLK
10 D Q D Q D Q
11
SI
SO
1 X 0
1
SE
SE
CLK
SI
RAM Sequential Patterns
 Recommended: let ATPG Expert choose.
 The following applies to RAM Sequential patterns:
 Targets faults associated with address and data lines.
 Automatically determines writes and reads to test logic around
memories.
 Single patterns with multiple loads.
– Load events include: two address writes and a read.
RAM Sequential Patterns (Cont.)
 RAM sequential patterns contain the following events:
1. Write to 1st address.
a. Load scan cells.
b. Force primary inputs.
c. Pulse write line(s).
2. Write to 2nd address.
– Repeat steps a through c for a different address.
3. Read 1st address.
– Load scan cells.
– Force primary inputs.
– Pulse read lines.
4. Capture read values.
– Load scan cells.
– Force primary inputs.
– Measure primary outputs.
– Pulse capture clock.
5. Unload values from scan cells.
 Do the following to generate RAM sequential patterns:
SETUP>ADD CLks 0 CLK
ADDR[0]
SETUP>ADD WRite Controls 0 RAMCLK
SETUP>ADD REad Controls 0 RAMCLK
D_OUT[0]
S-a- 0 D_OUT[1]
DQ
.
X ADDR[1] .
U1 ATPG>SET PAttern Type -RAM_sequential ON
RAM DQ
D_IN[0]
Scan_Out
IN1 D_IN[1]
RE Targets for RAM_
WE sequential patterns ATPG Expert creates
CLK CLK these patterns automatically.
Scan_In
RAMCLK
Targets for RAM_

sequential patterns
 RAM must be stable during LOAD/UNLOAD events.
 If the scan clock is used for RAM, read enable (RE) and write
enable (WE) must be off during shift.
ADDR[0]
D_OUT[0]
DQ
D_OUT[1]
ADDR[1]
U1
RAM DQ
D_IN[0]
Scan_Out
IN1 D_IN[1]
RE
Inserted test logic
WE
holds WE and RE off
CLK CLK
during shift.
Scan_In
RAMCLK
SE
RAM Sequential Patterns Example: Tests for Stuck-At-0 at
the Output of U1
 Do the following to test for S-a-0
ADDR[0]  Write data to 1st address.
D_OUT[0]
S-a- 0 D_OUT[1]
DQ ADDR [0] = 1
X ADDR[1] ADDR [1] = 1
U1
RAM DQ – Data In = 00
D_IN[0] – Address = 11
Scan_Out  Write different data to 2nd address.
IN1 D_IN[1] ADDR [0] = 1
RE ADDR [1] = 0 (target S-a-0)
WE – Data In = 11
CLK CLK – Address = 01
Scan_In
RAMCLK
 Read 1st address.
SE  Capture read values.
– Correct captured data will read 00
(ADDR [1] = 1)
– If U1 is S-a-0, captured data
will read 11
(ADDR [1] is stuck-at-0)
RAM Sequential Pattern Operation
1
 Write to 1st Address. 1 ADDR[0]
D_OUT[0]
S-a-0 DQ
a. Load scan chain. X
D_OUT[1]
X
1 ADDR[1]
1
b. Force PI. U1
RAM DQ
0 X
c. Pulse write lines. 1 D_IN[0]
Scan_Out
0
1 IN1 D_IN[1]
0
RE
1 WE
0
CLK CLK
Pulse write
Scan_In
RAMCLK
Force PI
SE
RAM CLK
SE
SI X X
CLK
IN1 X
Load Scan Chain
Address = 11 Data = 00
RAM Sequential Pattern Operation (Cont.)
1
 Write to 2nd address. 1 ADDR[0]
D_OUT[0]
a. Load scan chain. S-a-0 D_OUT[1] DQ
X ADDR[1] X
0
b. Force PI. U1
0
RAM DQ
1 X
c. Pulse write lines. 0 D_IN[0]
Scan_Out
1
0 IN1 D_IN[1]
0
RE
1 WE
0
CLK CLK
Scan_In
RAMCLK
SE
Pulse write
Force PI
RAM
CLK
Load Scan Chain
SE
SI X X
CLK
IN1 X
Write to 1st address Write to 2 nd address
 Read 1st address. 1
ADDR[0] 0
1
a. Load scan chain. S-a-0
D_OUT[0]
D_OUT[1]
DQ
b. Force PI. 1 X ADDR[1] 0 X

1
U1
RAM DQ
c. Pulse read lines. x
D_IN[0]
X
x
Scan_Out
x IN1 x
D_IN[1]
1
RE
0 WE
CLK 1
CLK
Scan_In
RAMCLK
SE
Pulse read
A “1” causes Data is now valid
Force PI
RE =1 at memory output
WE =0
RAM
CLK
Load Scan Chain Load Scan Chain
SE
SI X X X
CLK
IN1 X
Write to 1st address Write to 2nd address Read to 1 st address
 Capture read values. x
x
ADDR[0] 0
0
a. Load scan cells. S-a-0
D_OUT[0]
D_OUT[1]
DQ
X 0
b. Force primary inputs. x x ADDR[1] 0
U1
RAM DQ
c. Measure primary outputs. x
D_IN[0]
x
d. Pulse capture clock. x
Scan_Out
x IN1 D_IN[1]
x
RE
x WE
CLK x
CLK
RAMCLK
SE
Measure PO
Force PI
Pulse
capture
RAM clock
CLK
Load Scan Chain Load Scan Chain Load Scan Chain
SE
SI X X X X X X
CLK
IN1 X
PO X
Write to 1st address Write to 2nd address Read 1st address Capture Scan out read values
Multi Load Patterns
 Recommended: let ATPG Expert choose.
 The following apply to multi load patterns:
 Tests through RAM/ROM and sequential logic that contain
non-scan cells.
 Clock sequential patterns are generated to load scan chains and
non-scan cells without disturbing the logic state of the non-scan
cells.
 Optionally, writes and reads to test logic around memories.
 Two ways to create multiple load patterns:
– APTG Expert (recommended).
– Using the SET PAttern Type command.
 Use the following commands to generate multi load patterns.
– Use in conjunction with the create patterns command in atpg
mode.
– Turn off other pattern types if needed.
SETUP> SET PAttern Type -MULtiple_load ON -Sequential 4
Multi Load Patterns (Cont.)
 Multi load patterns contain the following events:
1. Load scan chains (optional after first time).
2. Force PIs.
3. Pulse sequential clock/write.
4. Repeat steps 1-3 and/or 2-3 up to “1 . . .N” times.
5. Apply capture cycle.
a. Force PI.
b. Measure PO.
c. Pulse clock.
6. Unload scan chains.
Multi Load Patterns Example
 This design requires the Non-scan logic
following multi load events:

1. Load scan chain.
2. Load non-scan cell. ADDR[0]
D_OUT[0]
a. Pulse non-scan clock (CLK2). CLK2 S-a-0
DQ
D_OUT[1]
3. Load scan chain. ADDR[1]
U1
4. Perform a write. RAM DQ
D_IN[0]
a. Pulse RAMCLK.
Scan_Out
5. Load scan chain.
IN1 D_IN[1]
6. Load non-scan cell with next
value and perform a write. RE
WE
a. Pulse CLK2 and RAMCLK. CLK1 CLK
7. Load scan chain. Scan_In
RAMCLK
8. Perform a read. SE
a. Pulse RAMCLK.
9. Capture data into scan cells.
a. Pulse CLK1.
10. Unload scan chains.
Multi Load Patterns Example (Cont.)
ADDR[0]
D_OUT[0]
DQ
CLK2 S-a-0 D_OUT[1]
ADDR[1]
U1 DQ
RAM
D_IN[0]
Scan_Out
IN1 D_IN[1]
RE
WE
CLK1 CLK
Scan_In
RAMCLK
SE
Clock Ram Load Clock Ram Clock Ram

Load Load Capture Unload
seq write seq write seq read
RAM CLK
CLK1 ... ... ... ...
CLK2
SE
Write Write Read
Generate Optimum Test Patterns Automatically
 Complete automated flow of pattern generation using one
command: create patterns
 Adds all faults.
 Creates all pattern types.
 Executes extensive analysis of design and DRC outcome.
 Finds compromise for
– Coverage, pattern count, and execution time.
 Considers RAMs, fault distribution, clock interactions, cost of
depth, cost of abort limit, pattern types, multi clock compression,
possible top-up runs, possible contention.
 Checks findings against user settings.
– Use –override to enable ATPG Expert to ignore user’s settings.
 Intercepts pattern generation and modifies parameters if
necessary.
 Performs automatic top-up run if necessary.
MacroTest Patterns
 Utility that helps automate the testing of embedded logic and
memories (macros) by automatically translating user-defined
patterns for the macros into scan patterns.
 User defines the pattern file and the instance to apply them to.
 No extra logic required.
 No performance impact.
 Restriction—patterns cannot be reordered.
MacroTest
Reproduced pattern input sequence Converted patterns ensure that the macro’s
is applied to the macro’s inputs output sequence is as specified
through the logic. in user-defined patterns.
Scan Patterns Scan Patterns

Tessent FastScan MacroTest
0 1
1 1 0 0
0 0
0 1
1 1 1 0
Logic
1
0
Macro 1
Logic
0 1
0
1
1
0
1 1
0 0
1 010001 0
01110101
MacroTest Vectors 01000010
10011100
(user defined) 10111000 MacroTest converts these
11110011
cycle-based patterns into
scan-based patterns.
ATPG> macrotest <instance> <pattern-file>
Clock Primary Output Patterns
 C8 and C9 DRC violations indicate that clock PO patterns can
be created.
 C8—rule violation occurs when a primary output is in the clock
cone.
 C9—rule violation occurs on a clock pin when a primary output is
in both the clock cone and the effect cone.
 The following apply to Clock Primary Output (PO) patterns:
 The tool generates clock PO patterns whenever it learns
that a clock connects to a primary output.
 Allows clocks to be active during force and measure events.
 Some testers cannot control clocks using clock PO patterns.
 Use the following command to prevent clock PO generation.
– SETUP> SET PAttern Type -CLockpo OFf
Clock Primary Output Patterns (Cont.)
 Clock PO patterns contain the following events:
1. Load values into the scan chain.
2. Force values on all primary inputs, including clocks
connected to primary outputs.
3. Measure all primary outputs that are connected to scan clocks.
Measure PO
Force PI
Load Scan Chain
LOGIC CLOUD
...
CLK ….
SI D Q
D D Q
D ...
D
SE
SE
1 ...
CLK C
1 PIs X
B
C X
Capture Cycle
Test Pattern Type Summary
CIRCUITRY PATTERN TYPES
BASIC CLOCK MULTI RAM CLOCK MacroTest
SEQ LOAD SEQ PO
FULL SCAN
RAMs/ROMs
RAM/ROM
SHAWDOW LOGIC
BLACK BOXES
BLACK BOX
SHADOW LOGIC
NONSCA
NIRCUITRY
C
NONSCAN
LATCHES TLA
SPECIAL (C8/C9)
Saving Patterns
 Save ATPG patterns in the following formats:
 Reuse and debugging.
– ASCII—ATPG > SAVe PAtterns <Filename> -Ascii
– Binary—ATPG > SAVe PAtterns <Filename> -Binary
• These pattern formats can be read back into the tool. Can also read WGL and
STIL files back into the tool too.
 Time-based verification.
– Verilog—ATPG > SAVe PAtterns <Filename> -Verilog
– VHDL—ATPG > SAVe PAtterns <Filename> -VHdl
• Allows user to independently verify test patterns with circuit timing.
 Manufacturing test (ATE) and diagnosis.
– WGL — ATPG > SAVe PAtterns <Filename> -Wgl
– STIL — ATPG > SAVe PAtterns <Filename> -STil
– Special tester formats
 Use .gz or .Z filename extension to save compressed files.
Reuse and Debugging
 The tool can write out a subset of patterns in any format.
 External patterns can be read back into Tessent FastScan/Tessent
TestKompress.
 Used for debugging (timing checks).
 Used for reuse (format translation).
 Failing pattern data from the tester can be read back into YieldAssist
to determine which set of faults match actual failures.
 Save a flattened model (netlist) when saving test patterns.
ATPG> SAVe FLattened Model filename
– Do not use HDL filename extensions such as .v or .vhd.
• Use an extension such as .flat instead.
– Use command only after design has been flattened.
• Design is flattened when attempting to exit SETUP mode or by issuing the FLAtten
MOdel command.
– Netlist is encrypted.
– Can also be password protected.
Reuse and Debugging: ASCII and Binary Formats
 ASCII is the default pattern format.
 Does not contain timing information.
 Fully commented and readable.
– Test procedures.
– Scan test procedures.
– Scan memory elements.
– Test coverage statistics.
 Binary format contains the same information as ASCII but is
in a condensed form.
 Used for archival purposes for large designs.
Reuse and Debugging: Reading ASCII Files Back Into
Tessent FastScan or Tessent TestKompress
 Do the following to read ASCII files back into the tool:
ATPG> SAVe PAtterns <testpat.ascii>
.
.
.
// Read external patterns
ATPG> SET PAttern Source External <testpat.ascii>
 Use .gz or .Z filename extension to automatically read

compressed file formats.
Time-Based Verification
 ATPG is event-based.
 Simulation using a time-based simulator validates patterns
with actual timing.
 Tessent FastScan/Tessent TestKompress writes events based
on specified timeplates in the test procedure file according to
timing requirements and tester specifications.
Time-Based Verification (Cont.)
 Do the following to enter procedure file timing information:
SETUP> ADD SCan Groups grp1 master.testproc
.
.
.
//timing in master.testproc
ATPG> SAVe PAtterns <testpat1.v> -Verilog -Parallel
//timing in new.testproc
ATPG> SAVe PAtterns <testpat2.v> -Verilog -Parallel \
-Procfile <new.testproc>
Verification of Pattern Formats
 Scan patterns and chain test.
 By default, test patterns contain a chain integrity test in addition to
the ATPG patterns.
 Chain test shifts a repeated data pattern through the scan chains.
 Chain test detects problems in the shift path.
 Parallel and serial patterns.
 Serial patterns behave as if applied by the tester (one clock cycle for
each shift).
 Parallel pattern values are directly applied to scan cell inputs to
speed up simulation (one clock cycle for all shifts).
 Verify all patterns in parallel format and a few in serial.
ATPG> SAVe PAtterns <testpat_p.v> -Verilog –Parallel
ATPG> SET PAttern Filtering –SAMple 2
ATPG> SAVe PAtterns <testpat_s.v> -Verilog -Serial
Manufacturing Test Patterns
 Many testers have special pattern formats.
 Tessent FastScan/Tessent TestKompress can save patterns
for ATE in specific formats and industry standard formats.
 WGL
 STIL
.
.
.
 User-defined pattern timing in the procedure file is based on
circuit timing and tester specifications.
Lab 5: Increasing Test Coverage With Patterns
During this lab, you will
 Apply pattern sequencing to achieve high test coverage.

 Save patterns in three formats:
 ASCII, Verilog, and WGL.
 Save patterns:
 Parallel patterns.
 Serial sample patterns.
 Chaintest patterns.
 Use ModelSim to simulate and verify the following
testbenches:
 Verilog.
– Parallel patterns.
– Serial sample patterns.
– Chaintest patterns.

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Tessent: Scan and ATPG

Achieving High Test

Upon completion of this module, you will be able to:

 Apply ATPG pattern types to relevant circuits.

ATPG> SET FAult Sampling 1

Retains original faults

ATPG> LOAd FAults <-FILENAME> -Retain

The tool loses all information added after flattening,

4. Pulse capture clock

 Load values into the scan cells. FORCE PI

1. Force SE to “1” (scan enable). MEASURE PO

2. Force SI (scan chain input pin). PULSE CAPTURE

1. Force SE to “1”. FORCE PI

2. Force SI. MEASURE PO

3. Pulse shift clock. PULSE CAPTURE

2nd Shift 2nd

3rd Shift 1st 2nd 3rd

Shift Shift Shift

– Now all internal values can be predicted. PULSE CAPTURE

Shift Shift Shift

of scan cells measured

Clock Sequential Capture Cycle

 The higher the depth, the more processing time

A Load Scan Chain

Initialized Unknown Initialized

Known input 0 CLK

Clock Sequential Capture Cycle

Clock Sequential Capture Cycle

Clock Sequential Capture Cycle

A Load Scan Chain

Targets for RAM_

b. Force PI. 1 X ADDR[1] 0 X

following multi load events:

Clock Ram Load Clock Ram Clock Ram

CLK1 ... ... ... ...

Write Write Read

Scan Patterns Scan Patterns

ATPG> macrotest <instance> <pattern-file>

 Use .gz or .Z filename extension to automatically read

 Apply pattern sequencing to achieve high test coverage.

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