DFT Training - 6 Occ

DFT TRAINING – 6 (OCC)
OCC CIRCUIT-1
OCC CIRCUIT-2
PURPOSE OF OCC
 OCC is the inserted logic on the SOC for controlling clocks during silicon testing on ATE(Automatic
Test Equipment).Since at-speed testing requires two clock pulses in capture mode with frequency equal
to the functional clock frequency. Without OCC we need to provide these at-speed pulses through I/O
pads. These pads has limitations in terms of maximum frequency which they can support.
 OCC uses internal PLL clock for generating clock pulses for test. During the OCC Stuck at Testing
ensures only one clock pulse is generated in the capture phase. Similarly, during at-speed testing, the
OCC ensures two clock pulses are generated in the capture phase, having a frequency equal to
frequency of the functional clock.
 Therefore, all the test clocks in a scan friendly design is routed through an OCC, which controls the
clock operation in scan mode (both in stuck-at and at-speed testing) and bypasses the functional clock
in functional mode. OCC is capable of enabling Fast clock or Slow clock based on Stuck at or At-
speed requirement.
 When the two inputs of AND Gate(i.e., Fast clock enable=1,PLL_bypass=0) then TEST
MODE=1,Flop1 EN=1,then Output of NAND Gate is '1'(Test Mode=1,PLL Bypass=0)fast clock is
enabled, then will get two clock pulses.
 When the two inputs of First OR Gate(i.e.Slow_clk_enable=1,PLL_bypass=0)
then Scan_enable=1,there by output of Second OR Gate is "1",when Test Mode=1,then three
input AND gate output will be '1',Slow Clock will get enabled, then will get one clock pulse.
OCC CIRCUIT-2 EXPLANATION
 From output of OR Gate of OCC Circuit2 is given as input to OCC Circuit1,then
based on requirement of the clock (i.e. either Fast clock or Slow Clock) can be
selected.
 To Enable the fast clock, fast_clk_enable is '1',Pll_bypass is '0',then the output of First
AND Gate is '0' and Test Mode=1,then Output of OR gate is '1' which enables Fast_clk
thereby giving one of the input as '1' to Second AND Gate. The other input is from
NAND Gate which has two inputs(Test Mode=1,Pll_bypass=0),then Output of NAND
Gate is '1' by making the Output of Second AND Gate is '1' which is given as
one Output to Main OR gate, the other input(Slow_clk) is '0' thereby enabling the Fast
Clock.
 To Enable the Slow clock, slow_clock_enable is '1',Pll_bypass is '0',the Output to first
OR gate is '1',For the Second OR gate, one input is Pll_bypass is '0' and other input
is scan_enable is '1',then output of OR gate is '1'.The three inputs to AND Gate are '1'
when Test_mode=1which enables slow_clock,this is given as one input to Main OR
gate, the other input is from fast_clock which will be '0' thereby enabling the Slow
OCC(On chip Clock Controller)
OCC
OCC(On chip Clock Controller)
 Both the flops(FF1 and FF2) are initially Reset condition.
 When Scan Enable is '1' ,the output of first AND gate is 1(Because output of
FF2 is 0(FF2 is in Reset Condition)),there by Slow Clock is enabled.
 When Scan Enable is '0' ,the output of first AND gate and FF1 is 0,the output of inverter
is 1,thereby the last flop output is connected as "1"to AND Gate(As same by using
counter and Decoder will get two pulses).
 And the FF1 output '0' is connected to Second AND gate, the output of FF2 is
1,thereby Fast Clock is Enabled.
OCC WAVEFORM
OCC INTEST
OCC EXTEST
OCC INTEST & EXTEST
 While considering the different Blocks Physically in the above slide figure, then for
example, Block 'A' and Block 'B' has its individual OCCs, then to put Block B in
INTEST Mode or activate OCC, Block 'A' should be kept in Transparent mode where
the Free Running clock will be activated. Block B INTEST will check internal
logic of Blocks.
 In Extest Mode, Block 'A' OCC will be programmed normally, and OCC of Block 'B'
will act as Buffer. In this Mode, Input Wrapper cells will have Shift and Capture
procedures.
 In Extest, Block'A' OCC works external logic circuit with free running clock and
Block 'B' will be in Transparent mode where the Free Running clock will be
activated.
 Free Running Clock implies Functional clock here. When Test Mode=1,then Fast
clock(PLL) will be enabled. Test Mode=0,then Functional Clock will be enabled.

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DFT TRAINING – 6 (OCC)

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