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Timing Diagram
Timing Diagrams
• Timing diagram is the display of initiation of read/write and transfer of data operations under the control of 3- status signals IO/M’, S1 and S0.
• Each machine cycle is composed of many clock cycles.
• The data and instructions, both are stored in the memory, the μP performs fetch operation to read the instruction or data and then execute the instruction.
• The 3-status signals: IO / M’, S1 and S0 are generated at the beginning of each machine cycle. The unique combination of these 3-status signals identifies read or write operation and remain valid for the duration of the cycle. Thus, time taken by any μP to execute one instruction is calculated in terms of the clock period.
• The execution of instruction always requires read and writes operations to transfer data to or from the μP and memory or I/O devices.
• Each read/ write operation constitutes one machine cycle. Each machine cycle consists of many clock periods/ cycles, called T-states. • During normal operation, the microprocessor sequentially fetches, decodes and executes one instruction after another until a halt instruction (HLT) is executed. • The fetching, decoding and execution of a single instruction constitutes an instruction cycle, which consists read or write operations between processor and memory or input/output devices. • Each memory or I/O operation requires a particular time period, called machine cycle. In other words, to move byte of data in or out of the microprocessor, a machine cycle is required.
• Each machine cycle consists of 3 to 6 clock periods/cycles, referred to as T-states.
Example: For the instruction MOV A, B, the 8085 microprocessor fetches the instruction from memory, decodes it, and then moves the content of register B into register A. This entire process is the instruction cycle.
For the same instruction MOV A, B, the machine cycle might involve fetching the instruction from memory. This would typically include an Opcode Fetch Machine Cycle, which is one machine cycle.
8085 microprocessor has 5 basic machine cycles.
• Opcode fetch cycle (4T) • Memory read cycle (3 T) • Memory write cycle (3 T) • I/O read cycle (3 T) • I/O write cycle (3 T) Microprocessor communication and bus timing Timing of data flow for the instruction code MOV C, A (instruction code 4FH), stored in location 2005H is fetched
Data flow from memory to MPU
Opcode fetch machine
Address and Data Busses
• The address bus has 8 signal lines A8 –
A15 which are unidirectional. • The other 8 address bits are multiplexed (time shared) with the 8 data bits. • So, the bits AD0 – AD7 are bi- directional and serve as A0 – A7 and D0 – D7 at the same time. • During the execution of the instruction, these lines carry the address bits during the early part, then during the late parts of the execution, they carry the 8 data bits. • In order to separate the address from the data, we can use a latch to save the value before the function of the bits changes. • When ALE goes low, the address is saved and the AD7– AD0 lines can be used for their purpose as the bi- Address and data bus with control signal Memory Read and write machine cycle
Opcode fetch and
Memory read machine cycle Continue…..
Opcode fetch and
Memory read and Memory write machine cycle Practice questions
