COMPUTER

ORGANIZATION AND
SOFTWARE SYSTEMS
SESSION
Prepared By: Prof. 7
Lucy J Gudino
BITS Pilani Instructor: Pradeep H K
Pilani Campus
 CISC Instruction Set
(Intel x86 as an
example)
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Pilani Campus
Today’s Session

Contac List of Topic Title Text/Ref

Book/external
t Hour
resource
• Instruction Set Architecture - CISC T1, R1
13-14 • CISC Instruction Set (Intel x86 as an example)
Machine Instruction Characteristics, Types of
Operands, Types of Operations, Addressing
Modes, Instruction Formats
• Control Unit Design
Hardwired vs microprogrammed control unit

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CPU Architecture
# RISC CISC
1. Reduced Instruction Set Computer. Complex Instruction Set Computer.
2. Small instruction set of uniform length. Hundreds of instructions of different sizes.
Instructions are executed in one clock
3. Takes one or more clock cycle
cycle.
4. Relatively simple to design. Complex to design.
5. Inexpensive. Relatively expensive.
Examples: Intel architecture(x86 and x64)
6. Examples: SPARC, POWER PC, ARM
AMD.
7. Less number of instructions. More number of instructions.
8. Fixed-length encodings for instructions Variable-length encodings of instructions.
9. Simple addressing formats Complex addressing modes.
10. Doesn't support arrays. Supports arrays.
11. I t doesn't use condition codes. Condition codes are used.

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BITS Pilani, Pilani Campus
Example code XCHG AL,LIST[SI]
MOV LIST[SI-1],AL
; Assembly program for Bubble Sort
.MODEL SMALL NEXT: LOOP NXTCOMP
.STACK DEC BX
.DATA JNZ NXTPASS
LEA DX,MSG
LIST DB 03H,034H,02H,01H,05H MOV AH,09H
N DW $-LIST INT 21H
ORDER EQU 0 ;implies ascending MOV BX,N
order
MOV SI,00H
MSG DB 'THE SORTED ARRAY IS:: $'
.CODE
AGAIN: MOV AL,LIST[SI]
MOV AX,@DATA
ADD AL,'0'
MOV DS,AX
MOV DL,AL
MOV BX,N
MOV AH,02H
DEC BX
INT 21H
NXTPASS: MOV CX,BX
MOV AH,02H
MOV SI,00H
MOV DL,' '
NXTCOMP: MOV AL,LIST[SI]
INT 21H
INC SI
INC SI
CMP AL,LIST[SI]
DEC BX
IF ORDER EQ 0 ;ascending
JNZ AGAIN
JB NEXT
MOV AH,4CH
ELSE ;descending
INT 21H
JA NEXT
END
ENDIF
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Introduction
• What is an Instruction Set?
• The complete collection of instructions that are
understood by a CPU
• Elements of an Instruction
• Operation code (Op code)
• Source Operand reference
• Result Operand reference
• Next Instruction Reference
• Source and Destination Operands can be found in four areas
• Main memory (or virtual memory or cache)
• CPU register
• I/O device
• Immediate
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Simple Instruction Format

• During instruction execution, an instruction is read into

an instruction register (IR) in the processor.
• The processor must be able to extract the data from the
various instruction fields to perform the required
operation.
• Opcodes are represented by abbreviations, called
mnemonics

Example: ADD AX, BX  Add instruction BITS Pilani, Pilani Campus

Instruction Types
• Data processing : Arithmetic and logic
instructions
• Data storage (main memory) : Movement of data
into or out of register and or memory locations
• Data movement (I/O) : I/O instructions
• Program flow control : Test and branch
instructions

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Number of Addresses (1/2)

• 3 addresses
– Result, Operand 1, Operand 2
– c = a + b; add c, a, b
– May be a forth - next instruction (usually
implicit)
– Needs very long words to hold everything
• 2 addresses
– One address doubles as operand and result
– a = a + b : add a, b
– Reduces length of instruction
– The original value of a is lost.

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Number of Addresses (2/2)

• 1 address
– Implicit second address
– Usually a register (accumulator)
– Common on early machines
• 0 (zero) addresses
– All addresses implicit
– Uses a stack
– e.g. c = a + b
push a
push b
add
pop c
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Example

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Address space: The amount of usable memory
allocated for program or process

Addressability: The way in which computer

identifies different memory locations.

Word-addressable: Refers to a memory unit

whose size is equal to "word", usually one byte
and pointed by a single binary address

Addressing mode: Refers to the way in which the

operand of an instruction is specified
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How Many Addresses
• Fewer addresses
– More Primitive instructions, shorter length instructions
– Less complex instructions, hence requires less complex
hardware
– More instructions per program
• Longer programs
• More complex programs
• Longer execution time
• Multiple address instructions
– Lengthy instructions
– More registers
• Inter-register operations are quicker
– Fewer instructions per program

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Instruction set Design Decisions

• Operation repertoire
– How many ops?
– What can they do?
– How complex are they?
• Data types
• Instruction formats
– Length of op code field
– Number of addresses
• Registers
– Number of CPU registers available
– Which operations can be performed on which
registers?
• Addressing modes BITS Pilani, Pilani Campus
Instruction set Design Decisions

• Operation repertoire
– How many ops?
– What can they do?
– How complex are they?
• Data types
• Instruction formats
– Length of op code field
– Number of addresses
• Registers
– Number of CPU registers available
– Which operations can be performed on which
registers?
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Types of Operand
• Machine instructions operate on data
• General categories of data
• Addresses
• Numbers
• Binary integer or binary fixed point, floating
point, decimal
• Characters
• ASCII etc.
• Logical Data Binary Representation
• Bits or flags 32 16 8 4 2 1
1 0 0 1 0 0
• Packed Decimal
• 36 : 0011 0110
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Byte Ordering

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x86 Data Types
• General – Byte, Word, double word, quadword, double
quad word - arbitrary binary contents
• Integer – signed binary using two’s complement
representation
• Ordinal - unsigned integer
• Unpacked BCD - One digit per byte
• Packed BCD - 2 digits per byte
• Near Pointer – 16/32 bit offset within segment
• Far pointer - 16/32 bit offset outside segment
• Bit field : A contiguous sequence of bits in which the
position of each bit is considered as an independent
unit.
• Bit and Byte String
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BITS Pilani, Pilani Campus
x86 Numeric Data Formats

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Types of Operation
• Data Transfer
• Arithmetic
• Logical
• Conversion
• I/O
• System Control
• Transfer of Control

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Data Transfer
• Specify
– Source
– Destination
– Amount of data
• Action:
1. Calculate the memory address, based on the address
mode
2. If the address refers to virtual memory, translate from
virtual to real memory address.
3. Determine whether the addressed item is in cache.
4. If not, issue a command to the memory module.

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Arithmetic
• Add, Subtract, Multiply, Divide
• May include
– Absolute value (|a|)
– Increment (a++)
– Decrement (a--)
– Negate (-a)
• Signed Integer

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Logical
• Bitwise operations
• AND, OR, NOT

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Shift and Rotate Operations
Input
Input Operation
Operation Output
Output
10101101
10101101 Logical
Logical right
right shift
shift (3 10101101=>
bits)
(3 bits) 00010101

10101101
10101101 Logical
Logical left
left shift
shift (3 10101101=>
bits)
(3 bits) 01101000

10101101
10101101 Arithmetic
Arithmetic right
right shift 10101101=>
shift (3 bits)
(3 bits) 11110101

10101101
10101101 Arithmetic
Arithmetic left
left shift
shift (3 10101101=>
(3 bits)
bits) 11101000

10101101
10101101 Right
Right rotate
rotate (3 bits) 10101101=>
(3 bits) 10110101
10101101
10101101 Left
Left rotate
rotate (3 bits) 10101101=>
(3 bits) 01101101

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Conversion
E.g. Binary to Decimal

(1101)2 to ( ? )10 = 1 * 23 + 1 * 2 2 + 0 * 2 1 + 1 * 2 0
=1*8 +1*4 +0*2 +1*1
=8+4+1
= 13

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Input/Output
• May be specific instructions (I/O-Mapped I/O)
• May be done using data movement instructions
(memory mapped)
• May be done by a separate controller (DMA)

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Systems Control
• Privileged instructions
• CPU needs to be in specific state
– User Mode
– Kernel mode
• For operating systems use

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Transfer of Control
• Jump / Branch (Unconditional / Conditional)
– e.g. jump to x if result is zero
• Skip (Unconditional / Conditional)
o skip (unconditional) : Increment to skip next
instruction
– e.g. increment and skip if zero
ISZ Register1
Branch xxxx
ADD A
• Subroutine call
• interrupt call

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Branch / Jump Instruction

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Use of Stack

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Addressing Modes
• Addressing modes refers to the way in which the
operand of an instruction is specified
• Types:
• Immediate
• Direct
• Indirect
• Register
• Register Indirect
• Displacement (Indexed)
• Stack

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BITS Pilani, Pilani Campus
Address space: The amount of usable memory
allocated for program or process
Addressability: The way in which computer
identifies different memory locations.
Word-addressable: Refers to a memory unit
whose size is equal to "word", usually one byte
and pointed by a single binary address
Addressing mode: Refers to the way in which the
operand of an instruction is specified

Address space tells you how many distinct locations there are
Addressability tells you how many bits are stored in each location.

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Immediate
Addressing
• Operand is specified in the instruction itself
• e.g. ADD #5
– Add 5 to contents of accumulator
– 5 is operand
• No memory reference to fetch data
• Fast
• Limited range

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Direct Addressing
• Address of the operand is specified in
the instruction
• Effective address (EA) = address field
(A)
• e.g. ADD A
– Add contents of memory cell whose
address is A to accumulator
– Look in memory at address A for
operand
• Single memory reference to access
data
• No additional calculations to work out
effective address
• Limited address space BITS Pilani, Pilani Campus
Indirect Addressing
• Memory cell pointed to by
address field of the
instruction contains the
address of (pointer to) the
operand
• EA = (A)
– Look in A, find address
and look there for operand
• e.g. ADD (A)
– Add contents of cell
pointed to by contents of
A to accumulator

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Indirect Addressing…
• Large address space
• 2n where n = word length
• May be nested, multilevel, cascaded
– e.g. EA = (((A)))
• Multiple memory accesses to find operand
• Slower

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Register Addressing
• Operand is held in register named in
address filed
• EA = R
• Limited number of registers
• Very small address field needed
– Shorter instructions
– Faster instruction fetch
• No memory access hence Very fast
execution but very limited address space
• Multiple registers helps in improving
performance
– Requires good assembly programming or
compiler writing
– C programming : register int a; BITS Pilani, Pilani Campus
Register Indirect Addressing

• Similar to indirect addressing

• EA = (R)
• Operand is in memory cell
pointed to by contents of
register R
• Large address space (2n)
• One memory access
compared indirect
addressing

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Displacement
Addressing
• EA = A + (R)
• Address field hold two
values
– A = base value
– R = register that
holds displacement
– or vice versa
• Three variants:
• Relative addressing
• Base register
addressing
• Indexing
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Relative Addressing
• Also known as PC relative addressing
• A version of displacement addressing
• R = Program counter, PC
• EA = A + (PC)
• Relative addressing exploits the concept of
locality
• If most memory references are relatively near
to the instruction being executed, then the use
of relative addressing saves address bits in the
instruction.

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Base-Register
Addressing
• The referenced register “R” contains a main
memory address
• address field contains a displacement A
• R may be explicit or implicit
• e.g. segment registers in 80x86

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Indexed Addressing
• The address field references a main memory
address A
• The referenced register R contains a positive
displacement from that address.
• EA = A + R
• Good for accessing arrays
– EA = A + R
– R++

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Auto Indexing
• Auto indexing incase certain registers are devoted
exclusively to indexing
EA = A + (R)
(R)  (R) + 1
Example: LODSB : Load byte at DS:[SI] into AL. Update SI.
AL = DS:[SI]
SI is incremented or decremented based on direction flag.
D = 0  increment SI
D = 1  decrement SI
• Two types:
• Postindex
• Preindex
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 Post-indexing

• indexing is performed after the indirection

EA = (A) + (R)
• Steps:
1. The contents of the address field are used to access
a memory location containing a direct address.
2. Address is then indexed by the register value
• Use:
• for accessing one of a number of blocks of data of a
fixed format

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Pre-indexing

• An address is calculated as with simple indexing

EA = (A + (R) )
• Use:
• to construct a multiway branch table

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Stack Addressing
• Operand is (implicitly) on top of stack
• e.g.
– ADD Pop top two items from stack and add,
push
the result on stack top

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x86 Addressing Modes

Virtual or effective address is offset into segment

– Starting address plus offset gives linear address
– This goes through page translation if paging enabled
12 addressing modes available
– Immediate
– Register operand
– Displacement
– Base
– Base with displacement
– Scaled index with displacement
– Base with index and displacement
– Base scaled index with displacement
– Relative

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x86 Addressing Mode
Calculation

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Instruction Formats

• Layout of bits in an instruction

• Includes opcode
• Includes (implicit or explicit) operand(s)
• Usually more than one instruction format in an
instruction set

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Instruction Length

Affected by and affects:

– Memory size
– Memory organization
– Bus structure
– CPU complexity
– CPU speed
Trade off between powerful instruction repertoire
and saving space

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Allocation of Bits

• Number of addressing modes

• Number of operands
• Register versus memory
• Number of register sets
• Address range
• Address granularity

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 Control Unit Design
Prepared By: Prof. Lucy J Gudino
BITS Pilani Instructor: Pradeep H K
Pilani Campus
Control Unit implementation

Hardwired control unit (RISC) – ARM processor

Microprogrammed control unit(CISC) – Intel

processor

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Hardwired Implementation (1)
• Control unit inputs
• Flags and control bus
• Each bit means something
• Instruction register
• Op-code causes different
control signals for each
different instruction
• Unique logic for each op-
code
• Clock
• Time efficient

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Problems With Hard Wired Designs

• Complex sequencing & micro-operation logic

• Difficult to design and test
• Inflexible design
• Difficult to add new instructions

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Microprogrammed Control Unit

• A computer executes a program

• Fetch/execute cycle
• Each cycle has a number of steps
• Called micro-operations
• Each step does very little
• Atomic operation of CPU

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Constituent Elements of
Program Execution

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Example: Fetch Sequence

T1: MAR  (PC)

T2: MBR  (memory)
PC  (PC) +1
T3: IR  (MBR)

OR

T1: MAR <- (PC)

T2: MBR <- (memory)
T3: PC <- (PC) +1
IR <- (MBR)

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Example: Execute Cycle (ADD)

Different for each instruction

e.g. ADD R1,X - add the contents of location X to
Register 1 , result in R1

T1: MAR  (IRaddress)

T2: MBR  (memory)
T3: R1  R1 + (MBR)

Note: no overlap of micro-operations

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Instruction Cycle
• Each phase decomposed into sequence of
elementary micro-operations
• E.g. fetch, indirect, and interrupt cycles
• Execute cycle
– One sequence of micro-operations for each
opcode
• Need to tie sequences together
• Assume new 2-bit register
– Instruction cycle code (ICC) designates which
part of cycle processor is in
• 00: Fetch
• 01: Indirect
• 10: Execute
• 11: Interrupt BITS Pilani, Pilani Campus
Flowchart for Instruction Cycle

ICC : Instruction cycle code BITS Pilani, Pilani Campus

Functions of Control
Unit
• The control unit performs two basic tasks:
– Sequencing
• Causing the CPU to step through a series of
micro-operations
– Execution
• Causing the performance of each micro-op
• This is done using Control Signals
Example: ADD R1, X
t1: MAR  (PC) t4: MAR  (IRaddress)
t2: MBR  (memory)
t5: MBR  (memory)
PC  (PC) +1
t6: R1  R1 + (MBR)
t3: IR  (MBR)

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Control Signals
• Inputs to the control unit
– Clock
• One micro-instruction (or set of parallel micro-
instructions) per clock cycle
– Instruction register
• Op-code for current instruction
• Determines which micro-instructions are
performed
– Flags
• State of CPU
• Results of previous operations
– From control bus
• Interrupts
• Acknowledgements
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Microprogrammed Control Unit

• Use sequences of micro-

instructions to control
complex operations called
micro-programming or
firmware

• Firmware is midway between

hardware and software

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Organization of
Control Memory

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