Module 4

AVLSI
Procedural statements and routines
• Procedural Statements
System verilogadapts many satements from C and C++
Such as i) For loop and restricting the loop variables
ii) post and pre increament/decreament
iii) giving label to start and end procedure
iv) Continue : if ina loop we want to exit from that iteration and
start new iteration.
v) Break: leave the loop immediately.
Tasks, Functions, and Void
Functions
• Verilog : function and task are different , main difference is task can consume time function .
• A function can not have delay like - #100 , blocking statement like @(posedge clock) or wait (ready) or call a
task.
• A Verilog function must return a value and the value must be used as in an assignment statement.

• In System Verilog-
• If function return value you want to ignore cast it to void.

• Task that does not consume time should be made a void function.

• For Max flexibility any debug routine should be void function rather than a task
So that it can be called from task or function.
Task and function overview
• Routines begin….. end removed
The task/end Task and function/end function keywords are enough to
define routine boundaries.
Routine Arguments
Many of the SystemVerilog improvements for routine make it easier to
declare arguments and expand the ways you can pass values to and
from a routine.
• C style routine arguments
• Arguments direction
• Advanced argument types
• Default Argument values
• Common coding errors
C style routine arguments
SystemVerilog and Verilog-2001 allow you to declare task and function
arguments more cleanly and with less repetition
Argument Direction
You can take even more shortcuts with declaring routine arguments.
The direction and type default to “input logic” and are sticky, so you
don’t have to repeat these for similar arguments
Advanced arguments types
In SystemVerilog, you can specify that an argument is passed by
reference, rather than copying its value. This argument type, ref, has
several benefits over input, output, and inout. First, you can now pass
an array into a routine.
With the const modifier the array a is
initialized when print_sum is called,
but cannot be modified in the routine.
Always use ref when passing arrays to a
routine. If you don’t
want the routine to change the array
values, use the const
ref type. With this, the compiler checks
that your routine does
not modify the array.
The second benefit of ref arguments is that a task can modify a variable and is instantly seen
by the calling function. This is useful when you have several threads executing concurrently
and want a simple way to pass information.
Default argument Values
As your testbench grows in sophistication, you may want to add additional controls
to your code but not break existing code.
However, you don’t want to go back and rewrite every call to add extra arguments.
In SystemVerilog you can specify a default value that is used if you leave out an
argument in the call
Common Coding Errors
The most common coding mistake that you are likely to make with a routine is forgetting that
the argument type is sticky with respect to the previous argument, and that the default type for
the first argument is a single-bit input
The two arguments are input integers. As you are writing the
task, you realize that you need access to an array, so you add a
new array argument, and use the ref type so it does not have to
be copied.
Returning from a Routine
SystemVerilog adds the return statement to make it easier for you to control the flow in your routines. The
following task needs to return early because of error checking. Otherwise, it would have to use an else clause,
that would cause more indentation and be harder to read.
Local Data Storage -Automatic storage ,Variable
initialization
When Verilog was created in the 1980s, its primary goal was describing hardware. Because of this, all objects in the language
were statically allocated.
In particular, routine arguments and local variables were stored in a fixed location, rather than pushing them on a stack like
other programming

However, software engineers who were used to the behavior of stack-based languages such as C were bitten by these subtle
bugs, and were limited in their ability to create complex testbenches with libraries of routines

Automatic storage

In SystemVerilog, routines still use static storage by default, for both modules and program blocks.

Always make program blocks (and their routines) use automatic storage by putting the automatic keyword in the program
statement
 Automatic storage

You can call this task multiple times concurrently, as the addr and expect_data arguments are stored separately for each call.
Without the automatic modifier, if you called wait_for_mem a second time while the first was still waiting, the second call
would overwrite the two arguments.
 Variable initialization
The following task looks at the bus after five cycles and then creates a local variable and attempts to initialize it to the current
value of the address bus.

The bug is that the variable local_addr is

statically allocated, so it is actually initialized
at the start of simulation, not when the
begin...end block is entered. Once again, the
solution is to declare the program as
automatic
 Time Values
Time units and precision Time literals
• When you rely on the ‘timescale compiler directive, you
SystemVerilog allows you to unambiguously specify a
must compile the files in the proper order to be sure all the time value plus units. Your code can use delays such as
delays use the proper scale and precision. 0.1ns or 20ps. Just remember to use timeunit and
• The timeunit and timeprecision declarations eliminate
timeprecision or ‘timescale. You can make your code
this ambiguity by precisely specifying the values for every even more time aware by using the classic Verilog
module. Example 3-22 shows these declarations. Note that if $timeformat and
you use these instead of ‘timescale, you must put them in $realtime routines
every module that has a delay.