BY RAJESH

INTRODUCTION
VHDL is a Hardware Description Language. Ovedr the years, HDLs have evolved to help electronic designers in the following tasks a) Describing digital systems b) Modeling digital systems c) Designing digital systems

The VHDL language can be used with several goals in mind i) To synthesize digital circuits ii) To verify and validate digital designs iii) To generate test vectors to test circuits iv) To simulate circuits

VHDL is an acronym of VHSIC Hardware Description Language VHSIC is an acronym of Very High Speed Integrated Circuits It is founded by United States Department Of Defense in the 1980s. VHDL-87 VHDL-93 IEEE-1076 IEEE-1164 VHDL describes the behavior of an electronic system,from which we can attained the physical system. It is intended for circuit simulation and synthesis. It can be used for sequential behavior as well as concurrent behavior. It is strongly typed language. The main application of VHDL are in FPGA,CPLDS, ASICS.

CONCURRENCY
VHDL is a concurrent language???? This concurrency is achived by event driven simulation as VHDL is event driven. This means that all components of design are executed concurrently whenever there is a event on the ports of a component. Here order of execution is not important. The main concurrent body is architecture and other concurrent blocks exist in the architecture. Components instantiated within an architecture and all sub-blocks and subcomponents within this component are considered concurrent

Example entity co_n is Port ( a,b,c,d : in STD_LOGIC_VECTOR (3 downto 0); y : out STD_LOGIC_VECTOR (3 downto 0)); end co_n; architecture Behavioral of co_n is signal a1,a2,a3 : std_logic_vector(3 downto 0); begin a3 <= d and a2; // each a,b,c,d, values are assignee a2 <= a1 and c; after 10 ns; y <= a1 and a3; a1 <= a and b; end Behavioral;

SEQUENTIAL

Sequentiality refers to the statements that are executed one after another. Here orde is important. VHDL provides sequential bodies(process block,functions,procedures) within which sequential statements are used.

The sequential bodies which describe sequential behavior are runs in parallel with other sequential bodies.
The delta delay is an internal simulation time for VHDL simulator.

It hide us from the fact that assignments and processing are done sequentially but it make us to appear as if concurrent assignements are really done concurrently.

BASIC DESIGN METHODOLOGY

RTL Model

Simulate

Synthesize

Gate-level Model

Simulate

Test Bench

ASIC or FPGA

Place & Route

Timing Model

Simulate

CODE STRUCTURE
LIBRARY

ENTITY

Basic Vhdl Code

ARCHITECTURE

FUNDAMENTAL PARTS OF LIBRARY

FUNCTIONS PROCEDURES COMPONENTS CONSTANTS TYPES

LIBRARY
Library ieee; Use ieee.std_logic_1164.all; Use ieee.std_logic_arith.all; Use ieee.std_logic_signed.all; Use ieee.std_logic_unsigned.all; Libraries are repositories of frequently used design entities that we wish to share. The library clause identifies a library we wish to access. Here the library name is IEEE, but in practice it will probably map to some directory on your local system. This directory will contain various design units that have been compiled, e.g. a package (which contains definitions of types, functions, or procedures to be shared by multiple application developers (users).

The use clause determines which package or design units in a library will be used in the current design. e.g. in the above description, the clause states that in library IEEE there is a package named std_logic_1164 and that we can use all the components defined in this package. We need this package because the definition for the type std_ulogic is in this package. SYNTEX: LIBRARY LIBRARY_NAME; USE LIBRARY_NAME . PACKAGE_NAME.PACKAGE_PARTS e.g -> ieee.std_logic_1164(from ieee library), -> standard (from std library) -> work (from work library)

ENTITY
It is the interface for communication among different modules / components and define the signal port modes (INPUT and OUTPUT) Entity name should be same as the file name

Entity name

Input 1 Input 2 ... Input n

Output 1 Output 2 ... Output n

This is a black box that implemented by the statements in Architecture

Entity declaration describes the input/output ports of a module

entity reg4 is port ( d0, d1, d2, d3, en, clk : in bit; q0, q1, q2, q3 : out bit ); end entity reg4;

punctuation

reserved words

port type

ARCHITECTURE
An architecture defines a body for a component entity An architecture body specifies a behavior between inputs and outputs The architecture name is not the same as the component name. The architecture declaration part must be defined before first begin and can consist of, for example:

types subprograms components signal declarations

ARCHITECTURE
Define functionality of the chip X <= A AND B; Y <= C AND D; E <= X OR Y; SYNTAX OF THE ARCHITECTURE
architecture <architecture_name> of <entity_identifier> is [<architecture_declarative_part>] begin <architecture_statement_part> -- The body of the arch. end [architecture] [<architecture_name>];

A B C D

Chip
X Y E

The word architecture in the last line is not supported before the VHDL-93 standard

THE MODE OF THE PORT

DATA TYPES
bit values: '0', '1' boolean values: TRUE, FALSE integer values: -(231) to +(231 - 1)

std_logic values: 'U','X','1','0','Z','W','H','L','-' U' = uninitialized 'X' = unknown 'W' = weak 'X 'Z' = floating 'H'/'L' = weak '1'/'0 '-' = don't care

Std_logic_vector (n downto 0); Std_logic_vector (0 upto n);

DESIGN DESCRIPTION METHODS

Structural Description Method: expresses the design as an arrangement of interconnected components

It is basically schematic

Behavioral Description Method: describes the functional behavior of a hardware design in terms of circuits
The hardware behavior is described algorithmically No architecture is required here

Data-Flow Description Method: is similar to a registertransfer language

This method describes the function of a design by defining the flow of information from one input or register to another register or output

DATAFLOW CODE
Dataflow code is also called concurrent code. It refers the statements which are declared outside the processes,functions or procedures. They are when statement (when/else,with/select/when, generate statement(for , if), blocks (simple block,and guarded block). Other and unaffected(when no action takes place) keyword. Syntex : ->When /else : assign when condition else .; -> with/select/when: with identifier select assignement when value, ;

o o

If generate/for generate: label1: for identifer in range generate label2 : if condition generate (concurrent assignements) end generate; end generate; Simple block /Guarded block Simple block is self contained within the main code.It is locally partioning the code. syntex: label:block {declarative part} begin {concurrent statements} end block label;

Guarded block : It is a special kind of block.It includes a guarded expression. A guarded statements in guarded block is executed only when the guard epression is true. It can be used to construct sequential circuits. Syntex : label: block (guard expression) {declarative part } begin { concurrent guarded and unguarded statements} end block label;

SEQUENTIAL CODE
Sequential code is also called behavioral code. Processes, functions and procedures, are the only sections of code that executed sequentially. Sequntial code can be used to build both sequential circuits as well as combinational circuits. Process: it is characterized by the presence of IF ,WAIT, CASE or LOOP and by a sensitivity list (except when wait is used) -> it is executed every time a signal in the sensitivity list changes. syntex [label:] process (sensitivity list) {variable declaration}; begin {sequential code} ; end process[label] ;

IF Syntex: if condition then assignements ; elsif condition then assignements; else assignements; end if; WAIT:The wait statements explicitly specify the conditions under which a process may resume execution after being suspended. The forms of the wait statement include a) wait for time expression; b) wait on signal; c) wait until condition; d) wait; Process should not have sensitivity list when wait empmoyed.

Loop : There are 2 kinds of loop statements, i) for loops, and ii) while loops. o for loop syntex: -> [label:] for identifier in range loop {sequential statements} end loop; o while loop syntex: -> [label:] for condition loop {sequential statements} end loop; o EXIT : used for ending of loop. Syntex : [label:] Exit [label] [when condition]

NEXT : used for skipping loop steps. Syntex : [label:] next [loop_label] {when condition};

CASE Syntex : -> case identifier is when value => assignements ; when value => assignements; end case -> OTHERS and NULL (when nonaction takes place) keyword.
o

GENERIC
Generic is useful to pass certain types of information (like rise and fall delays, the size of the interface ports) Generics declares a constant object of mode in (i.e the vlaue can only be read ) . It can be used in the entity declaration and its corresponding architecture bodies(component declaration , component instantiation,configuration declaration , configuration specification. Syntex : generic (parameter_name:parameter_type := parameter_value); e.g generic(n:integer := 8); o Synetex for during component instantiations: comp-lb: comp_nm[generic map(generic- association-list)][port map(port-association list)]; e.g a1:a_na generic map (6) port map(a,b,y);

CONFIGURATION

Configurations are used to organize top-level entity in terms of lower level entites by specifying the bindings between the entites. It is used to bind the desired architecture to the entity and a component to the desired entity. This binding is done in two ways: By using a configuration specification( binding a component to the desired entity). By using a configuration declaration(binding an entity to the desired architecture).

CONFIGURATION SPECIFICATION

It binds a component to the desired entity(inside the architecture). e.g component g

y : out STD_LOGIC);
end component; for n1:g use entity work.inv1 (behave);-- port map (a=>a,y =>y); // inv1 is an inverter, g is a buffer , for n2,n3,n4: h use entity work.nand_behave(behave); signal sbar,asel,bsel: std_logic; // nand_baheve is an nand , h is an and gate // after binding g act as a inverter and h as a nand gate.

Begin
n1: g port map (sel,sbar); n2: h port map (a,sbar,asel); n3: h port map (b,sel,bsel); n4: h port map (asel,bsel,y);

CONFIGURATION DECLARATION

A configuration declaration is a seprate design unit.It is declared outside the architecture body.
It is used to bind the desired architecture to an entity or component defined in the block(architecture body, generate statement or block statement) to desired entity. One entity can have more than one configuration declaration.

SUBPROGRAMS
It defines sequential algorithm that performs a certain computation. It allows decomposition of large behaviors into modular sections. There are two types of subprogram: Functions: -> it is used to return a single value by using return construct. -> it executes in zero simulation time . -> it is only used for combinational circuits. -> its parameter restricted to mode inonly(only read) Syntex : function function_name(parameter-list) return return type.

e.g
function mux_2_1(x,y,s:in std_logic) return std_logic is variable z : std_logic; begin case s is when '0' => z := x; when '1' => z := y; when others => z := '0'; end case; return z; end mux_2_1; begin y(0) <= mux_2_1(a(0),b(0),sel(0)); y(1) <= mux_2_1(a(1),b(1),sel(1));

Procedures: -> It is used to return zero or more then one value using parameters mode out and inout . -> It is used for both combinational and sequential circuits. -> It may executes in non zero simulation time. Syntex : procedure procedure-name (parameter-list);

e.g

procedure dff( signal a,clock,reset : in std_logic ; signal o : out std_logic) is

begin
if(reset = '1')then o <= '0'; elsif(clock'event and clock = '1')then o <= a;

end if;
end dff; begin dff(din,clk,rst,dout);

UNDERSTANDING DELAYS
An accurate representation of digital circuit behavior requires an accurate modeling of delays thru the components. There are several delay models in VHDL, e.g. Inertial Delay Model,Transport Delay Model, Delta Delay Model. a) The Inertial Delay Model It takes a gate a finite amount of time and a certain amount of energy for the output of a gate to respond to a change on the input. This means that the change on the input has to persist for a certain period of time to ensure that the output will respond.

This propagation delay model is called the inertial delay model, and is the default delay model for VHDL programs. E.g Out1 is the output waveform for delay = 8 ns. Out2 is the output waveform for delay = 2 ns. If the gate delay is 8 ns, then any pulse on the input signal of duration less than 8 ns will not be propagated to the output, e.g. Out1. If the gate delay is 2 ns, then since each pulse in the input waveform is greater than 2 ns, it will be propagated to the output, e.g. Out2.

Input

8 ns
Out1 Out2 2 ns 5 10 15 20 25 30 35 input

OR

output

Syntex : signal <= reject time-expression inertial value-expression after time-expression e.g sum <= reject 2 ns inertial (a xor b) after 5 ns; b) The Transport Delay Model Signals propagate through wires at a finite rate and experience delays proportional to the distance. In modern electronics, the wire delays dominate, so designs need to minimize wire length. Wire delays are non negligible, so need to be modeled to produce accurate simulations of circuit behavior. These delays are called transport delays. To specify to VHDL a transport delay, use sum <= transport (a xor b) after 5 ns;