Digital System

Design
VERILOG® HDL
TASKS AND FUNCTIONS
Introduction
Procedures/Subroutines/Functions in SW programming languages
◦ The same functionality, in different places

Verilog equivalence:
◦ Tasks and Functions
◦ Used in behavioral modeling
◦ Part of design hierarchy  Hierarchical name

12/29/23 VERILOG HDL 2

Functions
Keyword: function, endfunction
Can be used if the procedure
◦ does not have any timing control constructs
◦ returns exactly a single value
◦ has at least one input argument

12/29/23 VERILOG HDL 3

Functions (cont’d)
Function Declaration and Invocation
◦ Declaration syntax:

function <range_or_type> <func_name>;

<input declaration(s)>
<variable_declaration(s)>
begin // if more than one statement needed
<statements>
end // if begin used
endfunction

12/29/23 VERILOG HDL 4

Functions (cont’d)
Function Declaration and Invocation
◦ Invocation syntax:
<func_name> (<argument(s)>);

12/29/23 VERILOG HDL 5

Functions (cont’d)
Semantics
◦ much like function in Pascal
◦ An internal implicit reg is declared inside the function with the same name
◦ The return value is specified by setting that implicit reg
◦ <range_or_type> defines width and type of the implicit reg
◦ <type> can be integer or real
◦ default bit width is 1

12/29/23 VERILOG HDL 6

 Function Examples
Parity Generator
module parity; function calc_parity;
reg [31:0] addr; input [31:0] address;
reg parity; begin
calc_parity = ^address;
initial begin end
… endfunction
end
endmodule
always @(addr)
begin
parity = calc_parity(addr);
$display("Parity calculated = %b",
calc_parity(addr) );
end

12/29/23 VERILOG HDL 7

 Function Examples
Controllable Shifter
module shifter; function [31:0] shift;
`define LEFT_SHIFT 1'b0 input [31:0] address;
`define RIGHT_SHIFT 1'b1 input control;
reg [31:0] addr, left_addr, begin
right_addr; shift = (control==`LEFT_SHIFT) ?
reg control; (address<<1) : (address>>1);
end
initial endfunction
begin
… endmodule
end

always @(addr)
begin
left_addr =shift(addr, `LEFT_SHIFT);
right_addr =shift(addr,`RIGHT_SHIFT);
end
12/29/23 VERILOG HDL 8
//Define a factorial with a recursive
function // Call the function
module top; integer result;
... initial
// Define the function begin
function automatic integer factorial; result = factorial(4); // Call
input [31:0] oper; the factorial of 7
integer i; $display("Factorial of 4 is
begin %0d", result); //Displays 24
if (operand >= 2) end
factorial = factorial (oper -1) * oper; ...
//recursive call ...
else endmodule
factorial = 1 ;
end
endfunction

12/29/23 VERILOG HDL 9

Tasks and Functions

TASKS
 Tasks
Keywords: task, endtask
Must be used if the procedure has
◦ any timing control constructs
◦ zero or more than one output arguments
◦ no input arguments

12/29/23 VERILOG HDL 11

Tasks (cont’d)
Task declaration and invocation
◦ Declaration syntax

task <task_name>;
<I/O declarations>
<variable and event declarations>
begin // if more than one statement needed

<statement(s)>
end // if begin used!

endtask

12/29/23 VERILOG HDL 12

Tasks (cont’d)
Task declaration and invocation
◦ Task invocation syntax
<task_name>;
<task_name> (<arguments>);

◦ input and inout arguments are passed into the task

◦ output and inout arguments are passed back to the invoking statement
when task is completed

12/29/23 VERILOG HDL 13

Tasks (cont’d)
I/O declaration in modules vs. tasks
◦ Both used keywords: input, output, inout
◦ In modules, represent ports
◦ connect to external signals
◦ In tasks, represent arguments
◦ pass values to and from the task

12/29/23 VERILOG HDL 14

 Task Examples
Use of input and output arguments
task bitwise_oper;
module operation;
output [15:0] ab_and, ab_or,
parameter delay = 10; ab_xor;
reg [15:0] A, B; input [15:0] a, b;
reg [15:0] AB_AND, AB_OR, AB_XOR; begin
#delay ab_and = a & b;
initial ab_or = a | b;
$monitor( …); ab_xor = a ^ b;
initial end
begin endtask
…
end
always @(A or B) endmodule
begin
bitwise_oper(AB_AND, AB_OR,
AB_XOR, A, B);
end 12/29/23 VERILOG HDL 15
 Task Examples-Automatic tasks
Use of module local variables
// clk2 runs at twice the frequency of clk // These two always blocks will call
and is synchronous the bitwise_xor task
// with clk. // concurrently at each positive edge
module top; of clk. However, since
reg [15:0] cd_xor, ef_xor; //variables in
module top // the task is re-entrant, these
reg [15:0] c, d, e, f; //variables in concurrent calls will work
module top correctly.
- always @(posedge clk)
task automatic bitwise_xor;
bitwise_xor(ef_xor, e, f);
output [15:0] ab_xor; //output from the
task -
input [15:0] a, b; //inputs to the task always @(posedge clk2) // twice the
begin frequency as the previous block
#delay ab_and = a & b;
bitwise_xor(cd_xor, c, d);
ab_or = a | b;
ab_xor = a ^ b;
-
end -
endtask endmodule

12/29/23 VERILOG HDL 16

Tasks and
Functions
DIFFERENCES BETWEEN
TASKS AND FUNCTIONS
Differences between...
Functions Tasks
◦ Can enable (call) just ◦ Can enable other tasks and
another function (not task) functions
◦ Execute in 0 simulation ◦ May execute in non-zero
time simulation time
◦ No timing control ◦ May contain any timing
statements allowed control statements
◦ At lease one input ◦ May have arbitrary input,
◦ Return only a single value output, or inout
◦ Do not return any value

12/29/23 VERILOG HDL 18

Differences between…
(cont’d)
Both
◦ are defined in a module
◦ are local to the module
◦ can have local variables (registers, but not nets) and events
◦ contain only behavioral statements
◦ do not contain initial or always statements
◦ are called from initial or always statements or other
tasks or functions

12/29/23 VERILOG HDL 19

Differences between…
(cont’d)
Tasks can be used for common Verilog code
Function are used when the common code
◦ is purely combinational
◦ executes in 0 simulation time
◦ provides exactly one output

Functions are typically used for conversions and

commonly used calculations

12/29/23 VERILOG HDL 20