[RISCV] Mark More Fatal Errors as Usage/Internal #154876
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We have lots of uses of `report_fatal_error` in the backend, which will result in a crash and a backtrace. This API has been replaced with `reportFatalUsageError` and `reportFatalInternalError`, for which only the latter emits a stack trace. This tries to move the errors in RISCVISelLowering and RISCVRegisterInfo to the new APIs, to prevent some stack traces where we specificially do not support certain situations. Updates llvm#124132
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@llvm/pr-subscribers-backend-risc-v Author: Sam Elliott (lenary) ChangesWe have lots of uses of This tries to move the errors in RISCVISelLowering and RISCVRegisterInfo to the new APIs, to prevent some stack traces where we specificially do not support certain situations. Updates #124132 Full diff: https://github.com/llvm/llvm-project/pull/154876.diff 2 Files Affected:
diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
index 4a1db80076530..a7a9f0fcb954b 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -109,7 +109,7 @@ RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM,
switch (ABI) {
default:
- report_fatal_error("Don't know how to lower this ABI");
+ reportFatalUsageError("Don't know how to lower this ABI");
case RISCVABI::ABI_ILP32:
case RISCVABI::ABI_ILP32E:
case RISCVABI::ABI_LP64E:
@@ -7300,7 +7300,8 @@ SDValue RISCVTargetLowering::LowerOperation(SDValue Op,
SelectionDAG &DAG) const {
switch (Op.getOpcode()) {
default:
- report_fatal_error("unimplemented operand");
+ reportFatalInternalError(
+ "Unimplemented RISCVTargetLowering::LowerOperation Case");
case ISD::PREFETCH:
return LowerPREFETCH(Op, Subtarget, DAG);
case ISD::ATOMIC_FENCE:
@@ -7498,7 +7499,7 @@ SDValue RISCVTargetLowering::LowerOperation(SDValue Op,
// vscale as VLENB / 8.
static_assert(RISCV::RVVBitsPerBlock == 64, "Unexpected bits per block!");
if (Subtarget.getRealMinVLen() < RISCV::RVVBitsPerBlock)
- report_fatal_error("Support for VLEN==32 is incomplete.");
+ reportFatalInternalError("Support for VLEN==32 is incomplete.");
// We assume VLENB is a multiple of 8. We manually choose the best shift
// here because SimplifyDemandedBits isn't always able to simplify it.
uint64_t Val = Op.getConstantOperandVal(0);
@@ -8511,7 +8512,7 @@ SDValue RISCVTargetLowering::emitFlushICache(SelectionDAG &DAG, SDValue InChain,
SDValue RISCVTargetLowering::lowerINIT_TRAMPOLINE(SDValue Op,
SelectionDAG &DAG) const {
if (!Subtarget.is64Bit())
- llvm::report_fatal_error("Trampolines only implemented for RV64");
+ llvm::reportFatalUsageError("Trampolines only implemented for RV64");
// Create an MCCodeEmitter to encode instructions.
TargetLoweringObjectFile *TLO = getTargetMachine().getObjFileLowering();
@@ -8671,7 +8672,7 @@ SDValue RISCVTargetLowering::lowerINIT_TRAMPOLINE(SDValue Op,
SDValue RISCVTargetLowering::lowerADJUST_TRAMPOLINE(SDValue Op,
SelectionDAG &DAG) const {
if (!Subtarget.is64Bit())
- llvm::report_fatal_error("Trampolines only implemented for RV64");
+ llvm::reportFatalUsageError("Trampolines only implemented for RV64");
return Op.getOperand(0);
}
@@ -8806,7 +8807,7 @@ SDValue RISCVTargetLowering::getAddr(NodeTy *N, SelectionDAG &DAG,
switch (getTargetMachine().getCodeModel()) {
default:
- report_fatal_error("Unsupported code model for lowering");
+ reportFatalUsageError("Unsupported code model for lowering");
case CodeModel::Small: {
// Generate a sequence for accessing addresses within the first 2 GiB of
// address space. This generates the pattern (addi (lui %hi(sym)) %lo(sym)).
@@ -8984,7 +8985,7 @@ SDValue RISCVTargetLowering::lowerGlobalTLSAddress(SDValue Op,
if (DAG.getMachineFunction().getFunction().getCallingConv() ==
CallingConv::GHC)
- report_fatal_error("In GHC calling convention TLS is not supported");
+ reportFatalUsageError("In GHC calling convention TLS is not supported");
SDValue Addr;
switch (Model) {
@@ -10833,7 +10834,7 @@ SDValue RISCVTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op,
if (!isValidEGW(4, Op.getSimpleValueType(), Subtarget) ||
!isValidEGW(4, Op->getOperand(1).getSimpleValueType(), Subtarget) ||
!isValidEGW(4, Op->getOperand(2).getSimpleValueType(), Subtarget))
- report_fatal_error("EGW should be greater than or equal to 4 * SEW.");
+ reportFatalUsageError("EGW should be greater than or equal to 4 * SEW.");
return Op;
}
// EGS * EEW >= 256 bits
@@ -10841,7 +10842,7 @@ SDValue RISCVTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op,
case Intrinsic::riscv_vsm3me: {
if (!isValidEGW(8, Op.getSimpleValueType(), Subtarget) ||
!isValidEGW(8, Op->getOperand(1).getSimpleValueType(), Subtarget))
- report_fatal_error("EGW should be greater than or equal to 8 * SEW.");
+ reportFatalUsageError("EGW should be greater than or equal to 8 * SEW.");
return Op;
}
// zvknha(SEW=32)/zvknhb(SEW=[32|64])
@@ -10850,11 +10851,11 @@ SDValue RISCVTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op,
case Intrinsic::riscv_vsha2ms: {
if (Op->getSimpleValueType(0).getScalarSizeInBits() == 64 &&
!Subtarget.hasStdExtZvknhb())
- report_fatal_error("SEW=64 needs Zvknhb to be enabled.");
+ reportFatalUsageError("SEW=64 needs Zvknhb to be enabled.");
if (!isValidEGW(4, Op.getSimpleValueType(), Subtarget) ||
!isValidEGW(4, Op->getOperand(1).getSimpleValueType(), Subtarget) ||
!isValidEGW(4, Op->getOperand(2).getSimpleValueType(), Subtarget))
- report_fatal_error("EGW should be greater than or equal to 4 * SEW.");
+ reportFatalUsageError("EGW should be greater than or equal to 4 * SEW.");
return Op;
}
case Intrinsic::riscv_sf_vc_v_x:
@@ -22330,8 +22331,8 @@ RISCVTargetLowering::EmitInstrWithCustomInserter(MachineInstr &MI,
case TargetOpcode::STACKMAP:
case TargetOpcode::PATCHPOINT:
if (!Subtarget.is64Bit())
- report_fatal_error("STACKMAP, PATCHPOINT and STATEPOINT are only "
- "supported on 64-bit targets");
+ reportFatalUsageError("STACKMAP, PATCHPOINT and STATEPOINT are only "
+ "supported on 64-bit targets");
return emitPatchPoint(MI, BB);
}
}
@@ -22564,7 +22565,7 @@ SDValue RISCVTargetLowering::LowerFormalArguments(
switch (CallConv) {
default:
- report_fatal_error("Unsupported calling convention");
+ reportFatalUsageError("Unsupported calling convention");
case CallingConv::C:
case CallingConv::Fast:
case CallingConv::SPIR_KERNEL:
@@ -22588,17 +22589,17 @@ SDValue RISCVTargetLowering::LowerFormalArguments(
break;
case CallingConv::GHC:
if (Subtarget.hasStdExtE())
- report_fatal_error("GHC calling convention is not supported on RVE!");
+ reportFatalUsageError("GHC calling convention is not supported on RVE!");
if (!Subtarget.hasStdExtFOrZfinx() || !Subtarget.hasStdExtDOrZdinx())
- report_fatal_error("GHC calling convention requires the (Zfinx/F) and "
- "(Zdinx/D) instruction set extensions");
+ reportFatalUsageError("GHC calling convention requires the (Zfinx/F) and "
+ "(Zdinx/D) instruction set extensions");
}
const Function &Func = MF.getFunction();
if (Func.hasFnAttribute("interrupt")) {
if (!Func.arg_empty())
- report_fatal_error(
- "Functions with the interrupt attribute cannot have arguments!");
+ reportFatalUsageError(
+ "Functions with the interrupt attribute cannot have arguments!");
StringRef Kind =
MF.getFunction().getFnAttribute("interrupt").getValueAsString();
@@ -22614,11 +22615,12 @@ SDValue RISCVTargetLowering::LowerFormalArguments(
"SiFive-CLIC-preemptible-stack-swap",
};
if (!llvm::is_contained(SupportedInterruptKinds, Kind))
- report_fatal_error(
- "Function interrupt attribute argument not supported!");
+ reportFatalUsageError(
+ "Function interrupt attribute argument not supported!");
if (Kind.starts_with("qci-") && !Subtarget.hasVendorXqciint())
- report_fatal_error("'qci-*' interrupt kinds require Xqciint extension");
+ reportFatalUsageError(
+ "'qci-*' interrupt kinds require Xqciint extension");
if (Kind.starts_with("SiFive-CLIC-") && !Subtarget.hasVendorXSfmclic())
reportFatalUsageError(
@@ -22856,7 +22858,7 @@ SDValue RISCVTargetLowering::LowerCall(CallLoweringInfo &CLI,
if (CallConv == CallingConv::GHC) {
if (Subtarget.hasStdExtE())
- report_fatal_error("GHC calling convention is not supported on RVE!");
+ reportFatalUsageError("GHC calling convention is not supported on RVE!");
ArgCCInfo.AnalyzeCallOperands(Outs, CC_RISCV_GHC);
} else
analyzeOutputArgs(MF, ArgCCInfo, Outs, /*IsRet=*/false, &CLI,
@@ -22870,8 +22872,8 @@ SDValue RISCVTargetLowering::LowerCall(CallLoweringInfo &CLI,
if (IsTailCall)
++NumTailCalls;
else if (CLI.CB && CLI.CB->isMustTailCall())
- report_fatal_error("failed to perform tail call elimination on a call "
- "site marked musttail");
+ reportFatalInternalError("failed to perform tail call elimination on a "
+ "call site marked musttail");
// Get a count of how many bytes are to be pushed on the stack.
unsigned NumBytes = ArgCCInfo.getStackSize();
@@ -23196,7 +23198,7 @@ RISCVTargetLowering::LowerReturn(SDValue Chain, CallingConv::ID CallConv,
nullptr, CC_RISCV);
if (CallConv == CallingConv::GHC && !RVLocs.empty())
- report_fatal_error("GHC functions return void only");
+ reportFatalUsageError("GHC functions return void only");
SDValue Glue;
SmallVector<SDValue, 4> RetOps(1, Chain);
@@ -23262,7 +23264,7 @@ RISCVTargetLowering::LowerReturn(SDValue Chain, CallingConv::ID CallConv,
const Function &Func = DAG.getMachineFunction().getFunction();
if (Func.hasFnAttribute("interrupt")) {
if (!Func.getReturnType()->isVoidTy())
- report_fatal_error(
+ reportFatalUsageError(
"Functions with the interrupt attribute must have void return type!");
MachineFunction &MF = DAG.getMachineFunction();
@@ -24557,8 +24559,8 @@ RISCVTargetLowering::getRegisterByName(const char *RegName, LLT VT,
BitVector ReservedRegs = Subtarget.getRegisterInfo()->getReservedRegs(MF);
if (!ReservedRegs.test(Reg) && !Subtarget.isRegisterReservedByUser(Reg))
- report_fatal_error(Twine("Trying to obtain non-reserved register \"" +
- StringRef(RegName) + "\"."));
+ reportFatalUsageError(Twine("Trying to obtain non-reserved register \"" +
+ StringRef(RegName) + "\"."));
return Reg;
}
diff --git a/llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp b/llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp
index 440f6cfc39b54..f3966a55ce7d1 100644
--- a/llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp
+++ b/llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp
@@ -170,7 +170,7 @@ BitVector RISCVRegisterInfo::getReservedRegs(const MachineFunction &MF) const {
if (MF.getFunction().getCallingConv() == CallingConv::GRAAL) {
if (Subtarget.hasStdExtE())
- report_fatal_error("Graal reserved registers do not exist in RVE");
+ reportFatalUsageError("Graal reserved registers do not exist in RVE");
markSuperRegs(Reserved, RISCV::X23_H);
markSuperRegs(Reserved, RISCV::X27_H);
}
@@ -216,7 +216,7 @@ void RISCVRegisterInfo::adjustReg(MachineBasicBlock &MBB,
const int64_t NumOfVReg = Offset.getScalable() / 8;
const int64_t FixedOffset = NumOfVReg * VLENB;
if (!isInt<32>(FixedOffset)) {
- report_fatal_error(
+ reportFatalUsageError(
"Frame size outside of the signed 32-bit range not supported");
}
Offset = StackOffset::getFixed(FixedOffset + Offset.getFixed());
@@ -511,7 +511,7 @@ bool RISCVRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
Offset += StackOffset::getFixed(MI.getOperand(FIOperandNum + 1).getImm());
if (!isInt<32>(Offset.getFixed())) {
- report_fatal_error(
+ reportFatalUsageError(
"Frame offsets outside of the signed 32-bit range not supported");
}
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We have lots of uses of
report_fatal_errorin the backend, which will result in a crash and a backtrace. This API has been replaced withreportFatalUsageErrorandreportFatalInternalError, for which only the latter emits a stack trace.This tries to move the errors in RISCVISelLowering and RISCVRegisterInfo to the new APIs, to prevent some stack traces where we specificially do not support certain situations.
Updates #124132