[AVR] Refactor ADIW/SBIW/MOVW instruction descriptions (NFCI) #156876
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✅ With the latest revision this PR passed the C/C++ code formatter. |
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benshi001
reviewed
Sep 5, 2025
| uint64_t Address, | ||
| const MCDisassembler *Decoder) { | ||
| assert(isUInt<2>(RegNo)); | ||
| Inst.addOperand(MCOperand::createReg(GPRPairDecoderTable[12 + RegNo])); |
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It would be better to add a comment line, something like
Only AVR::R25R24, AVR::R27R26, AVR::R29R28, AVR::R31R30 are legal.
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* Remove custom decoders for these instructions * Instead, provide decoders for DREGS/IWREGS register classes * Change register pair encodings to simplify instruction descriptions
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